Research Review Integrated Systems Laboratory Microelectronics Design Center

Transcription

1 Eidgenössische Technische Hochschule Zürich Swiss Federal Institute of Technology Zurich Integrated Systems Laboratory Microelectronics Design Center Research Review 2008

2 Cover Image: MIMO 4-Stream Baseband Transceiver ASIC for IEEE n IEEE n is the most popular emerging standard for wireless local area networks. Compared to its predecessors (IEEE a/b/g), this new standard achieves larger range, better reliability, and up to 10x higher data rates. To achieve this significant improvement, IEEE n employs multiple-input multiple-output (MIMO) technology with up to four spatial streams. Unfortunately, the complexity of the baseband processing increases rapidly with the number of spatial streams. Hence, present commercial implementations of the standard support only up to two streams, employing 2 or 3 antennas. The application-specific integrated circuit (ASIC) developed in this research project is the worldwide first 4-stream IEEE n baseband transceiver. With 4 transmit and 4 receive antennas, the MIMO-OFDM modem reaches peak over-the-air data rates of up to 600 Mbps in 40 MHz bandwidth, or 289 Mbps in 20 MHz. To support the high number of transmission modes and to provide maximum flexibility for future extensions, the first two levels of hierarchy of the developed VLSI architecture are partitioned into two types of components: processing elements (PEs) perform signal processing but are mostly agnostic about the details of the standard. Data path controllers orchestrate the operation of the PEs. A handshake protocol controls the exchange of data between PEs and the exchange of commands and reports between datapath controllers and the associated PEs. Thanks to this structure, the timing of the data flow is com- The cover image shows the 4x4 MIMO Transceiver ASIC. Modern chip technologies provide rather unattractive chip photographs. In order to illustrate more details, two images have been overlaid over the chip micrograph: The first is a plot of the layout data with selected metal connections, all memories, and the PLL. The second indicates the contours of he most important building blocks. The layout constraints for optimal speed and area results lead to this arrangement realized by the automatic place-and-route tools. pletely self-organizing and individual PEs can easily be modified, exchanged, or added without the need to modify other blocks or the datapath controllers. The block diagram on the top right of this page shows the first level of hierarchy with 7 PEs and 2 datapath controllers. The PEs in the transmit data path handle the channel coding, the space-time coding, and the MIMO-OFDM modulation which is partially shared with the receiver to reduce silicon area. In the receive data path, the first PE controls the analog gain stages in the RF and performs various synchronization tasks. The subsequent MIMO-OFDM demodulation (shared with the transmitter) and the pilot tracker obtain the frequency-domain representation of the received signal and correct residual frequency and timing offsets. Next, the MIMO processing estimates the channel s frequency response and separates the spatially multiplexed data streams using a linear MMSE detector. Soft-information is then provided to the channel decoding which employs two 300 Mbps Viterbi decoders to recover the transmitted data. The above described architecture was implemented in a 130 nm CMOS technology, using a standardcell-based design methodology to facilitate process migration. In addition to the 1.1 M gate equivalents for the standardcells in the data path and the control logic, a total of 595 kbit of on-chip memory was used. This memory is distributed across 49 macro cells. A phase-locked-loop generates the 160 MHz and the 320 MHz internal clock signals from an external 80 MHz reference clock. The final layout of the circuit occupies a core area of 14.4 mm 2, which is comparable to the area required by commercial 2-stream implementations. Including the pads, the manufactured ASIC occupies an overall area of 25 mm 2. For more information, please look up pages 40ff. Address of the Laboratory: ETH Zürich Integrated Systems Laboratory ETZ J81 and J96 Gloriastr Zurich, Switzerland Phone: Fax: sekr@iis.ee.ethz.ch www: Visitor information: contacts visitors

3 Integrated Systems Laboratory Microelectronics Design Center Research Review 2008 Qiuting Huang Wolfgang Fichtner Bernd Witzigmann Hubert Kaeslin Norbert Felber Dölf Aemmer

4 Research in Physical Characterization Reconstruction of Scanning Electron Microscopy Images by Monte Carlo Simulation for Critical Dimension Measurement in Advanced CMOS Devices The International Roadmap for Semiconductors identifies the non-destructive Scanning Electron Microscopy (SEM) for the measurement of critical dimensions (CD) in technology nodes below 22 nanometers as a difficult challenge. Improved sensitivity and resolution, better discrimination, faster data acquisition and analysis are all characteristics that have to be addressed to reach the required uncertainty level of 0.06 nm by the year Accurate nano-metrology requires that the electron beam interactions and the signal comprising the SEM image be understood and modeled. For SEM and CD SEM in manufacturing, the primary problem today is not the necessarily the intrinsic resolution of the equipment but all image artifacts such as charging of the sample with the consequent deflection of the secondary electrons, as shown in Fig. 1. Despite their technological relevance, the models for the SE yield and for electron transport in dielectrics are still inaccurate. This is in particular the case of polymethylmethacrylate (PMMA) and SiO 2. Therefore new MC schemes and models have been developed recently to trace the trajectories of primary and secondary electrons down to the energy range of few milli-electronvolts. Figure 2 shows the SE yield in PMMA as calculated with this original MC code, which takes into account elastic scattering, electron-electron interactions, interactions with phonons, and electron trapping through polarons. The simplest models used in CD SEM to deconvolute the relationship between the sample and its image utilize no physics and simply assume that lines, gates, etc. are objects with sharp edges located where the bright edge bloom is visible in the SEM image. As shown in the MC simulation of Figure 3, with narrower lines and tighter tolerances, the bloom width is no longer negligible, such that locating the position of the line edge requires additional image processing. Fig. 1 Electrostatic potential build up in a SiO 2 via on the top of a Si substrate as a consequence of the fixed charges introduced in the dielectric by electron beam irradiation. At present, Monte Carlo (MC) simulation is still the most straightforward approach to the solution. A complete software package for the simulation of charging effects must include 1. several basic functions: the simulation of the electron interactions down to 1 ev energy within the sample. 2. transport and the recombination of the deposited charge within the dielectric. 3. a Poisson solver to calculate the electric field, as a function of the local charge distribution in the dielectrics and semiconductor. 4. a ray tracing code for the calculation of the trajectories of the secondary electrons exiting the sample surface and possibly reaching the detector. Experience has shown that the main limitations of existing simulation codes are due to the inaccuracy in the estimation of the yield of SE emerging from the surface of the sample. Fig. 3 Monte Carlo simulation at different primary beam energies of SEM linescans obtained for SiO 2 lines on the top of a Si substrate. Several approaches are pursued. The most popular make use of the model-based library methodology, where linescans acquired by SEM are compared with linescans simulated by a MC code in order to find out the bestmatching set of parameters to fit the experimental data. Unfortunately, taking into account a sufficient number of parameters easily turns into an unrealistic number of library entries to be pre-calculated. Alternative and faster solutions are explored, which base on the solution of the direct problem. As an example, suitable digital filters are used to process the experimental linescans to extract the features to be characterized, as shown in Fig. 4. Fig. 2 SE yield of PMMA as a function of the primary beam energy, for a normal incidence beam. The solid line represents the Monte Carlo calculations. Empty symbols are experimental data from different groups. Fig. 4 Digital processing (bottom) of the experimental linescans of three PMMA lines (top) by a properly calibrated wavelet filter to quantitatively extract upper linewidth. 2

5 Contents Preface 6 Announcement of Assistant Professor Andreas Burg 9 Organization 10 Representative Figures 11 Staff 15 Former PhD Students 17 Academic Guests 22 Partners and Funding Agencies 24 Awards 30 Patents 32 News 2008 and History of the Integrated Systems Laboratory (IIS) 33 Research Projects: IC and System Design and Test 35 Real-Time Multi-User MIMO-OFDM Testbed Improvements and Measurements 36 Real-time MIMO-OFDM Testbed Extension with SQRD-based MIMO Preprocessing 36 VLSI Architectures for Gram-Schmidt-based QR Decomposition 37 VLSI Architectures for QR Interpolation 37 Automatic Gain Control and Noise Estimation for MIMO-OFDM Testbed 38 Multi-User MIMO-OFDM Offline Testbed 38 2x2 MIMO-OFDM Baseband Processing on a Reconfigurable Processor 39 Matrix Preprocessing for MIMO-OFDM on the SOL Processor 39 A 4-Stream Baseband Transceiver ASIC for IEEE n 40 Verification Framework for Wireless Baseband Transceivers 40 Channel Matrix Preprocessing for IEEE n 41 Soft-Output Sphere Decoder for IEEE n 41 Configurable High-Throughput Decoder Architecture for Quasi-Cyclic LDPC Codes 42 VLSI Implementation of Max-Log M-BCJR Algorithms for Iterative MIMO Decoding 42 Finite Lattice-Size Effects in MIMO Detection 43 VLSI Implementation of the LLL Algorithm for MIMO Detection 43 SHA-3 Proposal BLAKE 44 EnRUPT Hash Function Specification 44 Hardware Characterization of Cryptographic Primitives 45 Fast AES Cipher Core on ASIC with New Cells based on CMOS and Pass-Transistor Logic 45 Research Projects: Analog and Mixed-Signal IC Design 46 High-Speed Pipelined A/D Converters in Deep-Submicron CMOS Technology 47 High-Speed Folding and Interpolating A/D Converters Employing Digital Calibration 47 Highly-Linear D/A Converters as a Building Block for High-Performance A/D Converters 48 A/D Conversion for Multi-Standard Wireless Receivers 48 Multi Band Transmitter Design for LTE Mobile Communications 49 Multi-Standard RF Receivers for Mobile Communications 49 Integrated Frequency Synthesizer for RF Multi-Mode Applications 50 A 58mW 1.2 mm 2 HSDPA Turbo Decoder ASIC 50 DC-DC Converters for Systems on Chip 51 Research Projects: Technology CAD 52 GIDL Suppression by Optimization of Junction Profiles in the 22 nm Technology Node 53 Simulation of Phonon Scattering in Silicon Nanowires 53 Limitations of the Effective Mass Approximation: A Specific Example 54 A Nonparabolicity Model compared to Tight-Binding 54 Ab-initio Calculations of Indium Clustering in Silicon 55 Extraction of Configurations and Diffusion Mechanisms from High Temperature Molecular Dynamics Simulations 55 Ab-initio Calculations of N-Type Dopant Clustering in Silicon 56 Ab-initio Calculations of Formation Energies for Fluorine Clusters in Silicon 56 Molecular Dynamics Simulations of Diffusion of Fluorine in Silicon 57 Kinetic Monte Carlo Model for Fluorine Diffusion and Clustering 57 Research Projects: Computational Optoelectronics Gbit/s-Capabilities of Directly Modulated VCSELs 59 AQUA: Electroluminescence in Nanostructures 59 3

6 Quantum Transport for Optoelectronics using NEGF 60 Comparison of Electroluminescence in Nanostructures of Different Dimensionalities 60 Polarization Effects in III-Nitride Structures 61 Strain-Engineering in InGaN/GaN Nanocolumn LEDs 61 Ellipticity and Operator Ordering in k p Calculations of III-Nitride Semicon-ductors 62 High Field Carrier Transport in III-V Heterolayer Structures 62 Characterization, Simulation and Analysis of Avalanche Photodiodes 63 Combined Analytical-FDTD Simulation of Mode-Locked VECSELs 63 Design of Electrically Pumped VECSELs 64 Optimization of the Electromagnetic Properties of 3rd Generation Nanowire Solar Cells 64 Research Projects: Physical Characterization 65 Reconstruction of Scanning Electron Microscopy SEM Images by Monte Carlo Simulation 66 Digital Processing of SEM Images for Line Width Measurements with Sub-Nanometer Uncertainty 66 Correction of Proximity Effects in Electron Beam Lithography Applications for 32 nm Structures and below 67 Monte Carlo Simulation of Electron Beam Cross-Linking Processes for Polymers 67 New Strategy for the On-Chip Screening of Gate Oxide Defects in Smart Power Devices 68 New Strategy for On-Chip Screening of Leakage Currents in LDMOS Transistors for Smart Power Devices 68 Multiscale Simulation for the Design of Highly-Reliable MEMS Devices 69 Design Methodology for CMOS and MEMS 69 Weak Coupling of Electric and Thermal Equations for Multiscale Simulation of Electronic Devices 70 Reliability of the Thermal Interfaces in Power Modules 70 Online and Offline Isolated Current Monitoring of Parallel Switched High-Voltage Multi-Chip IGBT 71 Lifetime Modeling and Prediction of Power Devices 71 Electro-thermal Simulation of Electron Devices by Behavioral Models in VHDL-AMS 72 Full Electro-Thermal Model of a 6.5kV Field-Stop IGBT Module 72 Packaging Reliability of Advanced Microelectronic Devices 73 Research Projects: Bio-Electromagnetics and Electromagnetic Compatibility 74 Numerical and Experimental Evaluation of the Thermal Load Caused by Cellphone-use by Adults and Children 75 Analysis of Age Dependent Anatomical and Biophysical Changes of the Exposure of Brain to Cellphone Radiation 75 Analysis of the Exposure of the Unborn Child to ELF and RF Fields in Uncontrolled Environments 76 Analysis of the Whole Body Exposure of Children with Respect to RF Safety Limits 76 Development of Standardized Techniques to Assess RF Induced Heating of Medical Implants during MRI Exams 77 Development of an Anatomical CAD Model of an Obese Adult Male 77 Experimental Evaluation of the SAR Induced in a Head Phantom of a Three Year Old Child 78 Full Wave SAR Assessment in Front of Representative Base Station Antennas 78 SAR Assessment from Mobile Phones Used with Wired and Wireless Hands-Free Kits 79 Dosimetric Assessment of Human Epidermis Exposed In Vitro to 900 MHz Electromagnetic Field 79 Dosimetric Assessment of C. elegans Exposed In Vivo to 900 MHz Electromagnetic Field 80 System to Study CNS Responses of ELF Modulation and Cortex Versus Subcortical RF Exposures 80 Evaluation of Artifacts by EEG Electrodes During RF Exposures 81 Development of MRI Exposure Risk Probability Based on Local Temperature Safety Considerations 81 An Investigation into Occupational Exposure to EMF for Personnel Working With MRI Equipment 82 Large-scale and Fast FDTD Calculation Using a GPU-Based Cluster (C-Type CIB) with Two or More Nodes 82 FDTD Calculation via GPU Using NVIDIA s Compute Unified Device Architecture (CUDA) Language 83 Novel Hyperthermia Applicator for Head and Neck Region with Antenna Array 83 The Influence of the User Hand on Mobile Phone Antenna Performance in Data Mode 84 Study of Quasi-Static H-Field Concentration on Hyperthermia Treatment 84 Investigation of Cross-talk on Mobile Phone PCB with Shielding 85 Optimization of a Metamaterial Inspired Antenna with Genetic Algorithms 85 Realistic Skeleton Based Deformation of High-Resolution Anatomical Human Models for Electromagnetic Simulation 86 Static and Low Frequency Extensions of EM Solver Package for Human Body Compliance 86 The Power of Generalized Huygens Wave Excitation 87 FDTD Calculation via GPU using NVIDIA s Compute Unified Device Architecture (CUDA) Language 87 A Complete Framework for the Modelling of Third Order Nonlinear Effects in FDTD 88 Refinement Schemes Applied to a Fully Interactive Novel Grid Generator in FDTD 88 A Novel Unified Material Architecture to Simultaneously Model Multiple Material Types 89 Investigation of Suitability of Unstructured Meshing Techniques to Complex Biomedical Data. 89 MRI Induced Implant Heating 90 Hardware Accelerated Thermal Simulations 90 Simulation the Thermal Impact of Blood Flow 91 Time Domain Circuit Co-Simulation 91 Implementation of Novel High-Speed SAR Averaging Routines in FDTD 92 Talairach Based Extraction - Implementation and Application 92 4

7 Education Program: Student Semester and Master Projects 93 Ellipitc Curve Cryptography ASIC for Radio Frequency Authentication 96 VLSI Implementation of the Whirlpool Hash Function 96 Matrix Decomposition Processor for MIMO Communication Systems 97 8-State Radix-4 M-BCJR Decoder 97 Virtual Component for the Division Operation 98 PCP - Pulse-Control Processor for Qubit Manipulation 98 High-Definition Audio Interface for Digital Audio Systems 99 Virtual Analog Synthesizer: Digital Implementation of an Analog Synthesizer 99 Modular Hardware Platform for IEEE n Transceiver 100 Robust Data Embedding in Audio 100 FPGA - ASIC Prototyping System 101 Meteo Station on Spartacus 101 Real-Time Compression of 3D Structures in FPGA 102 FIR Filter Design Support for Signal Processing in FPGAs 102 Digital Audio Algorithms for Reconfigurable Processor 103 Analysis and Design of GSM/EDGE Receivers 103 Turbo Equalization for GSM/EDGE 104 Implementation of Receiver for GSM/EDGE 104 Design of a Multi-Band CMOS RF Receiver Frontend for Mobile WiMAX 105 Frontend Topologies for Low-Power Wireless Receivers in CMOS 105 Multi-Bit Sigma-Delta DAC for WLAN Applications 106 Discrete Distribution of Doping Atoms in 3D Devices 106 CNT-FET Simulator: A Green s Function Simulator for Nanoscopic CNT-based Strain Sensors 107 Coupling the Monte-Carlo Method with Semi-Analytical Solutions of the Boltzmann Transport Equation 107 Simulation of InGaN / GaN Nano-LEDs 108 Ab-Initio Simulations for Constructing Envelope Theories in Nanostructures 108 Nitride-Based Back Contacts for CIGS Solar Cells 109 Noise in Avalanche Photodiodes 109 Simulation of Plasmonic Waveguides with the Finite Element Method 110 Finite Element Simulation of the Bimetallic Effect in Power Modules 110 PhD Theses Abstracts 111 Master Theses Overview 112 Semester Projects Overview 113 Education at IIS 114 Lectures 116 IC Design Projects Overview 119 Research Projects Overview 121 Microelectronics Design Center (DZ) 124 Joint Research Cooperation with the IT IS Foundation 128 Publications 129 Presentations 138 Equipment for Electronic Test and Physical Characterization 144 EDA and TCAD Software 147 Computer Equipment 149 5

8 Preface Introduction This report presents the academic and research activities of the Integrated Systems Laboratory (IIS) and the Microelectronics Design Center (DZ) at the Department of Information Technology and Electrical Engineering (D-ITET) of the Swiss Federal Institute of Technology in Zurich (ETH Zurich) for the year The IIS staff includes four professors, five research associates, thirteen (13) post docs, thirty six (36) PhD students, three computer system administrators, five persons in administration, and two technicians. Research topics in digital, mixed, and analog integrated circuit (IC) design range from sensitive sensor interfaces to GHz RF circuits on the analog side, over analog-todigital converters to the digital field covering projects from low-power design methodologies to complex systemson-a-chip (SoC). Technology CAD (TCAD), technology and device development, computational optoelectronics, physical characterization, and bio-electromagnetics complement the research fields of IIS towards professional tools for modeling and optimizing nanoelectronic and optoelectronic devices and technologies in the nanometer range as well as bio-electromagnetic systems. Microelectronics Design Center The Microelectronics Design Center, headed by Dr. H. Kaeslin, with four staff members, is a service organization of the Department of Information Technology and Electrical Engineering. It is closely cooperating with IIS and other D-ITET and ETH Zurich laboratories in their design research and teaching activities for VLSI, analog, and system electronics (see page 124ff.). Research Projects and Funding Following the trends of earlier years, our cooperation with national and international partners is at the center of our activities. In 2008, ten new research projects started in the fields of complex digital and analog systems-on-chip as well as semiconductor process and device development and simulation for nanoelectronics and optoelectronics. Three of them are KTI/CTI (Swiss Commission for Technology and Innovation) projects, one a project of the European Union, one SNF (Swiss National Science Foundation) project and five industrial research cooperations. Overall, IIS was involved in a total of 29 research projects. Five of them were projects funded by EU, eight by KTI, one by ETH Zurich, six by SNF, and nine by industrial partners and research foundations in Switzerland, Europe, and Japan. PhD Students In 2008, four PhD students finished their doctoral thesis successfully. IIS offers an excellent and highly stimulating research environment that permits PhD students to work on very attractive topics and, nevertheless, to finish their thesis in a comparatively short time. However, it is still an ambitious challenge to find very qualified PhD students from all over the world. We try our best to overcome this situation by an appropriate salary policy and by focusing the student activities on scientific work in order to reduce the administrative and educational overhead. Analog and Mixed Signal IC Design Group For the Analog and Mixed Signal Integrated Circuit Design (AMIC) Group of Prof. Huang, the year 2008 has shown a continuation of work around the group s focus in the field of RF and base-band circuit design for telecommunications applications. One of the main result of the group s research efforts has been the successful realization of a power and area efficient turbo decoder in 0.13 µm CMOS technology for High-Speed Downlink Packet Access (HSDPA) in 3G mobile radios, improving the current state-of-the-art energy efficiency by more than a factor of 10 (in collaboration with IC and System Design and Test Group). This decoder has been presented at the most important conference in the field, the International Solid- State Circuit Conference ISSCC The contribution has been selected to appear in the special ISSCC edition of the Journal of Solid-State Circuits as well. In 2008, the AMIC group has been partner in several national projects with research focus in advanced circuit design for wireless applications and implementation in deep-submicron CMOS technologies at the 130 nm node and beyond, mainly in collaboration with its spin-off ACP. IC and System Design and Test Group The main activities of the IC and System Design and Test Group in 2008 were in multi-antenna communications (MIMO) and encryption systems with quantum key distribution. Many algorithms for MIMO communications have been realized or enhanced. The real-time MIMO-OFDM Testbed has been improved and adapted to accept ASICs for critical applications. A so-called offline testbed has been developed in collaboration with the ETHZ Communication Technology Laboratory. It supports realworld, real-time MIMO experiments with offline execution of algorithms in Matlab. Multi-user experiments have been conducted on both testbeds. A 2x2 MIMO system has been implemented on a reconfigurable processor for multi-media ASIC. Further important activities concerned cryptographic systems. New Hash functions have been investigated together with Prof. Willi Meier of FHNW, submitted to the NIST Cryptographic Hash Algorithm Competition 2008, and implemented in silicon. SNF Professorship in Signal Processing Circuits and Systems The Swiss National Science Foundation has awarded an SNF professorship to Dr. Andreas Burg for a project entitled Circuits and Systems for Next Generation Wireless Systems. Based on this grant, an the SNF Assistant Professorship in Signal Processing Circuits and Systems has been established at the Integrated Systems Laboratory of the ETH Zurich (further information on page 9). Since January 2009, the Signal Processing Circuits and Systems (SPCaS) Group works on the hardware-efficient, low-power implementation of various applications that require computationally complex digital signal processing. The research interests of the SPCaS group range from algorithm development and optimization for hardware implementation to their VLSI and system integration. An important focus of the group are wireless communication systems. The activities in this area tie in well with the previous research at IIS. Upcoming challenges include the development of high-performance multi-antenna receivers and the improvement of the power consumption and energy efficiency of corresponding integrated circuits in deep submicron CMOS technologies. 6

9 Technology CAD Group Research in the Device Physics Group focused on quantum transport and methods to solve the Boltzmann transport equation. The quantum-transport simulator SIMNAD was extended by intra- and inter-valley phonon scattering in the Non-equilibrium Green s Function (NEGF) framework, and effects like broadening of the density of states, destruction of phase coherence, and spectral current variation were studied. The non-parabolicity model was verified with tight-binding simulations for threshold voltage shifts and on-currents of quantum wire transistors. In an exceptional masters thesis, a novel modeling method for nanoscopic Carbon Nano Tube (CNT) based transistors was outlined. The new NEGF approach, called orbital-charge model, uses a complex contour integration to rigorously calculate the electron density within the device. To avoid diverging potentials close to interfaces, an original new way of calculating the Hartree potential was developed with an accuracy exceeding previous methods by far. The current-based one-particle Monte Carlo (CBOPMC) approach to solve the Boltzmann transport equation (BTE) as implemented in the Monte Carlo simulation package SimnIC can be used, amongst others, to extract transport parameters (TPs) from a device simulation. A new semi-analytical series for these TPs was derived by simply inverting the BTE and rearranging the terms without further assumptions. It was found that the influence of higher-order derivatives of the electrostatic potential and the quasi Fermi potential on the TPs is not negligible. SimnIC was also extended by a new refinement strategy to treat discrete doping atoms in a Monte Carlo simulation. The group participated actively in two European projects with Monte Carlo and leakage simulations of template devices of the 32 nm and 22 nm technology nodes. This also involved the determination of parameter sets for future hafnium-oxide based gate stacks. In a collaboration with IBM Yorktown Heights a model for gate-induced drain leakage was validated using well-characterized pnjunction diodes provided by IBM. Collaboration with TU Munich resulted in the improvement of the model. The activities of the Atomistic Simulation Group are centered on multiscale simulation of dopant diffusion and activation in silicon. Diffusion and clustering parameters were calculated with ab-initio calculations based on density functional theory and then used as input in a stateof-the art process simulator based on the kinetic Monte Carlo approach. The selection of defect species was made according to the needs of model development for process simulation, taking into account the availability of experimental data, model sensitivity and the capabilities of current ab-initio methods. To ensure a suitable selection of defect species and a correct transfer of the results based on first-principle physics to the kinetic Monte Carlo simulator, the close collaboration with Synopsys was essential. The calculated ab-initio results at the Supercomputing Center CSCS are compiled into a systematic database of more than 10,000 calculations for 120 defect types in several charge states. It covers clusters with arsenic, phosphorus, antimony, indium and fluorine, including mixed clusters. Computational Optoelectronics Group The COE group has focused on both the development of novel simulation models, as well their application to the design and analysis of semiconductor optoelectronics devices. In the domain of nano-scale light emitters, research has been undertaken with the aim to model the physical properties of optical cavities with high quality factors in connection with quantum dots/wires and wells. These emitters are envisioned to approach ultrahigh efficiencies. A three-dimensional finite-element method for the solution of Maxwell s equations has been developed in order to study the optical outcoupling mechanisms of nano-scale light emitters. By applying a modal analysis, the interplay between multiple quantum dots coupling to multiple optical modes could be explained in the measured spectrum. Further work in the field of electromagnetics for light emitters aims to find new discretization schemes in order to reduce the computational burden substantially. Here, first demonstrations of the ultra-weak variational formulation for the wave equation showed promising results. In the field of Gallium-Nitride materials for visible light sources, a microscopic model for gain and luminescence in disordered materials has been developed, that, for the first time, matches measured data for quantum wells emitting in the blue and green in a consistent manner. The main ingredient is the introduction of localized hole states on the level of the density of states. The gain and luminescence degradation due to disordering can now be studied systematically for emission in the green regime, which currently is a major effort in the display industry. In the field of semiconductor nanostructures, the electro-optical simulator AQUA has been further developed. In particular, an important finding has been made in the calculation of the electronic band structure with the k p method: the occurrence of unphysical solutions (spurious modes), which has been discussed for two decades, has been explained by the COE group in a mathematical consistent way. Using the new results, a straightforward a-priori check for spurious solutions can be made, and by proper choice of parameters, they can be eliminated. Several design projects are ongoing, and first designs have been made in In collaboration with an industrial partner, an avalanche photodiode for fiber to the home (FTTH) applications has been developed. The design applies novel ideas in order to address cost and yield aspects. In the field of mode-locking vertical cavity surface emitting lasers, a design has been developed that allows electronic pumping of an external optical cavity configuration. As an outlook for 2008, a 3.2 Mio. Euro European project on high efficiency nanoscale solar cells has been granted, and the COE group will contribute the design and modeling in the consortium. Leave of Professor Bernd Witzigmann Since November 2008, Prof. Witzigmann is full professor and head of the Computational Electronics and Photonics Laboratory at the Electrical Engineering and Computer Science Department of the University of Kassel in Germany. From March 2004 till his move, Bernd was Assistant Professor at ETH Zurich and head of the Computational Optoelectronics Group (COE) at our laboratory. His outstanding scientific qualifications led to a wide range of research co-operations with academic and industrial partners. Together with his research group members, Bernd achieved remarkable results in science and education: Graduation of 5 PhD candidates as supervisor. 6 PhD candidates of the COE Group will graduate between 2009 and 2011 under his scientific supervision. Supervisor of 15 master students and 11 Semester theses. 18 research projects supported by public funding agencies and industrial partners with a total of 3.7 million Swiss francs (EUR 2.5 million, USD 3.3 million). 7

10 38 journal and book publications and 53 conference talks. These results were achieved in only four and a half years. For an assistant professor, this represents an outstanding scientific and educational performance. The Integrated Systems Laboratory would like to thank Prof. Witzmann sincerely for his work at ETH Zurich and for the future support of PhD students in computational optoelectronics. We wish him lots of success in his new position! Physical Characterization Group In 2008 four new research fields have been initiated in conjunction with four new projects. In a project with Infineon AG, a novel screening strategies based on embedded circuits to control the gate oxide defectivity in Smart Power ICs for critical automotive applications will be developed. In a first phase, dedicated circuitries have been conceived (and integrated) for on-chip stressing and characterization of gate oxide defects and leakage currents in LDMOS transistors. A project in nano-metrology of advanced CMOS technologies is carried out with Synopsys. Its scope is to develop the necessary quantification tools to reach the required sub-nanometer uncertainty in the measurement of critical dimensions for wafer and mask-level scanning electron microscopy (SEM) of the 32 nanometer node and beyond. In a project in collaboration with Synopsys, a systematic methodology for modeling and correction of the enhanced proximity effects occurring in high-resolution direct writing of wafers by electron beam lithography at low beam energies will be developed. The goal of a project with HUBER+SUHNER is the design of accurate dosimetry tools for the electron beam processing of polymers in the manufacturing of electrical cables and optical fibers. Two research cooperations concern the field of the Micro-Electro-Mechanical Systems (MEMS). The first one with Toshiba is the development of a multiscale simulation methodology to predict the mechanical behavior of macroscopic thin film structures from the morphology at nanoscale, with the scope to ensure the long term reliability of MEMS products. The second cooperation with NTT is related to the development of a systematic design methodology for CMOS MEMS, which bases on standard CMOS processing flows. A European project with ALSTOM (F) has been successfully concluded. In this framework, the prototype simulation tool using unified, coupled, multi-level abstraction VHDL modeling has been tested on different examples, showing interesting capabilities and some intrinsic limitations. Bio-Electromagnetics Group IT IS, the Foundation for Research on Information Technologies in Society (headed by ETH adjunct Prof. Niels Kuster), a non-profit research institution supported by ETH Zurich, established its scientific and technical work in close collaboration with our laboratory. The research activities of IT IS are in the domain of the interaction of electromagnetic radiation with biological organisms, in advanced measurement equipment for electromagnetic radiation, and health risk assessment. A growing number of research projects and PhD students at IIS is funded by the global wireless communications industry, several governmental agencies, and the Commission of the European Union. It turned out that this collaboration with IT IS is very fruitful and a benefit for both institutions (see page 128). Education Next to research, teaching occupies a central role in our activities. Our staff is responsible for several core lectures in Information Technology and Electrical Engineering as well as in other departments (see page 116). The chapter on student projects (page 93) gives an overview on the manifold diploma theses and semester projects. Several outstanding student semester and master projects contribute to our research projects. Their descriptions can be found together with the research reports on pages 37, 38 (left), 39 (right), 41 (left), 42, 43 (right), 45 (right) and often lead to accepted presentations at international conferences ([D13], [D6], [D21]; pages 129ff.). Partners and Funding Agencies The activities of our laboratory were only possible through the support from the governing board of our university, and several national and international institutions and industrial parties. Special thanks go to our school, to the computing services of ETH Zurich, as well as to the Department of Information Technology and Electrical Engineering and its services and administration. Finally, we would like to express our gratitude to the Swiss Commission for Technology and Innovation (KTI/ CTI), the Swiss National Science Foundation (SNF), the Swiss State Secretariate for Education and Research (SER), and the Commission of the European Union for their financial support. Just as much, we would like to thank our partners ACP Switzerland, Alstom France, AMAT USA, Anagram Switzerland, austriamicrosystems Austria, Bookham Switzerland, BridgeCo Switzerland, Celestrius Switzerland, ECPE Germany, Enablence Switzerland (former Albis Optoelectronics Switzerland), Enclustra Switzerland, Epsilon France, Exalos Switzerland, Flisom Switzerland, Fraunhofer Gesellschaft Germany, FH Windisch Switzerland, Fujitsu Japan, Hasler Stiftung Switzerland, Huber+Suhner Switzerland, IBM Research Switzerland, id Quantique Switzerland, IMEC Belgium, Infineon Austria and Germany, IT IS Foundation Switzerland, MHT Optic Switzerland, NEC Japan, NTT Japan, Osram Germany, Samsung Korea, Sol Voltaics Sweden, SPEAG Switzerland, ST Microelectronics France and Italy, Synopsys Switzerland LLC, Synopsys, Inc. USA and Germany, Toshiba Japan, Technical University of Armenia, Technical University Eindhoven Netherlands, Technical University Graz Austria, Technical University Wien Austria, University of Bologna Italy, University of Cagliari Italy, University of Canberra Australia, University College Cork Ireland, University of Pisa Italy, University of Purdue USA, University of Regensburg Germany, VEST Corp. France, VSEA USA, the EPFL laboratories IQEP and LPN in Lausanne Switzerland, and the ETH Zurich laboratories CGL, HVL, IfA, IfE, IBT, IFH, IKT, IQE, IWR, and Vision Laboratory for the fruitful cooperation in research projects as well as for their financial support. 8

11 Announcement of Assistant Professor Andreas Burg Head of the Signal Processing Circuits and Systems Group It is a great pleasure for the Integrated Systems Laboratory to announce the election of Dr. Andreas Burg as Assistant Professor for Electronic Systems for Signal Processing in the Department of Information Technology and Electrical Engineering at ETH Zurich as of 1 January Prof. Andreas Burg is well known for his work in digital IC design of signal processing circuits and systems. He received the diploma (M.Sc.) in electrical engineering of ETH Zurich in For his diploma work, he received a best-in-class award and the ETH Medal for excellent diploma thesis. In his PhD studies at our laboratory, he developed novel architectures and VLSI circuits for MIMO communication systems. During this time, he was a visiting researcher at Bell Laboratories, Lucent Technologies, Holmdel, USA for a total of one year. He received the Dr. sc. techn. degree from ETH Zurich in 2006, and his scientific work was rec-ognized with the ETH Medal for excellent PhD thesis. After his doctorate, Dr. Burg remained at ETH as post-doctoral research assistant, initially at our laboratory, and later in Prof. Bölcskei s Communication Theory Group. In 2007 he was a co-founder and Director VLSI at the ETH spin-off Celestrius Inc., Zurich, Switzerland. Andreas Burg received a SNSF Professorship for Electronic Systems for Signal Processing from the Swiss National Science Foundation (SNSF). Currently, he is the head of the Signal Processing Circuits and Systems (SPCaS) group at our laboratory. Further members are Dr. Simon Häne (SPCaS deputy) and the PhD students Pierre (Pit) Greisen and Pascal Meinerzhagen. Besides the research activities in digital IC design for signal processing circuits and systems and the operation of the communication testbed facilities at our laboratory, Prof. Burg teaches graduate classes in VLSI design and signal processing. A wide range of emerging applications relies heavily on computationally complex signal processing algorithms. The hardware-efficient, low-power implementation of such systems requires consideration of both algorithm and VLSI implementation aspects. The SPCaS group under Prof. Burg develops VLSI circuits and systems for various applications that require low-power, high speed VLSI implementations of computationally complex digital signal processing. The new research team combines a solid background in digital signal processing with considerable experience in the development and implementation of digital circuits and systems in deep submicron CMOS technologies. Algorithms and circuits developed in the SPCaS research group find applications in wireless communication systems, in image and video processing, and in a wide range of other consumer electronics devices. One important research topic of the group focuses on next generation wireless transceivers such as IEEE n, 3GPP LTE, and WirelessHD. In the area of wireless communication systems, the SPCaS group collaborates closely with Prof. Bölcskei s Communication Theory Group, building on a significant body of previous research. Prominent examples of such prior research are algorithms, VLSI circuits, and hardware prototype implementations of multi-antenna wireless systems and circuits for high-speed and lowpower error correction coding. For industrial partners, the activities of the SPCaS group contribute to the development of highly integrated complex signal processing systems with low power consumption and provide prototype ASIC implementations and technology demonstrators. From an academic perspective, the interdisciplinary approach between microelectronics and signal processing sparks innovative concepts and solutions and leads to new, interesting research problems that are relevant for real-world applications. To realize these applications, it is the clear intention of the group to continue and intensify the scientific and technical cooperation with industrial and academic partners in Switzerland, Europe, and all over the world. 9

12 10

13 Representative Figures Staff Number of FTE (full-time equivalent) job positions at the Integrated Systems Laboratory from 1999 to PhD Theses Number of completed PhD theses per year at the Integrated Systems Laboratory from 1999 to Abstracts of PhD theses: see page

14 Journal and Book Publications Number of journal and book publications by the Integrated Systems Laboratory from 1999 to References: see pages 129ff. Conference and Workshop Presentations Number of conference and workshop presentations by the Integrated Systems Laboratory from 1999 to 2008 References: see pages 138ff. 12

15 IIS Research Projects Number of research projects with external funding at the Integrated Systems Laboratory from 1999 to Overview of research projects: see pages 121ff. Partners and funding agencies: see pages 24ff. Research Partners of IIS World CH Europe USA Japan Others World Industry Academia Research partners of the Integrated Systems Laboratory in Switzerland (CH), Europe, and worldwide. Addresses of partners: see pages 24ff. 13

16 Awards and Patents Academic & industrial awards and patents received by Integrated Systems Laboratory staff from 1999 to References for 2008: see pages 30ff. Former PhD Students Working places in industry and academia of 124 former PhD students graduated at Integrated Systems Laboratory in Switzerland, Europa, USA, Japan and worldwide. Addresses of former PhD students: see pages 17ff. 14

17 Staff Professors Huang Qiuting, Dr., Professor for Electronics, since 1 Jan 1993 Head until 30 Sep 2008 Fichtner Wolfgang, Dr., Professor for Electronics, since 1 Sep 1985 Head since 1 Oct 2008 Witzigmann Bernd, Dr., Professor for Optoelectronics 4 Feb Oct 2008 Schenk Andreas, Prof., Dr., Dipl.-Phys., Senior Scientist since 1 Aug 1991 Microelectronics Design Center Kaeslin Hubert, Dr., Dipl. El.-Ing. ETH, Head since 1 Jan 1986 Brändli Matthias, Dipl. El.-Ing. ETH 1 Mai Sep 2008 Gürkaynak Frank, Dr., dipl. El. Ing since 1 Jun 2008 Köppel Rudolf, FEAM since 1 Apr 1995 Muheim Beat, Dipl. El. Ing. ZHAW since 1 Aug 2008 Scientific Staff Aemmer Dölf, Dr., Dipl. Phys. ETH, Senior Scientist since 1 Sep 1985 Bäcker Alexandra, Dipl.-Ing. since 1 Oct 2004 Balmer Christoph, Dipl. El.-Ing. HTL 1 Aug Apr 2008 Benkeser Christian, Dipl. El.-Ing. ETH since 15 Sep 2004 Brugger Simon, Dr., Dipl. Phys. ETH 17 Jan Mar 2008 Burg Andreas, Dr. Dipl. El.-Ing. ETH since 1 Jul 2008 Burger Thomas, Dr., Dipl. El.-Ing. ETH since 1 Oct 1994 Carnelli Dario Albino, M. Sc. EE since 15 Nov 2008 Castellazzi Alberto, Dr., Dipl. Phys 1 Jan Sep 2008 Chen Yihui, M. Sc. EE since 1 Aug 2003 Chen Zhiheng, Dr., M. Sc. EE 1 Oct Mar 2008 Chen Yangjian, Dr., El.-Ing. since 1 Oct 2007 Ciappa Mauro, Dr., Dipl. Phys. since 1 Jan 1998 Del Castillo Guillermo, Dr., M. Mech. Engineer since 1 Mar 2005 Dolgos Denis, Dipl. Phys since 1 Jan 2008 Eberli Stefan, Dipl. El.-Ing. ETH since 1 Dec 2003 Esposito Aniello, Dipl. Phys. ETH since 15 Aug 2005 Felber Norbert, Dr., Dipl. Phys. ETH, Senior Scientist since 1 Jul 1987 Frey Martin, Dipl. Phys. ETH since 15 Aug 2005 Haene Simon, Dr., Dipl. El.-Ing. ETH since 1 Jul 2008 Henzen Luca, Dipl. El.-Ing. ETH since 1 Aug 2007 Holzer Stefan, Dr., techn., Dipl.-Ing. since 1 Dec 2008 Keogh Craig Brendan, M. Sc. EE since 1 Apr 2005 Koch Thomas, M. Sc. EE ETH since 1 Mai 2008 Koschik Alexander, Dr., techn., Dipl.-Ing. since 15 Mai 2008 Kreuter Philipp, Dipl.-Ing. Elektro- u. Informationstechnik since 1 Oct 2005 Kühn Sven, Dipl. Ing. Informationstechnik since 1 Mar 2005 Kull Lukas, Dip. Inf.-Ing. ETH 1 Nov Aug 2008 Kupec Jan, Dipl.-Ing. since 1 Jan 2008 Li Chung-Huan, M. Sc. EE since 5 Apr 2007 Loeser Martin, Dr., Dipl.-Ing. 1 Sep Oct 2008 Lüthi Peter, Dipl. El.-Ing. ETH since 1 Nov 2003 Mächler Patrick, Dipl. El.-Ing. ETH since 1 Sep 2008 Makhlouka Slim, Dipl. Phys. 1 Jan Aug

18 Malandruccolo Vezio, Dipl. El.-Ing. since 1 Mar 2008 Mangiacapra Luigi, Dipl. Phys. since 1 Sep 2008 Martelli Chiara, Dr., Dipl. El.-Ing. since 17 Jan 2001 Meier Hektor, Dipl. El.-Ing. ETH since 1 Apr 2007 Peter Thomas, M. Sc. EE ETH 1 Mar Oct 2008 Römer Friedhard, Dr., Dipl. Ing. Elekrotechnik 15 Apr Sep 2008 Sahli Beat, Dr., Dipl.-Phys. since 1 Jun 2000 Senning Christian, M. Sc. EE ETH since 1 Mar 2008 Schild Stefan, Dr., Dipl. El.-Ing. ETH 1 Jul Aug 2008 Steiger Sebastian, Dipl. Phys. ETH since 1 Nov 2005 Studer Christoph, Dipl. El.-Ing. ETH 1 Jan Nov 2008 Treichler Jürg, Dipl. El.-Ing. ETH since 1 May 2003 Veprek Ratko, Dipl. Rech. Wiss. ETH since 1 Aug 2005 Vollenweider, Dipl. Phys. ETH since 1 Jan 2007 Wenk Markus, Dipl. El.-Ing. ETH since 1 Jan 2006 Computer Staff Feigin, Adam, dipl. El.-Ing. since 1 May 2006 Richardet Christoph, Oberstufenlehrer since 10 May 2000 Wicki Christoph, Dipl. El.-Ing. ETH since 1 Oct 1985 Technical Staff Gisler Hansjörg, Industriespengler (80%) since 1 Aug 1989 Kleier Thomas, Dipl.-Ing. (FH) Nachrichtentechnik since 1 Jun 2005 Administrative Staff Fischer Bruno, Dipl. El.-Ing. HTL since 14 Apr 1992 Haller Christine, Betriebsökonomin HWV (95%) since 8 Mar 1993 Müller Claudia (35%) since 1 May 2006 Plank Eva (60%) since 1 Jul 1998 Roffler Verena (50%) since 1 Sep

19 Former PhD Students Name Year Now with Bach Carlo Balmelli Pio Basedau Philipp Benkler Stefan Berdinas Veronika Bonnenberg Heinz Bösch Thomas Brenna Gabriel Brugger Simon 2005 Burg Andreas Burger Thomas Felix Bürgin Bürgler Josef Buzzo Marco Carbognani Flavio Chavannes Nicolas Chen Xinhua Christ Andreas Ciampolini Lorenzo Ciappa Mauro Conti Paolo Corvasce Chiara Curiger Andreas Deiss Armin Dettmer Hartmut Doswald Daniel Eicher Simon Esmark Kai Etherton Melanie 1993 Interstaatliche Hochschule für Technik (NTB) Werdenbergstrasse 4, CH-9471 Buchs, Switzerland 2003 Silicon Laboratories 7000 West William Cannon Drive, Bldg. 1, Austin, TX 78735, USA 1999 NXP Semiconductors Switzerland AG Binzstrasse 44, CH-8045 Zürich, Switzerland 2006 SPEAG Zeughausstrasse 43, CH-8004 Zürich, Switzerland 2007 EMPA Überlandstrasse 129, CH-8600 Dübendorf 1993 ESPROS Photonics AG Lindenstrasse 10, CH-6340 Baar, Switzerland 2004 STMicroelectronics N.V. Via Cantonale 16 E, CH-6928 Manno, Switzerland 2004 McKinsey & Company, Inc. Alpenstrasse 3, CH-8065 Zurich 2005 Integrated Systems Laboratory, ETH Zürich CH-8092 Zürich, Switzerland 2002 Integrated Systems Laboratory, ETH Zürich CH-8092 Zürich, Switzerland 2008 ESPROS Photonics AG Lindenstrasse 10, CH-6340 Baar, Switzerland 1990 Hochschule Technik+Architektur Luzern Technikumstrasse 21, CH-6048 Horw, Switzerland 2006 Infineon Technologies AG Siemensstrasse 2, A-9500 Villach, Austria 2007 V. le della Villetta 6/1, I Parma, Italy 2002 IT IS Foundation Zeughausstrasse 43, CH-8004 Zürich, Switzerland 2007 Marvell Switzerland Sarl Route de Pallatex 17, CH-1163 Etoy, Switzerland 2003 IT IS Foundation Zeughausstrasse 43, CH-8004 Zürich, Switzerland 2001 STMicroelectronics, Front-End Technology and Manufacturing 850, Rue Jean Monnet - BP16, F Crolles Cedex 2000 Integrated Systems Laboratory, ETH Zürich CH-8092 Zürich, Switzerland 1991 Glasmalergasse 2, CH-8004 Zürich, Switzerland 2006 ABB Semiconductors AG R&D Lb2, Fabrikstrasse 3, CH-5600 Lenzburg, Switzerland 1993 Omnisec AG Rietstrasse 14, CH-8108 Dällikon, Switzerland 2002 Microtune, Inc th Street, Plano, TX 75074, USA 1994 Infineon Technologies AG Siemensstrasse 2, A-9500 Villach, Austria 2000 Seeweg 4, CH-6330 Cham, Switzerland 1996 ABB Semiconductors AG R&D Lb2, Fabrikstrasse 3, CH-5600 Lenzburg, Switzerland 2001 Infineon Technologies IFAG AIM AP D TD M, Am Campeon 1-12, D Neubiberg, Germany 2005 Freescale Semiconductor, Inc Ed Bluestein Blvd. MD:K10, Austin, TX 78721, USA 17

20 Fillo Marco Francese Pier-Andrea Gappisch Steffen Garreton Gilda Geelhaar Frank Glaser Ulrich Gull Ronald Gürkaynak Frank Häne Simon Hager Christian 1993 Quadrics Supercomputers World Ltd. Via Marcellina 11, I Roma, Italy 2005 National Semiconductor GmbH, Data Conversion Systems Group Livry-Gargan-Str. 10, D Fürstenfeldbruck, Germany 1996 NXP Semiconductors Switzerland AG Binzstrasse 44, CH-8045 Zürich, Switzerland 1998 Sun Microsystems Laboratories Asynchronous Group, 16 Network Circle, Menlo Park, CA 94025, USA 2004 Advanced Micro Devices, Inc. 1 AMD Place, Sunnyvale, CA , USA Infineon Technologies IFAG AIM AP D TD M, Am Campeon 1-12, D Neubiberg, Germany 1996 Synopsys Switzerland LLC Thurgauerstrasse 40, CH-8050 Zürich, Switzerland 2005 Integrated Systems Laboratory, ETH Zürich CH-8092 Zürich, Switzerland 2007 IM Ingegneria Maggia SA Via S. Franscini 5, 6601 Locarno 2000 McKinsey & Company Alpenstrasse 3, CH-8065 Zürich, Switzerland Hammerschmied Clemens 2000 Maxim Integrated Products 120 San Gabriel Drive, Sunnyvale, CA 94086, USA Heeb Hansruedi Heinz Frederik Heiser Gernot Herkersdorf Andreas Herrigel Alexander Hertle Jürgen Heusler Lucas Hitschfeld Nancy Höfler Alexander Höhr Timm Humbel Oliver Kells Kevin Körner Thomas Kouchev Ilian Krause Jens Krumbein Ulrich Kuratli Christoph Laino Valerio 1989 Im Tiergarten 9, CH-8055 Zürich, Switzerland 2004 Synopsys Switzerland LLC Thurgauerstrasse 40, CH-8050 Zürich, Switzerland 1991 University of New South Wales, School of Computer Science & Engineering P.O. Box 1, Sydney, 2052 NSW, Australia 1991 TU München, Institute for Integrated Systems Arcisstr. 21, D München, Germany 1990 Bergstrasse 62, CH-8706 Meilen, Switzerland 2004 Miromico AG, Sonneggstrasse 76, CH-8006 Zürich, Switzerland 1990 IBM Zurich Research Division Zurich Research Laboratory, Säumerstrasse 4, CH-8803 Rüschlikon, Switzerland 1993 Departamento de Ciencias de la Computación, Universidad Católica de Chile Blanco Encalada 2120, Santiago, Chile 1997 Freescale Semiconductor Inc West William Cannon Drive, Mail Drop OE341, Austin, TX 78735, USA 2005 Qimonda Dresden GmbH & Co. OHG Königsbrücker Strasse 180, D Dresden, Germany 2000 Infineon Technologies Austria AG AI PL T PI 32 HV, Siemensstrasse 2, A-9500 Villach, Austria 1994 Synopsys, Inc. 700 East Middlefield Road, Mountain View, CA 94043, USA 1999 ABB Business Services Ltd. SLE-I Intellectual Property, Brown Boveri Strasse 6, CH-5400 Baden, Switzerland 2006 Advanced Circuit Pursuit AG Zwischenweg 2, CH-8702 Zollikon, Switzerland 2001 Trithor GmbH, D-5339 Rheinbach, Germany 1996 Infineon Technologies WS SD D Tr MOS, Postfach , D München, Germany 1999 EM Microelectronic Marin SA Sensor & Actuator Interfaces, Rue des Sors 3, CH-2074 Marin, Switzerland 2006 Exalos AG Wagistrasse 21, CH-8952 Schlieren Lamb Peter Gilbert ST, Hackett 2602, Canberra, Australia Lendenmann Heinz 1994 ABB Corporate Research Dept. G, SE Västerås, Sweden 18

21 Leonhardt Götz Liegmann Arno Litsios James Loeser Martin Luisier Mathieu Martelli Chiara Menolfi Christian Mergens Markus Müller Christoph Müller Stephan Muttersbach Jens Neeracher Matthias Nussbaum Miguel Oberle Michael Odermatt Stefan Oesch Walter Omura Ichiro Orsatti Paolo Papadopoulos Dimitris Perels David Pfaff Dirk Pfäffli Paul Pfeiffer Michael Piazza Francesco Pommerell Claude Rogenmoser Robert Rogin Jürgen Röllin Stefan Roth Eric Rothacher Fritz Röwer Thomas Rühl Roland 2000 Synopsys, Inc. 700 East Middlefield Road, Mountain View, CA 94043, USA 1995 Rüti 18, CH-8357 Guntershausen, Switzerland 1996 Actant AG Bahnhofstrasse 10, CH-6300 Zug, Switzerland 2008 Brandschenkestrasse 162, 8002 Zürich 2007 Network for Computational Nanotechnology, Purdue University 465 Northwestern Avenue, West Lafayette, IN-47907, USA 2006 Advanced Circuit Pursuit AG Zwischenweg 2, CH-8702 Zollikon, Switzerland 2000 IBM Zurich Research Laboratory Säumerstrasse 4, CH-8803 Rüschlikon, Switzerland 2001 QPX GmbH Lincolnstrasse 54/II, D München, Germany 2004 Rahn & Bodmer Talstrasse 15, CH-8022 Zürich, Switzerland 1994 Sun Microsystems Santa Clara, CA-95054, USA 2001 Zühlke Engineering AG Wiesenstrasse 10a, CH-8952 Schlieren, Switzerland 1998 Apple Computer, Inc. Zeppelinstrasse 49, CH-8057 Zürich, Switzerland 1988 Departamento de Ciencias de la Computación, Universidad Católica de Chile Casilla 6177, Santiago, Chile 2002 IT IS Foundation Zeughausstrasse 43, CH-8004 Zürich, Switzerland 2006 Synopsys Switzerland LLC Thurgauerstrasse 40, CH-8050 Zürich, Switzerland 2005 Ammann Aufbereitung AG Eisenbahnstrasse 25, CH-4901 Langenthal, Switzerland 2001 Department of Electrical and Electronical Engineering, Kyushu Institute of Technology Sensui-cho, Tobata-ku, Kitakyushu, , Japan 2000 NemeriX SA Stabile Gerre 2000, Casella postale 425, CH-6928 Manno, Switzerland 2008 Marvell Switzerland Sarl Route de Pallatex 17, CH-1163 Etoy, Switzerland 2007 Phonak AG Laubisrütistrasse 28, CH-8712 Stäfa 2003 Diablo Technologies Inc. 290 Boulevard St-Joseph, Suite 200, Gatineau, Quebec, J8Y 3Y3, Canada 1999 Synopsys Switzerland LLC Thurgauerstrasse 40, CH-8050 Zürich, Switzerland 2004 Vela Solaris AG Herrenberg 35, CH-8640 Rapperswil, Switzerland 2000 NemeriX SA Stabile Gerre 2000, Casella postale 425, CH-6928 Manno, Switzerland 1992 ABB (Switzerland) Ltd. CH-I Information Technology, Brown Boveri Strasse 6, CH-5400 Baden, Switzerland Benton Ct, Sunnyvale, CA 94087, USA 2004 Advanced Circuit Pursuit AG Zwischenweg 2, CH-8702 Zollikon, Switzerland 2004 Mühlegasse 60a, CH-6340 Baar, Switzerland 2004 Esmertec AG Lagerstrasse 14, CH-8600 Dübendorf, Switzerland 1995 Infineon Technologies Communication Solutions, Am Campeon 1-12, D Neubiberg, Germany Pilgrim Drive, Danbury, CT 06811, USA 1992 PDF Solutions, Inc. 333 West San Carlos Street, San Jose, CA 95110, USA 19

22 Ryter Roland Saad Yves Sahli Beat Schenk Olaf Schenkel Michael Schmithüsen Bernhard Schneider Lutz Scholze Andreas Schönbächler Edgar Schuderer Jürgen Schuster Christian Seda Steven Sponton Luca Stadler Manfred Stangoni Maria Streiff Matthias Stricker Andreas Thalheim Jan Thalmann Markus Tschopp David Villablanca Luis Villiger Thomas von Arx Christoph Wassner Jürgen Wegmüller Marc Westermann Marc Wettstein Andreas Wikström Tobias Witzig Andreas Witzigmann Bernd 1996 NXP Semiconductors Switzerland AG B137, Binzstrasse 44, CH-8045 Zürich, Switzerland 2007 Synopsys Switzerland LLC Thurgauerstrasse 40, CH-8050 Zürich 2006 Integrated Systems Laboratory, ETH Zürich CH-8092 Zürich, Switzerland 2000 University of Basel, Department of Computer Science Klingelbergstrasse 50, CH-4056 Basel, Switzerland 2002 Synopsys Switzerland LLC Thurgauerstrasse 40, CH-8050 Zürich, Switzerland 2001 Synopsys Switzerland LLC Thurgauerstrasse 40, CH-8050 Zürich, Switzerland 2006 Synopsys Switzerland LLC Thurgauerstrasse 40, CH-8050 Zürich, Switzerland 2000 IBM Systems & Technology Group, Semiconductor Research and Development Center Essex Junction, VT-05452, USA 1998 Bien-Air Dental SA Länggasse 60, Case Postale 6008, CH-2500 Bienne 6, Switzerland 2003 ABB Corporate Research Applied Physics & Materials, Segelhof 1, CH-5405 Baden-Dättwil, Switzerland 2000 TU Hamburg-Harburg, Institute of Electromagnetic Theory Harburger Schloss Str. 20, D Hamburg, Germany 1993 Zurich Financial Services Mythenquai 2, CH-8022 Zürich, Switzerland 2007 Synopsys Switzerland LLC Thurgauerstrasse 40, CH-8050 Zürich, Switzerland 2000 BridgeCo AG Ringstrasse 14, CH-8600 Dübendorf, Switzerland 2005 Huber+Suhner AG Wire + Cable Division, Tumbelenstrasse 20, CH-8330 Pfäffikon, Switzerland 2004 Sensirion AG Laubisruetistrasse 50, CH-8712 Stäfa, Switzerland 2000 IBM Microelectronics MS 972C, 1000 Riverstreet, Essex Junction, VT 05452, USA 2003 CT-Concept Technologie AG J. Renfer-Strasse 15, CH-2504 Biel, Switzerland 2000 BridgeCo AG Ringstrasse 14, CH-8600 Dübendorf, Switzerland 2005 Advanced Circuit Pursuit AG Zwischenweg 2, CH-8702 Zollikon, Switzerland 2000 Synopsys, Inc. 700 East Middlefield Road, Mountain View, CA 94043, USA 2004 NXP Semiconductors Switzerland AG Binzstrasse 44, CH-8045 Zürich, Switzerland 1996 cva technical consulting ag Geissfluhweg 30, CH-4600 Olten, Switzerland 2001 Hochschule Luzern, Technik & Architektur Technikumstrasse 21, CH-6048 Horw 2007 Zühlke Engineering AG Wiesenstrasse 10a, CH-8952 Schlieren 1995 Logismata AG Hardturmstrasse 76, CH-8005 Zürich, Switzerland 2000 Synopsys Switzerland LLC Thurgauerstrasse 40, CH-8050 Zürich, Switzerland 2000 ABB Switzerland Ltd., Semiconductors Fabrikstrasse 3, CH-5600 Lenzburg, Switzerland 2002 Vela Solaris AG Herrenberg 3, CH-8640 Rapperswil, Switzerland 2000 University of Kassel, Computational Electronics and Photonics Institute Wilhelmshoeher Allee 71, D Kassel, Germany 20

23 Yun Chan-Su Zahir Rumi Zelenka Stefan Zimmermann Reto 2000 Synopsys, Inc. 700 East Middlefield Road, Mountain View, CA 94043, USA Glenwood Avenue, Menlo Park, CA 94025, USA 2001 Synopsys Switzerland LLC Thurgauerstrasse 40, CH-8050 Zürich, Switzerland 1997 Synopsys Switzerland LLC Thurgauerstrasse 40, CH-8050 Zürich, Switzerland 21

24 Academic Guests Dr. Miao Peng Southeast University, Nanjing, China since 15 Sep 2008 Prof. Dr. Shahriar Mirabbasi University of British Columbia, Vancouver, Canada since 1 Oct 2008 Haruka Kubo Toshiba Corporation, Yokohama, Japan since 11 Oct 2008 Dr. Norio Sato NTT Corporation, Kanagawa, Japan since 17 Nov 2008 Dr. Xavier Perpinya Centro National de Microlelectronica, Barcelona, Spain 16 Jan 2008 Jesus Urresti Centro National de Microlelectronica, Barcelona, Spain 16 Jan 2008 Dr. José Rebollo Centro National de Microlelectronica, Barcelona, Spain 16 Jan 2008 Dr. Thomas Licht Eupec GmbH + Co. Kg, Warstein, Germany 16 Jan 2008 Dr. Michel Mermet-Guyennet Alstom Transport Composants, Semeac, France 16 Jan 2008 Michel Piton ALSTOM, Tarbes, France 16 Jan 2008 Dr. Marc-André Dupertuis Institut de Photonique et d Electronique Quantique, EPFL, Lausanne, Switzerland 13 Feb 2008 Takashi Tsurgai Toshiba Corporation, 19 Feb 2008 Takuma Hara Toshiba Corporation, 19 Feb 2008 Dr. Kazunobu Kojina Kyoto University, Kyoto, Japan 26 Feb 2008 Dr. Schulz Synopsys Munchen, Germany 4 Mar 2008 Dr. Markus Dülk Exalos AG, Schlieren, Switzerland 23 Apr 2008 Bo Hammarlund TranSiC, Kista, Sweden 26 Apr 2008 Dr. Lars Bomholt Synopsys Switzerland LLC, Zurich Switzerland 19 Mai 2008 Dr. Masatoshi Higuchi Toshiba Corporation, Yokohama, Japan 19 Mai 2008 Takayuki Masunaga Toshiba Corporation, Yokohama, Japan 19 Mai 2008 Hidehiko Yabuhara Toshiba Corporation, Yokohama, Japan 19 Mai 2008 Silvio Grogg BELIMO Automation AG, Hinwil, Switzerland 21 Mai 2008 Dr. Berthold Schmidt Bookham Technology, Zürich, Switzerland 23 Mai 2008 Dr. Marc-André Duptuis EPFL, Institut de Photonique et d Electronique Quantique, Lausanne Switzerland 29 Mai 2008 Takashi Hori Synopsys Co., LTD, Tokyo, Japan 29 Mai 2008 Yoshiyuki Shioyama Toshiba Corporation, Yokohama, Japan 29 Mai 2008 Dr. Yuichiro Yamazaki Toshiba Corporation, Yokohama, Japan 29 Mai 2008 Dr. Paul Zbinden Phonak AG, Laubisrütistrasse 28, Stäfa, Switzerland 29 Mai 2008 Pedro Castrillo Universita de Valladolid, Valladolid, Spain 3 Jun 2008 Dr. Martin Jaraiz Universita de Valladolid, Valladolid, Spain 3 Jun 2008 Dr. Ingacio Martin-Bragado Synopsys Inc., Mountain View, CA, USA 3 Jun 2008 Nik Zographos Synopsys Switzerland LLC, Zurich Switzerland 3 Jun 2008 Prof. Pierre Fazan Innovative Silicon, EPFL Lausanne, Lausanne, Switzerland 5 Jun 2008 Dr. Cédric Bassin Innovative Silicon, EPFL Lausanne, Lausanne, Switzerland 5 Jun 2008 Dr. Felix Lustenberger Espros Photonics AG, Baar, Switzerland 23 Jun 2008 Dr. Maurizio Dapor Fondazione Bruno Kessler Center for Materials and Microsystems Povo, Italy 30 Jun- 2 Jul 2008 Dr. Masami Hane NEC Eletronics Corporation, Kanagawa, Japan 2 Jul 2008 Dr. Pietro Altermatt Universität Hannover, Hannover, Germany 30 Jun 2008 Yasuyuki Asahara Synopsys Co., LTD, Tokyo, Japan 9 Jul 2008 Dr. Masami Hane NEC Eletronics Corporation, Kanagawa, Japan 9 Jul 2008 Masahiro Tanaka Synopsys Co., LTD, Tokyo, Japan 9 Jul 2008 Dr. G. Mura University of Caligary, Italy Dr. Paul Solomon IBM Research Division, Yorktown Heights, NY, USA 18 Jul 2008 Dr. Heike Riess IBM Research Division, Rüschlikon, Switzerland 18 Jul 2008 Dr. Walter Riess IBM Research Division, Rüschlikon, Switzerland 18 Jul 2008 Dr. Hwasik Park Synopsys Korea. Inc., Seoul, Korea 29 Jul 2008 Dr. Keun-Ho Lee Samsung Electronics Co. Ltd., Hwasung-City, Korea 29 Jul

25 Youngkwan Park Samsung Electronics Co. Ltd., Hwasung-City, Korea 29 Jul 2008 Moonhyun Yoo Samsung Electronics Co. Ltd., Hwasung-City, Korea 29 Jul 2008 Dr. Markus Blaser Enablence Switzerland AG, Rüschlikon, Switzerland 10 Sep 2008 Prof. Hovik V. Baghdasaryan University of Armenia, Yerevan, Armenia 28 Sep - 3 Oct 2008 Prof. Dr. Michal Okoniewski University of Calgary, Calgary, Alberta, Canada 28 Aug 2008 Takayuki Masunaga Toshiba Corporation, Yokohama, Japan 13 Oct - 15 Oct 2008 Jaesup Lee Samsung, Suwan, Korea 16 Oct 2008 Dr. Christian Enz CSEM SA, Neuchâtel, Switzerland 28 Nov

26 Partners and Funding Agencies ACP Albis OptoElectronics Alstom AMAT Anagram austriamicrosystems BBT BCI Bookham BridgeCo Celestrius CGL-ETHZ ECPE Enablence Enclustra EPFL Epsilon ETHZ Exalos FhG-IISB FhG-ISE FHNW Windisch Flisom Fujitsu ACP Advanced Circuit Pursuit AG Alte Landstrasse 101, CH-8702 Zollikon ZH, Switzerland Albis Optoelectronics AG (now: Enablence Switzerland AG) Moosstrasse 2, CH-8803 Rüschlikon, Switzerland Alstom Transport S.A. 3 Avenue André Malraux, F Levallois-Perret, France Alstom Transport Composants Rue du Docteur Guinier - BP 4, F Semeac, France Applied Materials, Inc. 974 E. Arques Avenue, M/S 81157, Sunnyvale, CA 94086, USA Anagram Technologies SA Zl Le Trési 6A, CH-1028 Préverenges, Switzerland austriamicrosystems AG Schloss Premstätten, A-8141 Unterpremstätten, Austria Bundesamt für Berufsbildung und Technologie (Federal Office for Professional Education and Technology, a Swiss Government Agency) Effingerstrasse 27, CH-3003 Bern, Switzerland BCI Group Moosstrasse 68-78, CH-2540 Grenchen, Switzerland Bookham (Switzerland) AG Binzstrasse 17, CH-8045 Zürich, Switzerland BridgeCo AG Ringstrasse 14, CH-8600 Dübendorf, Switzerland Celestrius AG Hochstrasse 60, 8092 Zurich, Switzerland Computer Graphics Laboratory ETH Zürich, Haldeneggsteig 4, CH-8092 Zürich, Switzerland ECPE Engineering Center for Power Electronics GmbH Landgrabenstrasse 94, D Nürnberg, Germany Enablence Switzerland AG (former: Albis Optoelectronics AG) Moosstrasse 2, CH-8803 Rüschlikon, Switzerland Enclustra GmbH Technoparkstrasse 1, CH-8005 Zürich, Switzerland Ecole Polytechnique Fédérale de Lausanne EPFL, CH-1015 Lausanne, Switzerland EPSILON Ingénierie 10 rue Jean Bart, BP 97431, F Labège Cedex, France Eidgenössische Technische Hochschule Zürich (Swiss Federal Institute of Technology Zürich) ETH Zürich, Rämistrasse 101, CH-8092 Zürich, Switzerland Exalos AG Wagistrasse 21, CH-8952 Schlieren, Switzerland Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.v. Institut für Integrierte Schaltungen und Bauelementetechnologie Schottkystrasse 10, D Erlangen, Germany Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.v. Institut für Solare Energiesysteme Heidenhofstr. 2, D Freiburg im Breisgau, Germany Fachhochschule Nordwestschweiz Klosterzelgstrrasse, CH-5210 Windisch, Switzerland Flisom AG Ueberlandstrasse 129, CH-8600 Dübendorf, Switzerland Fujitsu Laboratories Ltd 10-1, Morinosato-Wakamiya, Atsugi , Japan 24

27 Hasler Huber+Suhner HVL-ETHZ IBM Research IBT-ETHZ ICOS-ETHZ idq IIS-ETHZ IKT-ETHZ IMEC Infineon IPEQ-EPFL IPEQ-LASPE-EPFL IQE-ETHZ IT IS IT IS Partners Hasler Stiftung Hirschgraben 6, CH-3011 Bern, Switzerland Huber+Suhner AG Tumbelenstrasse 20, CH-8330 Pfäffikon, Switzerland High Voltage Laboratory ETH Zürich, Physikstrasse 3, CH-8092 Zürich, Switzerland IBM Research GmbH Säumerstrasse 4, CH-8803 Rüschlikon, Switzerland Institut für Biomedizinische Technik (Biomedicinical Engineering Laboratory) ETH Zürich, Gloriastrasse 35, CH-8092 Zürich, Switzerland Institut for Computational Science ETH Zürich, Universitätsstrasse 6, CH-8092 Zürich, Switzerland id Quantique S.A. Chemin de la Marbrerie 3, CH-1227 Carouge, Switzerland Integrated Systems Laboratory ETH Zürich, Gloriastrasse 35, CH-8092 Zürich, Switzerland (i.e. the publisher of this Research Review 2008 ) Institut für Kommunikationstechnik (Laboratory for Communication Technology) ETH Zürich, Sternwartstrasse 7, CH-8092 Zürich, Switzerland Interuniversity Microelectronics Centre Kapeldreef 75, B-3001 Leuven, Belgium Infineon Technologies Austria AG Siemensstrasse 2, A-9500 Villach, Austria Infineon Technologies AG Am Campeon 1-12, D Neubiberg, Germany Institut de Photonique et Electronique Quantique, Quantum Devices Group, EPFL, CH-1015 Lausanne, Switzerland Institut de Photonique et Electronique Quantique, LASPE EPFL, CH-1015 Lausanne, Switzerland Institut für Quantenelektronik (Laboratory for Quantum Electronics) ETH Zürich, Wolfgang Pauli-Strasse 16, CH-8093 Zürich, Switzerland IT IS Foundation for Research on Information Technologies in Society ETH Zürich, Gloriastrasse 35, CH-8092 Zürich, Switzerland Zeughausstrasse 43, CH-8004 Zürich, Switzerland AGC Automotive, Ypsilanti, USA Asher Sheppard Consulting, Redlands, USA ARCS, Seibersdorf, Austria Aristotle University of Thessaloniki, Thessaloniki, Greece BAG, Bern, Switzerland BASEXPO Consortium, Europe BfS, Salzgitter, Germany BORL-USZ, Zürich, Switzerland Boston Scientific Corporation, USA Campus of Ravenna, University of Bologna, Bologna, Italy Cancer Research UK, Beatson Laboratories, Glasgow, UK Chalmers University, Gothenburg, Sweden Charité, Berlin, Germany CTIA, Washington DC, USA Department Clinical Research and Veterinary Public Health, University of Bern, Bern, Switzerland Erasmus MC Rotterdam, Rotterdam, The Netherlands Exponent Inc., Menlo Park, CA, USA FAU Erlangen, Erlangen, Germany FDA, Washington DC, USA Forschungsgemeinschaft Funk e.v., Bonn, Germany Fraunhofer ITEM, Hannover, Germany GSM-Association, Genève, Switzerland Health Protection Agency, Chilton, London, UK IBT-ETHZ, Zürich, Switzerland 25

28 KTI LPN-EPFL MASCOT Consortium MAVT-ETHZ MHT Optic NANOSIL Consortium IMTEK, Freiburg, Germany INTEC, Gent, Belgium Incos Boté Cosmetic GmbH, Mainz, Germany IPM, Stockholm, Sweden IPT-UNIZH, Zürich, Switzerland ISTB, University of Bern, Bern, Switzerland Karolinska Institute, Huddinge, Sweden Laboratoire IMS, Uni Bordeaux, Bordeaux, France Laboratoire Clarins, Paris, France McGill University, Montreal, Canada MCL, London, UK MIT, Cambridge, USA MMF, Brussels, Belgium Motorola, Ft. Lauderdale, USA National Technical University of Athens, Athens, Greece NCCR Co-Me, Zurich, Switzerland NIEHS, Research Triangle Park, USA NIST, Gaithersburg, USA NOKIA NRC, Helsinki, Finland Philips Medical Systems, Best, The Netherlands Phonak Communications AG, Murten, Switzerland Schmid & Partner Engineering AG, Zurich, Switzerland Siemens Medical Solutions AG, Erlangen, Germany Toronto University, Toronto, Canada ULP, Strasbourg, France University of Basel, Basel, Switzerland University of Gent, Gent, Belgium University of Uppsala, Uppsala, Sweden University of Zürich, Zürich, Switzerland Zejiang University, Hangzhou, China ZonMW, The Hague, The Netherlands ZMT Zurich Med Tech, Zurich, Switzerland Kommission für Technologie und Innovation (Commission for Technology and Innovation, a Swiss Government Agency) Effingerstrasse 27, CH-3003 Bern, Switzerland Laboratory of Physics of Nanostructures EPFL, CH-1015 Lausanne, Switzerland Forschungszentrum Telekommunikation Wien Betriebs-GmbH, Wien, Austria Eidgenössische Technische Hochschule Zürich, ETH, Zürich, Switzerland Fraunhofer Institute for Telecommunications, Germany Fundació Barcelona Media, Universitat Pompeu Fabra, E Barcelona, Spain Politecnico di Torino, Torino, Italy Nokia Corporation, Finland Technische Universität Wien, Wien, Austria Professur für Mikro- u. Nanosysteme (Professorship of Micro- and Nanosystems at Department of Mechanical and Process Engineering) ETH Zürich, Tannenstrasse 3, CH-8092 Zürich, Switzerland MHT Optic Research AG Mandachstrasse 50, CH-8155 Niederhasli, Switzerland INPG Entreprise S.A., Seyssinet Pariset, France Institut Polytechnique de Grenoble, Grenoble, France The University of Warwick, Coventry, United Kingdom Rheinisch-Westfälische Technische Hochschule Aachen, Aachen, Germany Kungliga Tekniska Hogskolan, Stockholm, Sweden Consorzio Nazionale Interuniversitario per la Nanoelettronica, Bologna, Italy Universite Catholique de Louvain, Louvain-La-Neuve, Belgium Interuniversitair Micro-Electronica Centrum Vzw, Leuven, Belgium Commissariat a l Energie Atomique, Paris, France ST Microelectronics Crolles, Crolles, France Institut Superieur d Electronique et du Numérique, Lille, France Université Paris-Sud, Orsay, France Gesellschaft für Angewandte Mikro- Und Optoelektronik mbh, Aachen, Germany Forschungszentrum Jülich GmbH, Jülich, Germany 26

29 NEC NTT PORTES Consortium PULLNANO Consortium QP-NCCR Samsung SNF Qimonda Dresden GmbH & Co. OhG, Dresden, Germany Technische Universität Braunschweig, Braunschweig, Germany Universität Stuttgart, Stuttgart, Germany National Centre for Scientific Research Demokritos, Aghia Paraskevi Attikis, Greece University College Cork - National University of Ireland, Cork, Ireland Politechnika Warszawska, Warszawa, Poland Universidad Rovira i Virgili, Tarragona, Spain Chalmers Tekniska Hoegskola Aktiebolag, Göteborg, Sweden Ecole Polytechnique Federale de Lausanne, Lausanne, Switzerland Eidgenössische Technische Hochschule Zürich, Zürich, Switzerland Synopsys Switzerland LLC, Zürich, Switzerland The University of Glasgow, Glasgow, United Kingdom University of Liverpool, Liverpool, United Kingdom The University of Newcastle Upon Tyne, Newcastle upon Tyne, United Kingdom NEC Corporation System Devices Research Laboratories 1120 Shimokuzawa, Sagamihara, , Japan NTT Corporation Microsystem Integration Laboratories 3-1 Morinosato Wakamiya, Atsugi, Kanagawa , Japan Alstom Transport SA, Semeac, France Conseja Superior de Investigaciones Cientificas (CNM), Barcelona, Spain ETH Zürich, Zürich, Switzerland ST Microelectronics Crolles 2 SA, Crolles, France Philips Semiconductors Crolles R&D, Crolles, France Freescale Semiconducteurs Centre de Recherche Crolles SA, Crolles France NXP Semiconductors Belgium, Belgium NXP Semiconductors B.V., The Netherlands Infineon Technologies AG, München, Germany ST Microelectronics S.R.L., Agrate Brianza, Italy Interuniversity Microelectronics Centre, Leuven, Belgium Commissariat à l Energie Atomique, Paris, France Fraunhofer Gesellschaft zur Förderung der Angewandten Forschung e.v., München, Germany Centre National de la Recherche Scientifique, Paris, France Technische Universität Chemnitz, Chemnitz, Germany University of Newcastle Upon Tyne, Newcastle Upon Tyne, United Kingdom Université de Savoie, Chambery, France Technische Universität Wien, Wien, Austria Université Catholique de Louvain, Louvain la Neuve, Belgium University of Glasgow, Glasgow, Untited Kingdom Politechnika Warszawska, Warszawa, Poland Chalmers Technika Hoegskola Aktiebolag, Göteborg, Sweden Eidgenössische Technische Hochschule Zürich, ETH, Zürich, Switzerland Gesellschaft für Angewandte Mikro- und Optoelektronik GmbH, Aachen, Germany Forschungszentrum Jülich GmbH, Jülich, Germany University of Liverpool, Liverpool, United Kingdom National Technical University of Athens, Athen, Greece University College Cork - National University of Ireland, Cork, Ireland University of Warwick, Warwick, Coventry, United Kingdom European Synchrotron Radiation Facility, Grenoble, France University of Surrey, Guildford, United Kingdom Ion Beam Services, Rousset, France ISD Integrated System Development S.A., Halandri Athens, Greece Magwell NV, Heverlee, Belgium Acies SARL, Lyon France Infineon Technologies SC300 GmbH & Co.OHG, Dresden, Germany Consortio Nationale Interuniversitario per la Nanoelettronica, Bologna, Italy The Quantum Photonics National Center of Competence EPFL, CH-1015 Lausanne, Switzerland Samsung Electronics Co., LTD. San 24 Nongseo-Ri, Giheung-Eup, Yongin-City, Gyeonggi-Do, Korea Swiss National Science Foundation Wildhainweg 20, CH-3012 Bern, Switzerland 27

30 Sol Voltaics SOLID-ETHZ SPEAG STM SUGERT Consortium Synopsys Toshiba TU Graz Uni Armenia Uni Bologna Uni Bordeaux Uni Cagliari Uni Linz Uni Loughborough Uni Lund Uni Pisa Sol Voltaics AB Scheelevägen 17, Ideon Science Park, S Lund, Sweden Institut für Festkörperphysik (Laboratory for Solid State Physics) ETH Zürich, Schafmattstrasse 16, CH-8093 Zürich, Switzerland Schmid & Partner Engineering AG Zeughausstrasse 43, CH-8004 Zürich, Switzerland ST Microelectronics SA 850 Rue Jean Monnet, F Crolles, France ST Microelectronics SRL Via Carlo Olivetti 2, I Agrate Brianza (MI), Italy Fraunhofer Gesellschaft E.V. IISB, Erlangen, Germany austriamicrosystems AG, Unterpremstätten, Austria Infineon Technologies AG, München, Germany NXP Semiconductors Belgium, Belgium ST Microelectronics S.A., Crolles, France ST Microelectronics SRL, Agrate Brianza, Italy Synopsys Switzerland LLC, Zürich, Switzerland SIGMA-C GmbH Software, München, Germany (now Synopsys, Inc.) Commissariat à l Energie Atomique/LETI, Grenoble, France Interuniversity Microelectronics Centre, Leuven, Belgium Eidgenössische Technische Hochschule Zürich, ETH, Zürich, Switzerland Technische Universität Wien, Wien, Austria Synopsys Switzerland LLC Thurgauerstrasse 40, CH-8050 Zürich, Switzerland Synopsys Inc. 700 East Middlefield Road, Mountain View, CA 94043, USA Synopsys Inc. (former SIGMA-C GmbH) Thomas Dehler-Strasse 9, D München, Germany Toshiba Corporation 1-1. Shibaura 1-chome, Minato-ku, Tokyo , Japan Toshiba Corporation 2-5-1, Kasama, Sakae-ku, Yokohama , Japan Toshiba Corporation 1, Komukai, Toshibacho, Saiwai-ku, Kawasaki 210, Japan Technische Universität Graz Institute for Applied Information Processing and Communications (IAIK) Infeldgasse 16a, A-8010 Graz, Austria State Engineering University of Armenia Fiber Optics Communication Laboratory 105 Terian Strasse, Yerevan , Armenia Università degli Studi di Bologna Dipartimento di Elettronica Informatica e Sistemistica Via Zamboni 33, I Bologna, Italy Université de Bordeaux Laboratoire de l Intégration du Matériau au Système 351 Cours de la Libération, F TALENCE CEDEX, France Università degli Studi di Cagliari Dipartimento di Ingegneria Elletrica et Elettronica Piazza d Armi, I Cagliari, Italy Johannes Kepler University Altenberger Str. 69, A-4040 Linz, Austria Loughborough University Electronic & Electrical Engineering Department Leicestershire, LE11 3TU, United Kingdom Lund University, Lund University Box 117, S Lund, Sweden Università di Pisa Dipartimento di Ingegneria dell Informazione Via Caruso 2, I Pisa, Italy 28

31 Uni Purdue Uni Regensburg Uni Virginia VEST Vision-ETHZ VSEA Purdue University West Lafayette, Indiana 47907, USA Universität Regensburg, Institute for Experimental and Applied Physics D Regensburg, Germany University of Virginia Computer Science Department 151 Engineer s Way, Charlottesville, VA 22904, USA VEST Corporation, Le Manoir, F Lantheuil, France Computer Vision Laboratory ETH Zürich, Sternwartstrasse 7, CH-8092 Zürich, Switzerland Varian Semiconductor Equipment Associates, Inc. 35 Dory Road, Gloucester, MA , USA 29

32 Awards Peter Lüthi, Markus Wenk, Thomas Koch, Michael Lerjen, Norbert Felber, Wolfgang Fichtner received the WinTech 08 Demonstration Contest Second Prize for the Live Demonstration of their Multi-User MIMO Testbed by the ACM MobiCom Conference 2008 / WinTech 08 Demo Cotest, San Francisco, CA, USA, September 14-19, 2008 Christoph Studer, Peter Lüthi, Wolfgang Fichtner received the Student Best Paper Award for their conference paper VLSI Architecture for Data-Reduced Steering Matrix Feedback in MIMO Systems at the 2008 IEEE International Symposium on Circuits and Systems (ISCAS), Seattle, WA, USA, May 18-21, Sven Kühn received the BEMS Student Award for Best Platform Presentation at the 30th Annual Meeting of the Bioelectromagnetics Society, San Diego, CA, USA, June 8-12,

33 Qiuting Huang was appointed Cheung Kong Seminar Professor by the Chinese Ministry of Education for a three year period ( ) 31

34 Patents Title: Owner: Inventors: Patent No.: Computation of extrinsic information in a branch-and-bound detector ETH Zürich, Switzerland Christoph Studer, Andreas Burg, Helmut Bölcskei PCT/CH2008/ Title: Owner: Inventors: Patent No.: Modified distance increments for branch-and-bound detection ETH Zürich, Switzerland Christoph Studer, Andreas Burg, Helmut Bölcskei PCT/CH2008/

35 News 2008 and History of the Integrated Systems Laboratory (IIS) News 2008 IC and System Design and Test The worldwide first 4-stream IEEE n baseband transceiver in an application-specific integrated circuit (ASIC) has been developed in a research project with the spin-off company Celestrius. With 4 transmit and 4 receive antennas, the MIMO-OFDM modem reaches peak over-the-air data rates of up to 600 Mbps in 40 MHz bandwidth. Analog and Mixed-Signal Design Design and implementation of a high-speed, high-performance folding and interpolating analog-to-digital converter with digital calibration. The circuit reaches 10bits of resolution up to 250 Msps with a digital calibration scheme that enhances the linearity of the analog circuitry such that the latter can be optimized for speed. Technology CAD Ab-initio calculations for diffusion and clustering of phosphorus and fluorine based on first-principle physics. Results form the basis for the calibration of KMC (Kinetic Monte-Carlo) models in Synopsys process simulation tools. Computational Optoelectronics Full explanation of the spatio-spectral multimode properties in quantum-dot photonic crystal cavities, including spatial distribution of quantum dots and spontaneous emission enhancement due to cavity quantum electrodynamics. Applications are next generation nano-leds and single photon sources for quantum cryptography. Physical Characterization A research team in computational electron beam physics was established. Scientific topics concern sub-nanometer measurement of critical dimensions for wafer and mask-level scanning electron microscopy (SEM) of the 32 nanometer node and beyond as well as modeling and correction of the enhanced proximity effects occurring in high-resolution direct writing of wafers by electron beam lithography at low beam energies. Event organized by Integrated Systems Laboratory MASCOT First ETHZ Openhouse Event to present and demonstrate the multi-user MIMO communication system and testbed, a result of the European research project MASCOT (EU-IST-26905). ETH Zurich, 20 Feb New equipment 4-Channel Real-Time Oscilloscope LeCroy WaveMaster 808Zi (SDA), 8 GHz Bandwidth, 40 G Samples/s for the analysis of digital high-speed signals on current CMOS chip s digital inputs and outputs. History 1985 Appointment of Wolfgang Fichtner, Professor for Electronics, Department of Electrical Engineering, ETH Zurich. Formation of the research group VLSI in the Electronics Laboratory Foundation of the Integrated Systems Laboratory by merging of the research groups of Prof. Wolfgang Fichtner (Department of Electrical Engineering) and Prof. Martin Morf (Department of Computer Science). Start of the lecture series VLSI I: Architectures, VLSI II: Design, and VLSI III: Test and Fabrication (graduate EE, CS, and physics students) Foundation of the Microelectronics Design Center (Department of Information Technology and Electrical Engineering, associated to the Integrated Systems Laboratory) Start of the lecture Semiconductor Devices: Physical Principles and Simulation. Start of the project Education and Research in Microelectronics, generous funding by the board of ETH Zurich for IC integration and measurement equipment. Prof. Wolfgang Fichtner elected IEEE Fellow for the application of numerical modeling to device scaling and submicron transistor optimization Appointment of Qiuting Huang, assistant professor for Analog Integrated Circuits, Department of Information Technology and Electrical Engineering, ETH Zurich. Foundation of the IIS spin-off ISE Integrated Systems Engineering AG Zurich by IIS members (scope of business: software and application support in Technology CAD). Location for the first one and a half years at IIS with support of ETH Zurich. Start of the lecture Analog Integrated Circuits (graduate EE students) Start of the Swiss priority program MINAST Micro and Nano System Technology, program director Prof. Wolfgang Fichtner ( ), program direction established at IIS, total 56 Mio CHF granted by Swiss authorities and more than 60 Mio CHF contributions from Swiss industrial enterprises; IIS research projects: two in the module Integrated Microsystems Technology, four in the module Design, Simulation and Engineering of Microsystems, and one in the module Microsystems Applications. 33

36 1998 Promotion of Qiuting Huang to Professor for Electronics, Department of Information Technology and Electrical Engineering, ETH Zurich Accommodation of the research group Physical Characterization, including well known experts and advanced equipment from the former Reliability Laboratory at the Department of Information Technology and Electrical Engineering, ETH Zurich Accommodation of the research group Bioelectromagnetics/EMC from the Electromagnetic Fields and Microwave Electronics Laboratory at the Department of Information Technology and Electrical Engineering, ETH Zurich. Election of Prof. Wolfgang Fichtner as head of the Department of Information Technology and Electrical Engineering (holding this position from Oct 1999 until Sep 2004). Establishment of the Foundation for Research on Information Technologies in Society IT IS (Zurich, director Dr. Niels Kuster). Associated to ETH Zurich and a close research partner of the IIS research group Bio Electromagnetics/EMC IEEE Andrew S. Grove Award of the Year 2000 to Prof. Wolfgang Fichtner for outstanding contributions to semiconductor device simulations. Evaluation of the Department of Information Technology and Electrical Engineering, ETH Zurich, by a group of international experts with high scientific reputation. Overall qualification: The international standing of Integrated Systems Laboratory regarding its core activities is definitely among the best of the world Prof. Qiuting Huang elected IEEE Fellow for outstanding contributions to integrated circuits for wireless communications. Start of the lectures Semiconductor Devices and Communications Electronics (undergraduate EE students) International Conference on Numerical Simulation of Semiconductor Optoelectronic Devices NUSOD-02, September 2002, organized by IIS at ETH Zurich, 111 participants from Europe, USA, and Japan, 13 invited talks by well known experts from USA and Europe, 19 talks, 10 posters, and 5 company presentations ETH Zurich established the assistant professorship Computational Optoelectronics. Dr. Bernd Witzigmann was elected and has taken up this position at the Integrated Systems Laboratory on 1 March The Optoelectronics Laboratory (OptoLab) was founded as a common research instrument between IIS-ETHZ, IfE-ETHZ and IFH-ETHZ to support scientific work in fundamental and applied research projects with industrial partners. Spin-off ISE AG was acquired by Synopsys, Inc. and became Synopsys Switzerland LLC. It is a Swiss based subsidiary and the headquarter of Synopsys TCAD activities. It is partner in ISE s and in future European and national research projects. Start of the lecture series Advanced Optoelectronics (graduate EE students). 15th European Symposium Reliability of Electron Devices, Failure Physics and Analysis (ESREF) 2004, 4-8 October 2004, organized by IIS at ETH Zurich, 234 participants from Europe, USA, and Far East, 7 invited talks by well known experts from Europe, Far East, and USA, 52 talks, 40 posters, and an exhibition with 16 companies The National Institute of Health NIH (USA) has granted a research contract worth USD 5.6 Million in a single source procedure to the IT IS Foundation and the BioEM group. This grant is part of the largest single experiment of NIH and includes several endpoints relevant for the health risk assessment of mobile communication systems Appointment of Professor Qiuting Huang as Cheung Kong Seminar Professor by the Chinese Ministry of Education. 34

37 Research Projects IC and System Design and Test Coordinator: Norbert Felber 35

38 Real-Time Multi-User MIMO-OFDM Testbed Improvements and Measurements Real-time MIMO-OFDM Testbed Extension with SQRD-based MIMO Preprocessing Markus Wenk, Peter Lüthi, Patrick Mächler, Thomas Koch Peter Lüthi, Markus Wenk EU IST MASCOT EU IST MASCOT IKT-ETHZ, MASCOT Consortium IKT-ETHZ, MASCOT Consortium References: [D14] The ETHZ MIMO-OFDM testbed has been extended towards multi-user MIMO communication capabilities within the third and last year of the European research project MASCOT. Among others, effort has been spent on improvements and performance measurements of the entire hardware platform. A major redesign of the RF interface was necessary to enhance the communication with the analog-to-digital/ digital-to-analog conversion chip and the RF transceiver. Furthermore, adjustments in the synchronization block and enabling of soft-output MMSE detection helped to improve the error-rate performance of the entire MIMO communication system. Various measurements of the system performance were carried out. In digital loop-back mode, the transmit error vector magnitude of the digital signal processing was determined to be -34 db. For different channel scenarios, measurements with the PropSim channel emulator complemented the results. Finally, bi-directional over-the-air measurements were carried out involving the Ethernet PHY layer, the MAC layer, and the MIMO MAC and PHY layer. The results showed that the current MIMO-OFDM testbed is able to communicate reliably in 4x4 spatial multiplexing mode for up to 16-QAM modulation schemes. Last but not least, the ETHZ real-time testbed was demonstrated at the WinTech 08 demo contest in San Francisco, USA, and became second among 10 competitors. QR decomposition is a key preprocessing algorithm for multiple-input multiple-output (MIMO) communication systems. The extension of the MASCOT real-time MIMO- OFDM testbed with a MIMO preprocessing block based on QR decomposition allows for a variety of MIMO detection schemes, ranging from linear detection to advanced detection methods, such as successive interference cancellation (SIC) or sphere decoding. For the MIMO preprocessing in the real-time testbed, the minimum mean squared error (MMSE) sorted QR decomposition (SQRD) architecture of [Lüthi et al., ISCAS 2007] has been integrated as dual-core variant in an ASIC in UMC 180 nm 1P/6M CMOS technology. A customized printed circuit board (PCB) employing two instances of the MMSE-SQRD ASIC has been designed and manufactured. The PCB incorporates also two instances of a video digital-to-analog converter (DAC) designed for the VGA standard. These video DACs are intended to be used in the testbed as versatile visualization and debugging infrastructure and for demonstration purposes. The implemented MIMO preprocessing block employs two MMSE-SQRD ASICs clocked at 80 MHz and achieves an aggregated preprocessing throughput of four million matrix decompositions per second. The processing time for 48 complex-valued 4x4 matrices using MMSE-SQRDbased preprocessing amounts to ms. ETHZ MOMO-OFDM testbed and scatter plots of the constellation points for different modulation schemes in an overthe-air 4x4 MIMO-OFDM transmission scenario. Custom-designed PCB for integration of the MMSE-SQRD ASIC in the MASCOT real-time testbed. The implemented MIMO preprocessing architecture achieves an aggregated throughput of 4 million matrix decompositions per second. 36

39 VLSI Architectures for Gram-Schmidtbased QR Decomposition VLSI Architectures for QR Interpolation Sebastian Dütsch, Eugen Zgraggen (students); Peter Lüthi, Christoph Studer Christoph Rüegg (student); Peter Lüthi, Christoph Studer; IKT-ETHZ: Davide Cescato EU IST MASCOT ETHZ IKT-ETHZ, MASCOT Consortium IKT-ETHZ References: [D13] The QR decomposition (QRD) is an important matrix decomposition method for many detection algorithms in multiple-input multiple-output (MIMO) systems. It is, for example, used as preprocessing for ordered successive interference cancellation (OSIC) and tree-search-based detection schemes. There exist different algorithms for the implementation of QRD, for instance Givens rotations, Gram-Schmidt, or Householder reflections. This work focuses on the VLSI implementation of an iteratively sorted Gram-Schmidt (GS) algorithm. Although it is well known that the numerical stability of the GS-based QRD is critical, the numerical properties have shown to be adequate for a dedicated VLSI implementation after a thorough investigation and the development and application of a reduced floating-point technique. The GS algorithm has been implemented as VLSI architecture for MIMO preprocessing employing minimum mean squared error (MMSE) sorted QR decomposition (SQRD). Two versions of the architecture were successfully integrated as ASIC in UMC 180 nm 1P/6M CMOS technology. The implementation results have been compared with the existing Givens-rotations-based MMSE- SQRD ASIC (Lüthi et al., ISCAS 2007) and published at the Asia-Pacific Conference on Circuits and Systems 2008, Macao, China. Advanced wireless receivers based on MIMO-OFDM technology require the computation of a large number of QR decompositions (QRDs) for MIMO preprocessing. As, in general, the number of OFDM subcarriers increases more than the degrees of freedom of the underlying channel impulse response, an alternative to a brute-force QRD-approach is highly appreciated and might be more economic in terms of computational complexity and corresponding VLSI resources. Recent theoretical research has shown that, under certain conditions, it is possible to increase the computational efficiency by means of interpolation. In this master s thesis, the focus was put on the practical implementation of VLSI architectures for QR interpolation including the assessment of various design aspects, such as numerical precision and hardware complexity. A variety of approaches for an efficient hardware implementation has been proposed and a configurable VLSI architecture was designed. Synthesis results have shown that in some cases, the interpolation-based method is indeed computationally more efficient than the brute-force approach. Chip photograph of the MMSE-SQRD ASIC containing two architectures with different numeric precision. It has been designed to run at a clock frequency of 155 MHz, delivering 1.48 million matrix decompositions per second. Block diagram of the VLSI core component for QR interpolation. The component consists of a ring of interpolation cells surrounded by a dedicated set of memories, which can be shifted and swapped to allow for efficient computation with highest core utilization. 37

40 Automatic Gain Control and Noise Estimation for MIMO-OFDM Testbed Multi-User MIMO-OFDM Offline Testbed Jonas Balmer, Dominik Bischoff (students); Markus Wenk, Stefan Eberli, Thomas Koch, Patrick Mächler IKT-ETHZ: Michael Lerjen Thomas Koch, Patrick Mächler, Markus Wenk IKT-ETHZ: Michael Lerjen EU-IST MASCOT EU-IST MASCOT IKT-ETHZ, MASCOT Consortium IKT-ETHZ, MASCOT Consortium Automatic gain control (AGC) and noise estimation are two critical tasks in a MIMO communication system that can strongly influence error-rate performance in the receiver. Based on the received signal strength indication (RSSI) signal, the AGC adjusts the low-noise amplifier and the variable-gain control in the RF receive path in order to fit the signal into the optimal range of the analog-to-digital converter. The main challenge of a the AGC is to react as fast as possible to input signal changes, and to control the gain stages in the receive path. Once the synchronization block has detected periodicity, the gain settings are no more allowed to change. The AGC unit was implemented on the XILINX Virtex-4 FPGA of the ETHZ MIMO-OFDM testbed. Noise variance estimation is crucial in a wireless MIMO receiver in order to benefit from sophisticated receive algorithms. Various noise estimation algorithms are available in the open literature. An analysis thereof was accomplished in this thesis and different algorithms were compared in Matlab. The used noise estimation algorithm is based on the periodic short preambles transmitted at the beginning of each frame and operates in time domain. The noise estimator was designed for FPGA implementation and is located next to the synchronization block. Measurements carried out with the noise estimator revealed a noise-estimation error in the high-snr regime most likely due to transmit noise and non-linearities. The motivation for developing an offline testbed was its higher flexibility and ease of use compared to the realtime testbed. Different multi-user MIMO algorithms and scenarios can quickly be assessed offline, but with data acquired over real world channels under realistic conditions (including RF impairments and the like). Most of the signal processing tasks are carried out offline in a highlevel computing environment, such as Matlab. The offline testbed uses the same hardware infrastructure as the real-time testbed for the data acquisition, but in contrast, the baseband signal and MIMO processing is performed in Matlab. The baseband transmit signal is preprocessed in Matlab, loaded into a buffer, transmitted in real-time over the air or a channel emulator, and recorded in a buffer on the receive terminal. Finally, the received signal is read back into Matlab for further processing. The processing in Matlab includes synchronization of time and frequency, channel estimation, and data detection. Different algorithms can be selected and compared against each other. Transmitter parameters and algorithms are set over a graphical user interface. The framework also supports multi-user transmissions from two transmitting boards to one receiving board. It could be shown that simultaneous transmission to both users is more efficient than time-multiplexed access. The figure above the ETHZ MIMO-OFDM testbed architecture shows the received signal. First, the AGC adjusts the input swing. Then, the noise variance is estimated based on the preambles. Top: Estimated channel amplitudes and scattering plot of a 4x4 MIMO system Bottom: Measurement setup for multi-user transmission experiments. 38

41 2x2 MIMO-OFDM Baseband Processing on a Reconfigurable Processor Matrix Preprocessing for MIMO-OFDM on the SOL Processor Stefan Eberli Benjamin Dietrich, Lukas Haas (students); Stefan Eberli IKT-ETHZ: Davide Cescato KTI-8537 NMPP MIMO2, BridgeCo KTI-8537 NMPP MIMO2, BridgeCo BridgeCo BridgeCo, IKT-ETHZ References: Eberli et al., Microel. Journal 2009 *) In the near future, WLANs will spread more and more into the homes, where the increasing data traffic (e.g. music, video streaming) calls for higher throughput than the currently supported 54 Mbps which do not suffice for real-time streaming of high-quality audio/video for multiple users. To this end, standards that embed multiple-input multipleoutput (MIMO) techniques to enable higher throughput, are reaching the market (e.g. IEEE n standard). In this project, the hard computational kernels of a 2x2 MI- MO-OFDM receiver were implemented on a platform with two reconfigurable instruction set processors (RISP). The partitioning and mapping of the receiver onto two RISPs respects the structure of the employed algorithms. The first RISP performs the OFDM frame synchronization and OFDM processing, for which the hard computational kernels are mainly correlations and fast Fourier transforms. The second RISP executes the MIMO detection, where matrix inversion and matrix-vector multiplications are the hard computational kernels (see column to the right). For the 2x2 MIMO-OFDM receivever to operate in real time, both RISPs have to run at a clock frequency of 250 MHz. The figure below shows the floorplan of the OFDM processing RISP. The design runs at a clock frequency of 250 MHz (after backend design) and occupies an area of 3.95 mm 2 on a 180 nm CMOS process. The building blocks and their areas are highlighted. DICT MEM: dictionary memory, INSTR MEM: instruction pointer memory, SU: storage unit, RF: register file, CALU: complex-valued ALU, CMAC: complex-valued MAC unit. *) Implementation of a 2x2 MIMO-OFDM Receiver on an Application Specific Processor, in press, to be published in References: [D6] Matrix inversion is a hard computational kernel of linear minimum mean-squared error (MMSE) multiple-input multiple-output (MIMO) receivers. The SOL processor developed at ETHZ is a reconfigurable instruction set processor (RISP) that is configurable at design-time with execution units tailored to the application to be implemented. In this project, two matrix inversion algorithms were mapped onto the SOL-RISP, a Rank-1 update method and a divide-and-conquer method. First, the two algorithms were re-arranged to fit best onto the RISP, and the required atomic operations were identified. Next, the execution units were designed. The configuration chosen to support both matrix inversion algorithms comprised one real-valued divider (DIV), one complex-valued ALU (CALU), two complex-valued MACs (CMACs), as well as storage units (SUs), and a register file (RF) for temporary data storage. The dictionary memory (DICT MEM) stores unique instructions that are addressed by the instruction pointer memory (INSTR MEM). Finally, the backend design was performed and the assembler code implementation of both algorithms for different antenna configurations was written. The figure below shows the floorplan of the implemented RISP and highlights the different building blocks. The design runs at a clock frequency of 250 MHz and occupies an area of 3.7 mm 2 on a 180 nm CMOS technology. With this implementation, a 2x2, 3x3, or 4x4 matrix is inverted in 11, 59, or 83 clock cycles, respectively. This RISP is employed for the MIMO detection block in the 2x2 MIMO- OFDM receiver described in the column to the left. Top: Simplified view of the 2x2 MIMO-OFDM receiver (continued in the column to the right). Bottom: Floorplan of the OFDM processing RISP. Top: 2x2 MIMO-OFDM receiver (continued from previous column). Bottom: Floorplan of the MIMO detection RISP. 39

42 A 4-Stream Baseband Transceiver ASIC for IEEE n Verification Framework for Wireless Baseband Transceivers A. Burg, S. Haene, Ch. Senning Celestrius: M. Borgmann, D. Baum, Th. Thaler, F. Carbognani, S. Zwicky, L. Barbero, P. Greisen, C. Foelmli, U. Schuster, P. Tejera, A. Staudacher Thomas Peter, Simon Haene, Andreas Burg Celestrius: Pierre Greisen, Ulrich Schuster KTI PFNM-NM, Celestrius KTI PFNM-NM, Celestrius IKT-ETHZ, Celestrius Celestrius The IEEE n wireless LAN standard relies on multiple-input multiple-output (MIMO) technology with up to 4 spatial streams to provide high data rates across a wide range with wire-like quality of service. Unfortunately, the circuit complexity of a corresponding MIMO baseband transceiver grows rapidly with the number of spatial streams. Hence, current commercial implementations of IEEE n support only up to 2 streams with 2 or 3 antennas and are limited to data rates of 300 Mbps. In this research project, a fully IEEE n compliant MIMO-OFDM baseband transceiver ASIC was developed. The circuit is the worldwide first implementation of IEEE n that supports up to 4 spatial streams with a bandwidth of 40 MHz to achieve up to 600 Mbps throughput. The innovative architecture of the industrial-grade design was tailored to efficiently handle the complexity of modern communication standards and is well suited as a basis for a variety of future research projects. The initial implementation was realized in a 130 nm CMOS technology. The manufactured prototype ASIC employs a soft-output MMSE receiver for MIMO detection. Optimizations on the algorithm and architectural level lead to a core area of the 4-stream transceiver that is almost on par with the area of commercial state-of-the-art 2-stream IEEE n transceiver ASIC implementations. A powerful verification framework has been developed to test an IEEE n-compliant WLAN transceiver physical layer (PHY) ASIC developed by the ETHZ spin-off company Celestrius. The framework supports all aspects related to functional verification, debugging, regression testing, architecture exploration and interoperability testing. A wide range of scenarios can be simulated on a bit-true MATLAB model of the transceiver or on an HDL simulator based on the VHDL implementation. In addition, also FPGA emulation, based on a commercial hardware platform, is supported. The extent of the simulated scenarios scales from simple functional tests to complex performance measurement sequences. FPGA emulation is essential to acquire significant statistical performance data in a reasonable time span. A specific simulation scenario for the verification framework is defined by a test case which is a hand-written MATLAB function following a clearly defined syntax. Test cases describe what kind of events are to be simulated, such as packet transmission and reception, configuration, and readout of the current state of the PHY. Test cases also contain information about the simulated modulation schemes, payload data sizes, channel realizations and signal power. Test cases are platform independent and can be executed on all three platforms (MATLAB, HDL simulator and FPGA). Based on test cases, the framework generates and applies stimuli to any of the three platforms and compares their output. The final result may range from simple bit or frame error-rate plots to statistical performance figures. Die photograph of the CLSN601P 4-stream baseband ASIC implemented in a 130 nm technology. The core area of the circuit is 14.4 mm 2, including 49 memories and a PLL. It operates at clock frequencies of 80, 160, and 320 MHz. The verification framework can emulate the VHDL design on an FPGA to significantly reduce the amount of time, compared to HDL simulation, required to extract statistical performance figures for the baseband transceiver. 40

43 Channel Matrix Preprocessing for IEEE n Soft-Output Sphere Decoder for IEEE n Andreas Staudacher (student); Christian Senning, Andreas Burg Christoph Studer, Andreas Burg Celestrius: Markus Laner, Moritz Borgmann KTI PFNM-NM, Celestrius KTI PFNM-NM, Celestrius Celestrius Celestrius References: [D19] One of the main challenges in the design of the IEEE n compliant Celestrius MIMO transceiver was the implementation of the channel-matrix preprocessing. For this problem, the QR decomposition is widely regarded as the most versatile algorithm since it can serve as preprocessing for various types of MIMO detectors. The goal of this project was the VLSI implementation and optimization of a QR decomposition circuit that meets the stringent latency and throughput requirements of an IEEE n transceiver. The precision requirements are set to support the highest-rate modes of the standard which are based on 64-QAM modulation with 4 spatial streams. In order to achieve these goals, the new architecture was designed as a deeply pipelined systolic array built from a library of parameterized processing elements. Common costly operations are delegated to shared processing elements in order to achieve good hardware utilization and low silicon area. The first implementation of the QR decomposition unit supports linear MMSE detection and has been taped out as part of the CLSN601P prototype transceiver ASIC. The two subsequent implementations add two different sorting strategies to the original design in order to support both a soft-output and a fixed-complexity sphere decoder. All three implementations operate at a clock frequency of 320 MHz in a 130 nm process and occupy a silicon area of 200 kge. In terms of throughput, the implemented architecture achieves 20 million QR decompositions of complex-valued 4x4 channel matrices per second. Accounting for the difference in process technology, the hardware efficiency is almost on par with the Givens-rotations-based MMSE-SQRD implementation (Lüthi et al., ISCAS 2007). Soft-output detection in multiple-input multiple-output (MIMO) wireless systems based on sphere decoding (SD) yields superior performance compared to that of linear soft-output MIMO detection. SD-based MIMO detection is key to enable the high-throughput-modes of modern wireless communication standards. In particular, soft-output MIMO detection based on single-tree-search (STS) SD was shown to achieve near-optimal error-rate performance at low computational complexity and enables the peak throughput of 600 Mbit/s in IEEE n. In this project, the STS-SD algorithm has been optimized for soft-output detection in the IEEE n physical layer (PHY) designed by Celestrius. The variable run-time of STS-SD poses problems in practical applications. To this end, a novel technique referred to as FIFO scheduling has been developed. The goal of this method is to instantiate several STS-SD cores and to impose individual runtime constraints based on the number of received data in the FIFO queue. Simulation results indicate that FIFO scheduling yields superior performance compared to other scheduling techniques (e.g., maximum-first scheduling) and is well-suited for integration in the Celestrius PHY. Numerous performance and complexity simulations have shown that the STS-SD with FIFO scheduling yields superior performance compared to state-of-the-art linear MIMO detection schemes and enables the high-throughput-modes of IEEE n in a practical system. Systolic architecture of the QR decomposition. Every 16 cycles, the data is passed from one block to the next. In the die micrograph of the CLSN601P prototype ASIC, the QR decomposition and the MMSE equalizer are highlighted. Impact on average number of visited nodes (i.e., computational complexity) by the FIFO buffer depth. The scheduler (bottom left) consists of a FIFO, a distribution unit, several STS-SD cores, and a collector unit. 41

44 Configurable High-Throughput Decoder Architecture for Quasi-Cyclic LDPC Codes VLSI Implementation of Max-Log M-BCJR Algorithms for Iterative MIMO Decoding Nicholas Preyss, Christoph Roth (students); Christoph Studer, Andreas Burg Schekeb Fateh, Dominik Riha (students); Christoph Studer, Christian Benkeser KTI PFNM-NM, Celestrius ETHZ References: [D21] The quality-of-service and throughput requirements of modern wireless communication systems require highperformance error-correction schemes. Low-density parity check (LDPC) codes are promising candidates for next-generation wireless systems due to the excellent error-correction capabilities. In this project, a configurable LDPC decoder architecture for quasi-cyclic (QC) codes has been designed. The proposed architecture is able to decode virtually any QC- LDPC code that fits into the allocated memories while achieving high decoding throughput. The VLSI implementation has been optimized for the IEEE n WLAN standard, but can be used for other standards as well. Additionally, low-power techniques (e.g., clock gating) have been employed in order to reduce the power consumption of the decoder. The QC-LDPC decoder has been implemented in 180 nm CMOS technology, requires a core area of 3.39 mm 2, and achieves up to 780 Mbit/s decoding throughout at a maximum clock frequency of 208 MHz. The energy efficiency is ranging from 1.9 nj/bit to 6.0 nj/bit, depending on the block-length and the code rate. Comparisons with nonconfigurable LDPC decoders have shown that the flexibility of this architecture does not lead to a performance penalty, neither in terms of area, throughput, or energyefficiency. Iterative detection and decoding in multiple-input multipleoutput (MIMO) wireless communication systems offers better quality-of-service and higher system throughput compared to that of soft-output MIMO detection. These gains come at the cost of significantly increased computational complexity in the MIMO detector and in the channel decoder. The goal of this project was to evaluate the hardwarecomplexity and throughput of soft-input soft-output channel decoders for convolutional codes. To this end, a windowed approximation of the BCJR algorithm [Bahl, Cocke, Jelinek, and Raviv, IEEE Trans. IT, 1974] has been used (referred to as max-log M-BCJR). Five different architectures have been implemented for five different codes. These codes differ in the number of states (i.e., 4, 8, 16, 32, and 64) and achieve different error-correction capability. The 64-state BJCR decoder achieves the best error-rate performance and is compliant to the IEEE n WLAN standard. All five M-BCJR architectures have been implemented in 180 nm (1P/6M) CMOS technology. The first ASIC contains the 64-state variant, whereas the remaining decoder cores have been implemented on the second ASIC. All M-BCJR cores achieve a maximum clock frequency of 375 MHz, which leads to 375 Mbit/s. The circuit area ranges from 0.22 mm 2 to 2.37 mm 2 for the 4-state and 64-state decoder, respectively. ASIC photo of the LDPC decoder (left). The VLSI architecture (right) consists of two memories, 81 node computation units, and three cyclic shifters. ASIC photos of the max-log M-BCJR decoders. Left: IEEE n-compliant 64-state max-log M-BCJR decoder. Right: 4-, 8-, 16-, and 32-state max-log M-BCJR decoders. 42

45 Finite Lattice-Size Effects in MIMO Detection VLSI Implementation of the LLL Algorithm for MIMO Detection Christoph Studer IKT-ETHZ: Dominik Seethaler, Helmut Bölcskei Lukas Bruderer (student); Christoph Studer, Markus Wenk IKT-ETHZ: Dominik Seethaler ETHZ EU-IST MASCOT IKT-ETHZ IKT-ETHZ References: [D21] Many powerful data detection algorithms employed in multiple-input multiple-output (MIMO) communication systems, such as sphere decoding (SD) or lattice-reduction (LR) aided MIMO detection, were initially designed for infinite lattices. Detection in MIMO systems is, however, based on finite lattices. In this project, the consequences of finite lattice size for the performance and complexity of MIMO detection algorithms (formulated for infinite lattices) are studied systematically. It has been shown that relaxation from finite to infinite lattices, combined with LR, can reduce the tree-search complexity of SD, but generally leads to a significant (errorrate) performance loss. This performance loss is caused by the fact that the relaxed detector does not necessarily deliver estimates that belong to the finite lattice, and hence, does not realize optimum performance. Remapping methods (from the infinite to the finite lattice) that yield (close-to) optimal performance necessitate to solve an additional finite-lattice closest-vector problem (CVP). Hence, if optimum performance is required, SD on the finite lattice seems to require lower complexity since remapping is avoided and only one finite-lattice CVP needs to be solved. Considering both performance and complexity, LR-aided MIMO detection does not seem to offer advantages in combination with SD, but is rather suited for low-complexity algorithms, such as successive interference cancellation or linear detection. Lenstra-Lenstra-Lovasz (LLL) lattice reduction (LR) can be used to improve the error-rate performance of lowcomplexity data detection in multiple-input multiple-output (MIMO) wireless communication systems. In particular, LLL-aided successive interference cancellation was shown to achieve the same diversity order as optimum (i.e., maximum likelihood) MIMO detection and is hence, a viable option for low-complexity detection in practical MIMO systems. In the first part of this project, algorithmic and VLSI implementation aspects of various LR algorithms have been investigated. The most promising LR algorithms (in terms of performance and complexity) have been identified: 1) the LLL algorithm and 2) the Siegel-Clarkson (SC) variant of the LLL algorithm. Both algorithms have been optimized to reduce the VLSI implementation complexity. The goal of the second part of this project was to design a VLSI implementation of the LLL and SC-LLL algorithm. The architecture contains a CORDIC (coordinate rotation digital computer), an array of four complex-valued multipliers, and three memories (register files) for complexvalued 4x4-dimensional matrices. The design has been implemented in 130 nm (1P/8M) CMOS technology. The resulting ASIC achieves a maximum clock frequency of 333 MHz, requires 1.61 mm 2 core area (corresponding to 101 kge) and produces a sustained throughput of 5.6 M lattice-reductions (of 4x4-dimensional matrices) per second. Top right: The transmitted lattice point (x ) is transformed and translated by the channel matrix (G) and the additive noise (n). Bottom left: bit error rate (BER) of maximum likelihood (ML) decoding and LR-aided MIMO detection. ASIC layout of the chip in 130 nm CMOS technology containing the Lenstra-Lenstra-Lovasz (LLL) and the Siegel-Clarkson-LLL algorithms. 43

46 SHA-3 Proposal BLAKE EnRUPT Hash Function Specification Luca Henzen FHNW: Jean-Philippe Aumasson, Willi Meier Uni Loughborough: Raphael C.-W. Phan Luca Henzen VEST Corporation: Sean O Neil Uni Virginia: Karsten Nohl ETHZ ETHZ FHNW Windisch, Uni Loughborough VEST, Uni Virginia References: [D1] The BLAKE hash function has been submitted as formal SHA-3 candidate to the U.S. National Institute of Standards and Technology (NIST) cryptographic hash algorithm competition. BLAKE meets all the criteria set by NIST, offers theoretical and empirical security guarantees, and performs well in high-end PC s. It is constructed on previously studied components, chosen for their complementarity. The heritage of BLAKE is threefold: BLAKE s iteration mode is HAIFA, an improved version of the Merkle-Damgard paradigm. BLAKE s internal structure is the local wide-pipe, which has already been used in the LAKE hash function. BLAKE s compression algorithm is a modified version of Bernstein s stream cipher ChaCha, for which the security has intensively been analyzed, the performance is excellent, and the architecture is strongly parallelizable. In hardware, the scalable structure of BLAKE s round function allows the implementation of distinct architectures, with a wide trade-off range between area and speed. Fast implementations are able to achieve 6 Gbps throughput in 180 nm CMOS technology and 3 Gbps in a Xilinx Virtex-4 FPGA, while slower, lightweight architectures require less than 10 kge ASIC resources or 1000 Virtex-4 slices. References: [D15] The EnRUPT hash function has been submitted as formal SHA-3 candidate to the U.S. National Institute of Standards and Technology (NIST) cryptographic hash algorithm competition. ïrrupt is the iterative-stream hash mode of the En- RUPT family. It is able to process a message, one w-bit word at a time, and to produce a condensed representation of the message, called message digest. Seven stream hash functions are proposed for general-purpose use: ïrrupt32-128, ïrrupt32-160, ïrrupt32-192, ïr- RUPT64-224, ïrrupt64-256, ïrrupt and ïr- RUPT These proposed algorithms differ mostly in the number of bits of security provided for the data being hashed, which is half of the message digest size. The performance of twelve implemented ïrrupt architectures with different degrees of parallelization (P=1, 2, 4), word sizes, and round structures, demonstrate the advantage of the EnRUPT stream hashing for hardware applications: In ASICs and FPGAs, the 8-ïrRUPT circuits are the fastest (especially for P=4), matching the needs of modern high-speed communication links. The 1-ïrRUPT architecture is a more suitable alternative for limitedresource applications like radio-frequency identification (RFID) systems or smart cards. Block diagram of the BLAKE compression function. A 512/1024-bit register-based memory stores the internal state V. The round module hosts the G functions for the computation of the round process. Area vs. processing time of the investigated ïrrupt circuits. The 8-ïrRUPT cores achieve the highest speed, however the 4-ïrRUPT with P=4 are the most efficient architectures concerning speed/area trade-offs. 44

47 Hardware Characterization of Cryptographic Primitives Fast AES Cipher Core on ASIC with New Cells based on CMOS and Pass- Transistor Logic Luca Henzen, Flavio Carbognani Fabio Coduri, Claudio Pagnamenta, Remo Poretti (students); Luca Henzen, Flavio Carbognani ETHZ ETHZ References: [D10], [D12] In secure environments and digital data transmission systems, cryptographic primitives play a cardinal role for privacy, identification, or data integrity. While the average performance of these algorithms on high-end processors is generally not critical, ease of implementation and flexibility in hardware are crucial. Several applications rely indeed on their security features on hardware-dedicated cores. Therefore, finding the suitable cryptographic algorithm, which is able to guarantee the required security level and to match all resource constraints, becomes a key factor. The aim of this project was the VLSI evaluation of such cryptographic primitives. For investigating a wide range of architectures, every algorithm has been described in hardware. Different trade-offs between speed and area allowed the classification in terms of maximal operational frequency, throughput, memory, and area. The estream candidates Grain, Salsa20 and the successor stream cipher ChaCha have been implemented in 180 nm CMOS technology. With the same design flow, the cryptographic hash functions RadioGatun, MAME, and LAKE have been designed in ASIC and FPGA. This project aimed at high-speed implementations of the Advanced Encryption Standard (AES) cipher on ASICs. The goal was to reach the highest throughput possible by using standard cells, and even further improvements in throughput with a new kind of cells based on pass-transistor logic (PTL). First, the Rijndael algorithm has been implemented using several high speed strategies like iterative design decomposition and deep pipelining. Meanwhile, comparisons between PTL cells and standard CMOS logic cells have been conducted. The investigation of the results led to a new kind of hybrid logic (HL) cells that have been developed using both technologies, taking profit of the PTL speed and supporting it with the stability of the CMOS logic. The fastest implementation involved six stages of pipelining inside each round of the AES core, allowing a simulated throughput of 100 Gbps with moderate increase in area and cost. Due to the limited chip size for student projects, a smaller and slower version has been chosen and implemented once using the standard CMOS cells and once with the new hybrid logic cells. Block diagram of the implemented hash function LAKE. The initialization (saltstate), the internal round function (processmessage), and the finalization (feedforward) are the main components of LAKE s compression function. Chip layout of two (mirrored) high-speed AES cores with pipelining: Top: Reference with standard CMOS cells. Bottom: Speed-enhanced AES with hybrid cells. 45

48 Research Projects Analog and Mixed-Signal IC Design Coordinator: Qiuting Huang 46

49 High-Speed Pipelined A/D Converters in Deep-Submicron CMOS Technology High-Speed Folding and Interpolating A/D Converters Employing Digital Calibration Jürg Treichler Yihui Chen ETHZ ETHZ The development of analog-to-digital converters (ADCs) is driven by an increasing demand for high data rates at adequate resolutions. While oversampling ADCs excel at high resolutions but only achieve moderate bandwidth, flash converters situate themselves at the other end of the spectrum, providing enormous data rates at the price of low accuracy. Pipelined ADCs offer an interesting tradeoff. While they may operate at speeds of several tens to hundreds of MSamples/s, they still achieve sufficiently high resolutions for modern communication systems. Considering that mainstream technologies continue to offer reduced minimum feature sizes, the inner architecture of ADCs has to adapt to these changes. Newly available processes are well suited to high speeds, but present difficult challenges if high resolutions are to be achieved. Most publications in the field of pipelined ADCs dealing with modern technologies that have been published during the past three years therefore limit themselves to high bandwidths. Pipelined ADCs with high resolutions, on the other hand, are increasingly scarce, as the lower available signal swing imposes harder limits on the achievable signal-to-noise ratio (SNR). The aim of this project was to partially counteract this tendency by designing and implementing a pipelined ADC featuring a resolution clearly exceeding 11 bits, a sampling rate around 100 MSamples/s, and a competitively low power consumption. The chip has been fabricated in a 130 nm process with a supply voltage of 1.2 volts. Digital error correction schemes, implemented on-chip, help to increase the effective resolution. In recent years, unrelenting growth in digital communications, multimedia, and other consumer products has translated into increasing demands for analog-to-digital converters (ADCs) with 8-10 bits resolution and sampling rate in excess of 100 MSample/s. Folding and interpolating architecture inherits speed advantages from flash one, and usually only needs low complexity building blocks, which makes it attractive for mainstream CMOS processes. However, its resolution is severely limited by the poor matching properties of the differential pairs and current mirrors. The interpolating and averaging techniques improve linearities, but fairly large transistors are indispensable to keep the offset low, which limits the achievable speed with a fixed power budget. This project employs an innovative digital calibration technique, which directly measures the offsets of preamplifiers and first stage folding amplifiers from raw digital codes of the folding ADC core, and accomplishes corrections in digital domain. This scheme only adds a few additional analog elements, but relaxes the matching requirements on the aforementioned amplifiers substantially. As a result, those amplifiers can be realized with smaller transistors, which improves the speed-accuracy-power tradeoff. A prototype circuit has been fabricated in a 0.13 μm CMOS technology with a supply voltage of 1.2 V. Rendered layout of the self-calibrating comparators in the first pipeline stage, hovering over a chip photomicrograph. The sampling capacitors of the comparators are visible in the front. Layout of folding and interpolating ADC employing digital calibration technique 47

50 Highly-Linear D/A Converters as a Building Block for High-Performance A/D Converters A/D Conversion for Multi-Standard Wireless Receivers Craig Keogh Thomas Christen ETHZ ACP Digital-to-analogue (D/A) converters serve as vital building blocks in high-performance Analogue-to-Digital ( A / D) converters that require feedback. The linearity of the constituent D/A converter in many cases is of crucial importance as it can adversely impact on the linearity performance of the overall A/D converter. One major source of non-linearity in contemporary D / A converter designs arises from the imperfect matching accuracy of the technology used to implement the converter s unit elements. Calibration techniques can be used to improve the linearity of D/A converters by measuring the amount of mismatch present between unit elements and applying a correction signal proportional to this mismatch. They can be broadly classified into one of two types: start-up calibration and background calibration methods. Start-up calibration, as its name suggests, is performed once during system start-up and hence cannot correct mismatch that results from thermal drift or long-term operation. Background calibration, on the other hand, can correct the mismatch arising from temperature and operational changes by working continuously behind the scenes during the data conversion. Since the calibration should not interfere with the data conversion, background calibration techniques are often more complex and difficult to implement than the aforementioned start-up calibration technique. This project involves the design, implementation and fabrication of a highly-linear and low-power D/A converter suitable for deployment in A/D converters. The D/A converter employs analogue background calibration and is implemented in a 1-poly, 6-metal CMOS 0.13 mm technology operating at supply voltage of 1.2 V. As data-centric application proliferate in both cellular and local area networks, higher data-rate expectations continue to precipitate newer wireless standards, while popular incumbent standards must be retained. From the user s point of view, the current trends call for designs that allow convergence of wireless services, allowing access to different standards from the same wireless device and cost effective solutions for intercontinental roaming. For space and cost reasons, hardware has to be shared as much as possible in this devices. Reconfigurability of wireless radios, or software defined radio (SDR), has therefore become a focus of recent research. Analog hardware is generally seen as an impediment to adaptability and its reduction a desirable outcome in the quest for SDR, especially as scaling of CMOS down to 100nm and below increasingly favors digital design over analog. High-performance ADCs are therefore an enabling component in the design of multi-standard radios. The goal of this research project is to develop a multimode ADC that fulfills the high requirements given by the various standards. In order to cope with current (GSM, UMTS etc.) and future wireless standards (WiMAX, UMTS-LTE etc.), the implemented ADC aims at resolutions over 14 bits at a bandwidth of 100 khz (for narrowband standards such as GSM), and resolutions of 11 bits for a bandwidth of 20 MHz (for broadband standards such as IEEE802.11n). A multi-mode DS modulator prototype that achieves the abovementioned requirements has been in implemented in 0.13 mm CMOS in this project. Layout of one of the transconductance cells used in the circuit. Physcial dimensions of this cell are 32 mm x 33 mm. Layout view of the implemented multi-mode DS modulator. 48

51 Multi Band Transmitter Design for LTE Mobile Communications Multi-Standard RF Receivers for Mobile Communications Dario Albino Carnelli Thomas Dellsperger Hasler Stiftung ACP ACP Although UMTS, with HSDPA and HSUPA delivers high data transfer rates, wireless data usage is expected to increase significantly over the next few years. The 3 rd Generation Partnership Project (3GPP) has developed and is optimizing the 3G Long Term Evolution (LTE) as a new standard to cope with future demand. The introduction of LTE aims at boosting the communication data rates with an air interface that allows higher spectral efficiency combined with increased spectrum flexibility and MIMO antenna technology advantages. Moreover, the introduction of a new modulation scheme called Single Carrier Frequency Division Multiple Access (SC-FDMA) for transmission establishes a good compromise between peak to average power ratio and hence transmitter power efficiency and spectral efficiency. This project focusses around the design of a multi band LTE user equipment (UE) transmitter that will face the impact of SC-FDMA on the direct conversion transmitter architecture. In particular, it highlights the critical aspects that have to be considered in order to meet the requirements defined by the air interface protocol standards. A system level analysis has been done that gives a thorough insight to the baseband signal processing functions and to describe specification details for each constituting block The idea of a multi-standard RF receiver is to accommodate a certain set of mobile communication standards in a single RF receiver by reconfiguration of its elements. Such a reconfigurable RF receiver can be expected on the one hand to substantially lower the bill of materials (BOM), and on the other hand to reduce the design effort if yet another standard should be accommodated. An all-digital software-defined radio in which the RF signal is fed into the analog to digital converter (ADC) right after the antenna would be the ideal candidate for a reconfigurable RF receiver. However, this provoking vision entails several obstacles for cellular phone handsets. The dynamic range requirements imposed on the ADC get excessively high and prevent an all-digital softwaredefined radio from being a viable solution. Nonetheless, a reconfigurable RF receiver becomes feasible (a) by retaining the paradigm of shifting as much signal processing as possible from the analog to the digital domain and (b) by employing broadband and/or reconfigurable signal processing wherever possible for the remaining analog parts. Along this line, a multi-standard RF receiver based on a direct conversion architecture has been implemented in 0.13 mm CMOS in this project. For a fully-fledged multistandard GSM/WCDMA receiver, the developed RF receiver can be complemented by off-the-shelf RF and BB components. For such a receiver, the reconfiguration capabilities remain mainly limited by these off-chip components such as RF band pass filters. Top: PSD signal before and after the baseband filter and a scatter plot on 16 QAM transmission. Bottom: schematic view of the direct conversion architecture applied to an LTE digital transmitter. Screenshot of a modulation accuracy measurement after the demodulation of a WCDMA signal by the developed multi-standard RF receiver. 49

52 Integrated Frequency Synthesizer for RF Multi-Mode Applications A 58mW 1.2 mm 2 HSDPA Turbo Decoder ASIC Yangjian Chen Christian Benkeser, Andreas Burg Hasler Stiftung ETH ACP References: ISSCC 2008, JSSC 01/2009 Even with the maturing of third-generation (3G) communication systems and the expectation that it will eventually replace the second-generation (2G) systems, the cellular market will still be experiencing a coexistence of 2G/2.5G/3G for several years. Therefore, multi-mode (or mulit-standard) RF transceivers will become increasingly popular and important in the near future. As a key block of multi-mode RF transceivers, the frequency synthesizer needs to meet the stringent specifications of phase noise and spurs, frequency accuracy and switching speed required by both 2G and 3G standards. Beside that, targeting high integration level and low power consumption makes the design even more challenging. In this project, a fractional-n frequency synthesizer is for a 2G/3G multi-mode RF transceiver using 130 nm CMOS technology is investigated. A SD modulator is used to shape the intrinsic quantization noise and to break the patterns from which spurs are generated. Beside meeting the requirements of 2G/3G standards, this frequency synthesizer is capable of switching very fast and consumes a small die area. Also, a highly linear phase frequency detector and charge pump will eliminate the mechanism of quantization noise folding back into the signal pass band. The high power level of 3G mobile phones, especially at the high data rates supported by High Speed Downlink Packet Access (HSDPA), still impedes the migration of users to the next generation of mobile phones. Therefore, new low-power, low-cost solutions for HSDPA signal processing blocks are required to guarantee the future sucess of 3G mobile phones. Turbo decoders are specified for the baseband part of the receiver in HSDPA mobile phones. In this project, several turbo decoder structures have been investigated, simulated and compared. Various architectural trade-offs have been analyzed and appropriate choices have been made to achieve the high data rates required by HSDPA at a low power level. Moreover, the turbo decoder has to handle all the specified block lengths to be standard compliant, which leads to a sophisticated design of the interleaver block. An HSDPA compliant turbo decoder has been optimized at algorithmic, architectural and gate levels to overcome speed bottlenecks while being frugal in the use of silicon area and power. The chip has been implemented in 0.13 mm CMOS with a die size of 1.2 mm 2 and a power consumption of only 58 mw at the maximum throughput specified by HSDPA of 10.8 MBit/s. Diagram of SD based fractional-n frequency synthesizer for multi-mode RF transceivers Chip photograph of the HSDPA turbo decoder ASIC with a die size of 1.2 mm 2. 50

53 DC-DC Converters for Systems on Chip Thomas Christen, Thomas Burger ETH Zürich ACP AG For battery operated devices such as mobiles phones the operating time is a critical factor for sales as well as user satisfaction. The battery voltage of these devices is usually not compliant to the preferred supply voltage for the ICs it is built of. For instance, the popular lithium-ion battery used in mobile phones provides a voltage between 3 and 4.2 V depending on the amount of charge stored. On the other side the core supply voltage of circuits implemented in deep sub-micron CMOS technologies with feature sizes of 130 nm and below is 1.2 V or lower. To adapt battery to chip voltage a regulator has to be inserted. So far, this function has usually been implemented on a separate power management IC. Integrating the voltage regulation on the target IC on the other hand reduces the number of different supply voltages for the latter. There are two popular ways to achieve the voltage conversion. The first is linear voltage regulation and the second is switched DC-DC voltage conversion. The first is more amenable to integration and does not create spectral distortions beside noise whereas switched DC-DC conversion can reach a power conversion efficiency above 90% which is far more than the one of linear regulation. In this research the usage of switched DC-DC conversion is investigated with respect to integration into transceiver circuits. Special emphasis is put on the reduction of distortions on the regulated supply voltage because such distortion will propagate to the RF over sensitive circuits as VCOs, mixers and LNAs. Start up behavior on an implemented DCDC-converter for SoC. Output switching waveform (yellow) and filtered output signal (light blue) 51

54 Research Projects Technology CAD Coordinators: Wolfgang Fichtner Andreas Schenk Dölf Aemmer 52

55 GIDL Suppression by Optimization of Junction Profiles in the 22 nm Technology Node Simulation of Phonon Scattering in Silicon Nanowires Andreas Schenk Martin Frey EU-IST PULLNANO EU-IST NANOSIL PULLNANO Consortium NANOSIL Consortium References: [T8] Task Tunnel Leakage Currents of the PULLNANO project aimed at the simulation of gate-induced drain leakage (GIDL) caused by band-to-band (B2B) tunneling and possible ways of its suppression by moderate changes of the doping profiles and the geometry. The template device of the 22nm technology nodes with SiOx/HfO2 stacks, as it had been defined in the PULLNANO work programme, were used for this purpose. As GIDL suppression always goes at the cost of a reduced on-current, attention was also paid to the behavior of the on-current. Variations which lead to the best compromise were highlighted. The analysis was based on the drift-diffusion transport model and the non-local B2B model ( Schenk model ) in Sentaurus Device (Synopsys). It was found that the as-defined template transistor fails to reach the ITRS off-current specification (10 pa/μm) by ~ 2-3 orders of magnitude. The following variations were studied: plateau, steepness, and lateral position of the source/drain (S/D) profiles, Si body thickness, and HfO2 layer thickness. The obtained results suggest the position of the lateral doping profile to be the decisive factor (see figure below). In order to capture the physical effects relevant for nanoscale metal-oxide-semiconductor field effect transistors (MOSFET), electronic transport through these devices should be described at the level of quantum mechanics (QM). The nonequilibrium Green s function (NEGF) formalism provides a framework to include different scattering mechanisms, such as electron-phonon scattering or impurity scattering on a perturbative approach. Since both electrons and phonons are described by wave functions, scattering in QM is a spatially correlated phenomenon. However, in order to decrease the computational burden, approximations can be made such that scattering becomes local in space. The influence of both intravalley and intervalley phonon scattering on transport through silicon nanowires has been studied using deformation potential theory and the self-consistent Born approximation. The electron-phonon scattering leads to a broadening of the density of states, a destruction of phase coherence and a non-constant spectral current, as shown below. Top: Localization of the B2B rate in the 22nm template FET in the off-state. Bottom: Transfer characteristics at VDS = 1 V for shifted lateral doping profiles, i.e. changed doping peak alignment relative to the gate corners. The spectral current of a triple gate silicon nanowire FET: channel length = 30 nm, gate length = 10 nm. In the gate region, spectral current crowding is observed as the allowed states are diminished. 53

56 Limitations of the Effective Mass Approximation: A Specific Example A Nonparabolicity Model compared to Tight-Binding Aniello Esposito Aniello Esposito; Uni Purdue: Mathieu Luisier NEQUATTRO SNF , PULLNANO EU-IST PULLNANO Consortium References: Schweizer Numerik Kolloquium 2008 A Schrödinger problem consisting of an optical lattice embedded in a confining external potential is solved by means of exact diagonalization and the result is compared to the one obtained via the effective mass approximation (EMA). This simple framework is used in order to probe the suitability of the EMA which became a popular tool for the quantum mechanical treatment of charge transport in nanodevices. The optical lattice parameters are adjusted in order to best mimic the environment generated by a typical semiconductor material such as silicon or gallium arsenide. Although the direct atomistic treatment of such a semiconductor would be more rigorous one can still expect satisfactory qualitative as well as quantitative insights from the much simpler optical lattice model. The Schrödinger equation is expressed within a planar wave basis yielding dense matrices of sizes up to ~100,000 degrees of freedom. While decreasing the width of the external potential from ~5 nm to ~1 nm the ground state energy obtained via the EMA and the exact method are compared and summarized in the figure below. In addition, three snapshots are plotted which illustrate the external potential at widths of ~5 nm, ~2.5 nm, and ~1 nm. The EMA increasingly overestimates the ground state energy thus emphasizing the need for more accurate approximations in such strongly confined systems. The algebraic problems are solved by means of ScaLAPACK as well as via a highly efficient tailor-made algorithm for groundstate searches. NEQUATTRO SNF , PULLNANO EU-IST PULLNANO Consortium References: Solid Some Electronics (SQWT) 53,3, p , 2009 In this project a nonparabolicity model (NP) is introduced which is able to improve the effective mass approximation (EMA) for computing transfer characteristics of square silicon quantum wire transistors (SQWT) working in the ballistic regime and subjected to bandstructure effects. The model is found to be treatable within the same transport framework as used in a present 3D EMA Poisson- Schrödinger solver thus keeping a comparable time efficiency. A full-band tight-binding (TB) code provides the bandstructures as well as the transfer characteristics related to a series of SQWTs needed for calibrating the NP model. In comparison with the EMA, the threshold voltage obtained via the NP model is notably closer to the TB data for all wire widths considered in this work. In addition, the NP model is found to satisfactorily predict the increase of the conduction masses belonging to the unprimed conduction valleys of the TB bandstructure. The investigation of the on-current behavior and velocity profiles is temporarily avoided as it requires well converged data up to notable gate voltages. This task is still ongoing and it is expected to be manageable via a suitable extrapolation scheme for the current characteristics. In conclusion, the main bandstructure effect leading to the shift of the threshold voltage is given by the overestimation of the conduction band edge caused by the EMA. This result may vary in the case of smaller gate lengths where tunneling becomes more relevant. The same investigation can now be extended to quantum wells. Ground state energy as a function of the external potential width D. The energy overestimation which is typical for the EMA considerably influences the calculation of interesting observables such as currents through nanodevices. Threshold voltages as a function of the wire width D. The EMA and nonparabolic outcomes are compared to the tightbinding case. In particlular, squares and diamonds are for different conduction masses. 54

57 Ab-initio Calculations of Indium Clustering in Silicon Ab-initio Calculations of N-Type Dopant Clustering in Silicon Beat Sahli, Kilian Vollenweider Beat Sahli, Kilian Vollenweider KTI NMPP ATOMDIFF, Synopsys Synopsys, Pilot Users: AMAT, Fujitsu, NEC, Samsung, STM, VSEA References: [T13] [T14] KTI NMPP ATOMDIFF, Synopsys Synopsys, Pilot Users: AMAT, Fujitsu, NEC, Samsung, STM, VSEA Indium is an important p-type dopant for advanced MOS- FET devices. The understanding of indium clustering in silicon on the atomic level is of great interest. However, it is currently not possible to determine the relevant defect properties by experiment. We calculated the formation and binding energies of a wide range of indium clusters in silicon from first principles. The density functional theory calculations were performed with the Vienna Ab-initio Simulation Package (VASP). All relevant charge states of all clusters were considered. For each cluster species, several initial configurations were relaxed with the conjugate gradient algorithm. The formation energies were calculated with respect to isolated substitutional dopant atoms. In total, 1,143 individual simulations were performed. Setting up, running and analyzing such a large number of simulations was made possible by a software framework developed for the ATOMDIFF project. The calculated formation energies will be used to implement an advanced kinetic Monte Carlo model of indium clustering. The ab-initio results serve as a physically sound starting point for the calibration with a large database of experimental results. Phosphorus, arsenic and antimony are three important n-type dopants for silicon technologies. They differ in characteristics relevant for semiconductor technology, for example the diffusion coefficient, the solid solubility, or their behavior in ion implantation. Selecting the optimal dopant for a specific application is a complex problem, depending on several factors. For example, antimony has recently gained special attention because of its advantageous behavior in strained silicon. The ever increasing requirements for semiconductor technology even call for solutions with several n-type dopant species in the same region of the device, cleverly combining the respective advantages and disadvantages of the individual dopant species. Therefore, comprehensive diffusion and clustering models must also properly include mixed clusters. The formation and binding energies of 70 clusters containing phosphorus, arsenic and antimony, including mixed clusters have been calculated. Several charge states were considered. The Vienna Ab-initio Simulation Package (VASP) was used for the density functional theory calculations. Including a wide range of different cluster types made it possible to investigate the systematic differences and similarities in the clustering behavior of the three dopant species. The dependence of the formation and binding energies on the cluster constituents revealed clear trends. The ab-initio results will be used as a basis for the development of a kinetic Monte Carlo model for the detailed dynamic simulation of the clustering processes in semiconductor device manufacturing. Formation energies of different indium cluster species in silicon. The formation energies of the vacancy and the selfinterstitial are also shown. Four examples from the P-As-Sb cluster family. From top left to bottom right: AsI, SbI, PAsI, Sb 3 I. The silicon atoms are shown in blue, phosphorus atoms in red, arsenic atoms in green and antimony atoms in magenta. 55

58 Ab-initio Calculations of Formation Energies for Fluorine Clusters in Silicon Molecular Dynamics Simulations of Diffusion of Fluorine in Silicon Kilian Vollenweider, Beat Sahli Kilian Vollenweider, Beat Sahli KTI NMPP-NM ATOMDIFF, Synopsys KTI NMPP-NM ATOMDIFF, Synopsys Synopsys Pilot Users: AMAT, Fujitsu, NEC, Samsung, STM, VSEA Synopsys Pilot Users: AMAT, Fujitsu, NEC, Samsung, STM, VSEA A broad range of fluorine clusters in silicon has been investigated, using the Vienna Ab-initio Simulation Package (VASP). In order to get a detailed understanding on cluster formation, the formation energies have been calculated for the minimal energy configurations, using the following equation: E f (X)=E tot (X)-S i n i m i E tot (X) is the total energy of the supercell containing the defect X, n i is the number of atoms of type i in the supercell and m i is the reference energy. The results for the formation energies are shown in the figure. Clusters including the same number of vacancies are grouped together and are indicated by the same color. The systematic construction of the clusters is reflected in the formation energies. For all groups the formation energy decreases linearly by increasing the number of fluorine atoms. In order to investigate diffusion of implanted fluorine we focused on the mobile defects FV, F, FI and FI 2. For all of these defects molecular dynamics (MD) simulations were performed in order to find diffusion mechanisms. The MD simulations are done with the Vienna Ab-initio Simulation Package (VASP) in a supercell of the size of 64 atoms at a temperature of 1000 C and an atomic time step of 1 fs. The simulation times varied between 60 ps and 200 ps. All defects are supposed to be negatively, neutral or positively charged. Diffusion events have been found for the negatively charged FI and for FI 2 in all charge states. In the following, the diffusion event of FI is discussed. In the minimal energy configuration the F atom is in a bond centered position. For the neutral and positively charged cases it stays in this configuration during the whole simulation time, rotating around the bond. The negatively charged F shows two diffusion events where the fluorine atom jumps into a neighboring bond centered position. The diffusion mechanism of FI: The different steps of the event are chronologically colored from green to blue. The fluorine atom is drawn with a smaller radius than the silicon atoms. 56

59 Kinetic Monte Carlo Model for Fluorine Diffusion and Clustering Kilian Vollenweider, Beat Sahli KTI NMPP-NM ATOMDIFF, Synopsys Synopsys Pilot Users: AMAT, Fujitsu, NEC, Samsung, STM, VSEA Systematic ab-initio calculations of fluorine diffusion and clustering in silicon have been performed. The calculated formation energies and migration energies were used to implement a new kinetic Monte Carlo (KMC) model. The findings of the ab initio study were directly transferred to a KMC process simulator to model implantation, diffusion and clustering of fluorine in consideration of amorphization and recrystallization, extended defect evolution and surface segregation. The model was calibrated and compared to Secondary Ion Mass Spectroscopy (SIMS) data, including ultra-shallow junctions for advanced silicon devices. The populations of the most important defects considered in the KMC simulation are shown in the figure below. After implantation there is no dominant defect. However, after spike anneal only F 2 I and F remain. Top: Defect populations after implantation and spike anneal. Bottom: Fluorine profiles with (SIMS) from [M. Diebel et al., Mater. Res. Soc. Symp. Proc. Vol 765 (2003)] for 20 kev 3*10 15 cm -2 implant followed by 1050 C spike anneal. 57

60 Research Projects Computational Optoelectronics Coordinators: Bernd Witzigmann Wolfgang Fichtner 58

61 40 Gbit/s-Capabilities of Directly Modulated VCSELs AQUA: Electroluminescence in Nanostructures Alexandra Bäcker Sebastian Steiger, Ratko Veprek NCCR-Quantum Photonics SNF GAIN Bookham References: [O12] Vertical-cavity surface-emitting lasers (VCSELs) have become an attractive light source in fields such as fiber-optic data links, computer mice, or laser printers. One major design issue - for a variety of communications applications - is the high-speed modulation capability of VCSELs, where data rates beyond 40 Gbit/s are desirable. In the scope of this project, the high-speed modulation potential of VCSELs under direct modulation is explored. Starting from the electro-opto-thermal calibration of a state-of-the-art 10 Gbit/s VCSEL, which is performed with the commercial device simulator Synopsys Sentaurus Device, the device is analyzed with respect to its bandwidth-limiting elements. The modulation response is very sensitive to carrier dynamics. Hence, an important factor in this analysis is the differential gain with respect to electrons and holes which is extracted from material gain simulations. In a next step, adaptations to the current VCSEL design will be investigated, which also include the exploration of new cavity designs such as a double active region or an integrated electro-absorption modulator marked the completion of the novel device simulator AQUA capable of modeling electroluminescence in quantum wells and wires on a microscopic basis. The physical picture behind AQUA relies on a fundamental partitioning of carriers into populations bound to a low-dimensional active region and unbound populations. Bound carriers are described by coherent k p states in the quantized directions whereas drift-diffusion transport occurs in the remaining directions. The third year of development was mainly devoted to feature completion, reliability and handling improvements, and most of all testing and validation against real-world structures. New physical models include the capability of simulating strained and piezoelectric structures, doping- and temperature-dependent mobility and recombination parameters, nitride material files, bowing of selected alloy parameters and incomplete dopant ionization. Furthermore, a selection of different linear solvers and input/output formats is now supported. AQUA was compared to several real-world structures, most notably the quantum-wire light-emitting diode given in Weman et al., APL 73, 2959 (1998). By fitting the capture times, agreement between experiment and simulation was achieved. The simulation was supporting the suggested operating mode in which carriers get channeled through the vertical quantum-well, leading to efficient injection into the wire and high internal quantum efficiencies. Top: measurement and simulation of material gain for different carrier densities at room temperature. Bottom: differential gain with respect to electrons and holes, calculated from the simulated material gain above. Top: Sketch of the simulated structure. Bottom left: simulated spectra of the combined QWR-QW system. Bottom right: Comparison of simulated turn-on voltages to experiment. 59

62 Quantum Transport for Optoelectronics using NEGF Comparison of Electroluminescence in Nanostructures of Different Dimensionalities Sebastian Steiger Sebastian Steiger, Ratko Veprek SNF GAIN SNF GAIN References: Proc. IWCE 2009 In spite of the successes of semiclassical simulators such as Sentaurus Device (Synopsys), APSYS or AQUA in simulating the emission of quantum-well (QW) LEDs, a conceptual flaw remains: the artificial restriction of the carrier system to a physical picture of either complete coherence or de-coherence. The use of Nonequilibrium Green s Functions (NEGF) eliminates this obstacle. NEGF is a full quantum formalism for nonequilibrium particle systems which accomodates scattering on a natural and conceptually clear basis. In particular, the carrier distribution is energy-resolved and carrier capture into the QW does not rely on any ad hoc model assumptions. NEGF was applied to an 8 nm GaAs QW embedded in an Al 0.3 GaAs p-i-n barrier. POP and acoustic phonon scattering were implemented as well as two phenomenological scattering models. Furthermore, scattering with an empty multi-mode free-space photon field was included to obtain luminescence. The code was MPI-parallelized to meet the enormous CPU and memory requirements. Results show qualitative agreement with the semiclassical simulator AQUA; however, the phonon-mediated carrier capture is now revealed. Luminescence spectra are broader than in AQUA due to the employed two-band effective mass band structure. References: Proc. SPIE of OPTO 2009 Conference This project employed the semiclassical simulator AQUA to investigate the effect of quantization on the internal quantum efficiency (IQE) and total output power of nanostructured LEDs. AQUA previously successfully modeled the carrier channeling and electroluminescence of the quantum-wire LED described in Weman et al., APL 73, 2959 (1998). Good agreement was found between experiment and simulation. The analysis was then extended to two other devices containing the same materials and doping profiles. However, the region of quantization differs in that it is either a quantum-well or not quantized at all. Hence the active region exhibits either a 3D, 2D or 1D density of states. Comparing the three devices, it is observed that the IQE increases dramatically with increasing quantization. However, the calculated radiative coefficient (B-coefficient) is roughly the same in all three devices. This suggests that the improved efficiency mainly stems from higher carrier densities in the active region. For the quantized structures, the IQE increases initially with the applied voltage until it reaches a maximum. Beyond this point state filling of the quantized region gives rise to carrier leakage, and Auger processes become relevant. The inferior density of states also limits the maximum possible output power in the QW and QWR cases. Thus higher quantization must be accompanied by stacks of quantum regions or larger active regions to achieve the same output as in the bulk case. For the present design of the QWR LED however, such a task does not seem feasible. Top: Spectrally resolved electron and hole density at 1.55 V. Bottom: NEGF luminescence spectra (solid) compared to AQUA results (dashed). Legend: output power in [W/cm -2 ]. Simulated internal quantum efficiencies of three similar structures exhibiting different degrees of quantization. The IQE increases dramatically with quantization. 60

63 Polarization Effects in III-Nitride Structures Strain-Engineering in InGaN/GaN Nanocolumn LEDs Ratko Veprek, Sebastian Steiger Ratko Veprek, Sebastian Steiger SNF GAIN SNF GAIN References: [O13] Light-emitting diodes (LEDs) based on III-nitride semiconductors are the most promising candidates for the realization of next generation light sources. By combining AlN, GaN and InN, optoelectronic devices can theoretically be fabricated to operate at ultraviolet to infrared wavelengths. Common devices based on III-nitrides are grown on the polar faces of the crystal, leading to strong piezo-electric fields within the active region. Such piezo-electric fields tend to separate the electron and hole population within the active region, severely lowering the transition probability. Consequently, the device efficiency is severely lowered. Further, due to the quantum confined Stark effect, a carrier density dependent blue-shift within the spectra can be observed. The computational modeling of such structures may provide answers on how optimal designs may lower the effect of the polarization-induced electric fields. Therefore, the developed nanostructure simulator AQUA/tdkp has been extended to include polarization effects of nanostructures of different dimensionality in arbitrary crystal directions. Conventional LED technology uses broad area epitaxial growth which has limitations in terms of substrate choice and multi-color capability. Nanocolumn LEDs have been proposed as an alternative, as their growth is nearly dislocation free on a wide range of substrates, leading to high quality crystals perfectly suitable for efficient devices. Due to the large lattice-mismatch between InN and GaN, highly compressive strains within active InGaN layers lead to undesired blue-shifts in the emission spectra. Further, the increase of indium content within the active layer is still technologically challenging. Consequently, the fabrication of red emitting diodes using III-nitrides is still an open issue. Here, nanocolumn LEDs may serve as an alternative, as their finite lateral size allows intrinsic strains to relax, shifting the emission spectra to the red. In the project, the lateral relaxation of the strain of three dimensional nanocolumns and its effect on the band gap and on the built-in fields have been analyzed. The calculations have been performed using the inhouse developed simulation tool AQUA/tdkp, based on continuummechanics. As a result, a strong relaxation of the strain towards the surface and the formation of tensile strains has been found. The strains lower the transition energy up to 500 mev. The strain relaxation has been proposed as an explanation of the red emission found in such devices. Polarization field of a 3D GaN-nanocolumn. Due to the finite size, lateral relaxation of intrinsic strains leads to nonuniform polarization charges and thereby causes nonuniform electric fields. Bulk bandgap of a horizontal cut through the In 0.4 Ga 0.6 N active layer embedded in a GaN nanocolumn of 50 nm diameter. The color represents the emission color. The relaxation towards the surface lowers the band gap by 500 mev. 61

64 Ellipticity and Operator Ordering in k p Calculations of III-Nitride Semiconductors High Field Carrier Transport in III-V Heterolayer Structures Ratko Veprek, Sebastian Steiger Denis Doglos, Hektor Meier SNF GAIN KTI PFNM PONDETECT, Enablence (former Albis OptoElectronics) Enablence (former Albis OptoElectronics) References: [O11] The modeling of optical properties of semiconductor nanostructures is commonly based on electronic states obtained using multiband k p envelope function methods. Such an approach is implemented within the developed simulator AQUA/tdkp for nanostructures of any dimensionality. Although the multiband k p envelope equations are often applied, the method is puzzled by the appearance of unphysical, spurious solution. It has recently been shown that the elliptic formulation of the envelope equations is crucial in order to obtain stable and spurious solution free band structures. In zinc-blende structures, elliptic equations are usually obtained by using the Burt-Foreman (BF) operator ordering. For wurtzite crystals, the issue of operator ordering has been discussed less frequently, as for common material systems, spurious solutions have not been reported so far. In the wurtzite crystal, the correct operator ordering cannot be estimated from bulk measurements. Therefore the developed theory has been applied to wurtzite models. It has been found that the usually applied symmetric operator ordering causes spurious solutions for certain material combinations. The ellipticity analysis suggests a stable, asymmetric operator ordering, which is motivated both, mathematically and physically. The simulation of carrier transport in modern semiconductor devices operating at far non-equilibrium conditions requires the solution of the semi-classical Boltzmann transport equation (BTE). A method to solve the steady-state BTE is the scattering matrix (SM) approach. Transport is viewed as a scattering problem that relates incoming and outgoing spectral fluxes on finite slabs of a semiconductor material. Within this project a hybrid simulator is being developed. First, the SMs of thin layers are computed using a Monte Carlo (MC) procedure. In a second step, during device simulation, the SMs are loaded from a library and are combined to a device SM. The Poisson equation is solved self-consistently in an iteration loop. This approach allows the deterministic evaluation of the spatially resolved distribution function in complex heterostructure devices. The computation time is considerably reduced compared to full-device MC simulations due to piecewise integration of the BTE. In future, the high-field transport of carriers will be modeled using ab-initio band structures and non-local impact ionization will be added. Probability distribution of top valence band state in a 1.8 nm 2. GaN quantum wire in Al 0.7 Ga 0.3 N, calculated using k p 6x6. The figure a) is obtained using the BF ordering and b) using the symmetric ordering. b) is clearly a spurious solution. Top: SM with sub-matrices t+, r-, r+, t- for a 100 nm slab,100 modes and an electric field strength E z =-10 5 V/m. Bottom: Positive distribution function for electrons travelling with k z >0 for a bulk simulation within a simple semiconductor model including acoustic and optical photon scattering. 62

65 Characterization, Simulation and Analysis of Avalanche Photodiodes Combined Analytical-FDTD Simulation of Mode-Locked VECSELs Hektor Meier Philipp Kreuter KTI PFNM PONDETECT, Enablence (former Albis OptoElectronics) ETHZ TH-46/05-2 E-VECSEL Enablence (former Albis OptoElectronics) IQE-ETHZ References: [O7] Modern avalanche photodiodes (APDs) can be found as part of optical receiver circuits in fiber optical networks, such as fiber-to-the-home (FTTH) passive optical networks (PON). APDs are operated close to their breakdown voltage and provide signal gain due to avalanche multiplication. State-of-the-art APDs have been characterized in the Optolab. This includes among others the dark- and photocurrent characteristics and the gain-dependent frequency response for various temperatures. This measurements provide accurate input parameters for the simulation tools, assure the reliability of the analysis and allow for predictive design improvements. Monte Carlo simulations can accurately describe non-local impact ionization and non-equilibrium transport which are performance critical physical effects. However, the computation time of such solution methods is high. Intermediate transport models such as drift-diffusion and energy balance are favorable for rapid device development and evaluation. Time domain simulations of the optical impulse response allow to analyse the dynamic behaviour of seperated absorption, charge and multiplication (SACM) APDs. Performance bottlenecks can be identified by observing the electron and hole currents within the the device. References: [O3] Vertical External-Cavity Surface Emitting Lasers (VEC- SELs) have been studied intensively in the past decade. For the generation of ultrashort pulses VECSELs are passively mode locked with a semiconductor saturable absorber mirror (SESAM). For the simulation of such highly dynamic and nonlinear structures time domain models are commonly chosen. The applied full wave model is based on Maxwell s equations which are reduced to 1D under the assumption of linear polarization and TEM 00 transverse mode operation. The material response in the gain medium and the absorber is treated by a resonant, carrier dependent polarization term, which is included using an IIR digital filter fit to susceptibility data obtained from a microscopic gain model. This set of equations is coupled to carrier rate equations in each quantum well. In order to reduce computational complexity compared to standard FDTD schemes, analytical wave propagation in the external cavity is coupled with an FDTD scheme in the gain and absorber mirrors. Furthermore, FDTD updating in the mirrors is deferred during pulse propagation in the external cavity. This allows for the simulation of large cavity mode-locked laser devices. Electron and hole current densities as response to an optical pulse. Bandwidth limitations of SACM APDs are the transit time of the carriers and the avalanche multiplication process. Top: Output pulse train of a passively mode-locked VECSEL. Bottom: Time evolution of the optical intensity compared to a hyperbolic secant pulse. 63

66 Design of Electrically Pumped VEC- SELs Optimization of the Electromagnetic Properties of 3rd Generation Nanowire Solar Cells Philipp Kreuter; IQE-ETHZ: Yohan Barbarin, Ursula Keller Jan Kupec ETHZ TH-46/05-2 E-VECSEL ETHZ References: [O4] IQE-ETHZ Uni Lund, FhG ISE, Sol Voltaics, TU Denmark, Uni Linz Vertical External-Cavity Surface Emitting Lasers (VEC- SELs) allow for a near diffraction limited output beam in conjunction with a scalable output power. Passive mode locking of VECSELs can be achieved with a semiconductor saturable absorber mirror (SESAM). Besides the vertical integration of the absorber into one monolithic structure with the gain quantum wells, electrical pumping is essential for the waferscale fabrication of compact ultrafast VECSEL structures. This is quite demanding because of Joule heating and optical losses in the doped layers. In this project, several designs of electrically pumped VECSELs (EP-VECSELs), which are compatible with passive mode locking, are investigated using microscopic simulation. We focus on the achievement of a good confinement of the carriers in the device center for fundamental transverse mode operation. Scalability of the carrier confinement is important to exploit the potential for power scaling of VECSELS. Furthermore, the design should yield a high outcoupling efficiency and a broad spectral range for mode locking and excessive heating in the distributed Bragg reflectors (DBRs) has to be avoided. Since the optical and electrical optimization are partially competing, a tradeoff has to be found. Simulations show that a p-doped bottom mirror is necessary to provide fundamental transverse mode operation in large-area VEC- SELs. A structured bottom contact in conjunction with a bottom p-dbr even showed to outperform oxide barriers and tunnel junctions in terms of carrier confinement. Photovoltaic power generation is increasingly attracting attention as an alternative source of energy. However, its cost is still too high compared to power generated by conventional means. Since the invention of the solar cell in 1954 the cost has been reduced by a factor of 1,000. A further reduction by the factor of 10 is necessary to achieve cost equal to fossil or nuclear power. The present projects focuses on concentrator photovoltaic devices based on an array of heterojunction nanowires. This concept allows both, optimal tuning of the bandgaps of the heterostructure and minimum amount of semiconductor material due to local concentration of light. In order to design efficient light absorption of these third generation solar cells, electromagnetic modeling has to be performed. Using the finite element method, the dispersion characteristics for both in-plane and perpendicular wave propagation were analyzed. It was shown that even though the nanowires are short compared to the wavelength, light is propagating in distinct modes and the incident power has to be coupled into those with maximum absorption. Carrier density distribution along the radial axis in the active region for various cap layer thicknesses and doping levels (in cm -3 ). The VECSEL exhibits an aperture radius of 50 micrometers and a bottom contact radius of 25 micrometers. Power flux of the incident light in a unit cell of the nanowire array. The dielectric contrast of the structure causes a local concentration of the optical power resulting in a higher effective fill factor of the structure. 64

67 Research Projects Physical Characterization Coordinators: Wolfgang Fichtner Mauro Ciappa Dölf Aemmer 65

68 Reconstruction of Scanning Electron Microscopy SEM Images by Monte Carlo Simulation Digital Processing of SEM Images for Line Width Measurements with Sub- Nanometer Uncertainty Alexander Koschik, Stefan Holzer, Mauro Ciappa Stefan Holzer, Alexander Koschik, Mauro Ciappa ETHZ ETHZ References: [P10] SEM metrology is a mature and robust tool for non-destructive quality control, in particular for critical dimension (CD) measurement in semiconductor technology. Due to the finite size of the interaction zone of the probing electrons in the sample, resolution of SEM images decreases with decreasing structure size, aggravating edge extraction in typical line scans for CD measurement. In the 32 nm node and beyond, the tight uncertainty requirements for CD measurement can not be met with present techniques. A SEM image is primarily formed by detection of the local secondary electron (SE) emission yield, which is among other a function of primary electron energy, local and proximate material properties, as well as local and proximate surface topology. Furthermore, charging of dielectric layers (e.g. resist layer) can deflect the primary beam, as well as the emitted secondary electrons, and additionally alter the SE yield. The challenge of this project is to extract the surface topography from SEM images distorted by these effects. The proposed technique is based on Monte Carlo (MC) simulation of the image formation process. The prediction capabilities of the developed tools are improved by the implementation of the most recent models for the low-energy scattering processes to allow for accurate treatment of SE generation and to include the charging effects. The most recent CMOS technology nodes have reached critical dimensions below 32 nanometers. Further downscaling and process control require line width metrology tools with uncertainty in the sub-nanometer range. Digital processing techniques, including filtering and convolutional approaches, are used within this project to solve the inverse modeling problem, in order to extract as accurately as possible the underlying geometry from scanning electron microscopy (SEM) images. The typical input information consists of secondary electron top-side images either of photoresist lines, or of vias through thick oxide layers. Critical dimensions are extracted with the required accuracy by inverse modeling of the SEM image formation process. The input signal (a typical input signal is shown below) is preprocessed by appropriate filtering and convolutional techniques to gain additional information, which is then used for the actual inverse modeling task in order to improve accuracy and convergence speed of the geometry extraction. Top: MC simulation of electron trajectories in SiO 2 lines on Si substrate. (white: incident e beam, red: secondary & backscattered e, blue/green: primary e in SiO 2 /Si). Bottom: Corresponding simulated SE signal. Input signal showing a scan of three parallel lines, where the peaks of the signal correlate with the edges of the lines and the level of background signal reflects secondary electron yield of the substrate. 66

69 Correction of Proximity Effects in Electron Beam Lithography Applications for 32 nm Structures and below Monte Carlo Simulation of Electron Beam Cross-Linking Processes for Polymers Alexander Koschik, Mauro Ciappa; Synopsys: Lars Bomholt Luigi Mangiacapra, Mauro Ciappa; HUBER+SUHNER: Maria Stangoni, Stephan Ott Synopsys KTI PFIW-IW, HUBER+SUHNER Synopsys HUBER+SUHNER E-Beam Lithography (EBL) is a prospective candidate for future integrated circuit production nodes (32nm and beyond), since optical lithography defers its physical limits at ever exceeding costs. In optical lithography, diffraction from nearby features jams the mapping of the IC layout to the photoresist layer. This is called proximity effect. In EBL, electron scattering in resist and substrate produces proximity effects, which lead to undesired interactions with the adjacent regions. The Point Spread Function (PSF) is the simplest computational approach used to describe the dose deposition in the target by a single impinging electron. Corrections are employed in order to map the desired layout onto the wafer. While Optical Proximity Correction (OPC) strategies in photo-lithography uses geometrical modifications of the layout to be exposed, E-Beam Proximity Correction (EBPC) is based on local dose modulation. The challenge in this case is to solve this inverse problem of dosimetry. At present, direct solution by fast deconvolution exists under the restriction that the PSF has rotational symmetry and does not depend on the depth in the photoresist layer. With regard to shrinking dimensions (where the e-beam probes the underlying structure) and lower accelerating voltages of 5 kv (PSF depth variation in resist layer), these assumptions might not hold any more. The scope of this study is to assess the necessity to include such 2D/3D effects in the PSF and investigate appropriate deconvolution methods. In high technology connectivity solutions for transportation, solar, and communication applications, electron beam irradiation of electrical cables, wires, and optical fibers is an established technology deployed to cross-link polymeric materials used as isolators to provide improved mechanical, chemical, and thermal properties, as well as a very low environmental impact, due to the avoidance of additional chemical processes. The most recent production strategies require a rigorous cost discipline and optimized production flows. Nevertheless, procedures and protocols used nowadays for the definition of the processing parameters still present relevant space for improvements and innovation. This project aims to introduce predictive physical modeling of the electron beam cross-linking process to achieve higher throughput, faster design cycles, shorter processing times, faster transfer among different accelerators, suppression of detrimental effects, and more efficient use of raw materials. In a first phase, quantitative Monte Carlo simulation has been applied to calculate the dose in dedicated test structures used to calibrate the process flow. Preliminary investigations have demonstrated the relevance of the irradiatiation setup, which strongly impacts the yield of the backscattered electrons and as a consequence the dose deposited in the polymer sample. Monte Carlo simulation of electron trajectories at the boundary of silicon (left) and polymethylmethacrylat (PMMA) (right) substrates with a primary incident electron beam of 5 kev (top center). (Red: backscattered e, Blue and Green: primary e ) Quantitative calculation of the effect of the target substrate material on the dose deposited in a polyethylene strip. Monte Carlo simulation has been performed by two different codes MC1 and MC2 for an electron beam energy of 1 MeV. 67

70 New Strategy for the On-Chip Screening of Gate Oxide Defects in Smart Power Devices New Strategy for On-Chip Screening of Leakage Currents in LDMOS Transistors for Smart Power Devices Vezio Malandruccolo, Mauro Ciappa; Infineon: Hubert Rothleitner Vezio Malandruccolo, Mauro Ciappa; Infineon: Hubert Rothleitner Infineon Infineon Infineon Infineon The ability to control the random defectivity of a product during its life cycle becomes more and more vital, especially in the automotive field, where the drive towards zero-defects is very stringent. In fact, due to the large number and critical functions of integrated devices in a car, random failures occurring in the field may have immediate disastrous consequences for the device manufacturer, which could be faced among other with safety issues for the car passengers, as well as expensive call back actions of the unreliable parts. In particular, gate oxide defects are a major constraint in the development of reliable automotive devices because of the extensive use of large gate areas for the power devices. In this respect, the analysis of a typical process flow shows that the occurrence probability of gate oxide defects is relevant compared to the total amount of defects that can be introduced during the whole production phase. This project aims at solving the limitations of the traditional screening procedures (e.g. burn in). Therefore, a new approach to the screening of defective gate oxides of Lateral Diffused MOS transistors (LDMOS) is developed, which is based on a dedicated embedded circuitry to perform on chip the gate stress and the measurement of the leakage current through the stressed gate oxide. Since the whole process is managed by an internal digital circuitry, this new built-in reliability test methodology does not require any additional testing equipment and can be run in parallel on a very large number of devices. Crystal defects as dislocations and stacking faults can be either inherently present in the bulk silicon, or generated during some critical process steps like epitaxial growth, implantation, and the formation of shallow trench isolations. During the lifetime of a device, crystal defects can coalesce or act as a gettering site for dopant atoms and contaminations. This can result into the formation of local highly conductive paths, which under some circumstances can heavily affect the performance of the integrated circuit. This is in particular the case of Laterally Diffused MOS transistors (LDMOS), where the presence of crystal defects in the active area can cause an increase in the source to drain leakage currents, or a significant reduction of the source to drain breakdown voltage. At present, the Drain Leakage Test is performed sequentially by means of expensive automatic test equipment direct pin access to the drain of power LDMOS. The proposed solution for a built in Drain Leakage Test (BI-DLT) makes use of the capabilities already offered by the circuit for the the built in Gate Oxide Stress. The realization of this additional test mode has been made possible by minor design changes, which have almost no impact on the required area overhead. Since the BI-DLT has been integrated in a process for temperatures up to 200 C, it is expected to reduce the cost and improve the efficiency when used conjunction with traditional burn-in screening under bias. Gate oxide area in a typical smart power IC for automotive applications (multiple low side power switch for motor management). Here, 65% of the chip area is occupied by the gate oxide of the LDMOS (green area), while the remaining 35% by the low voltage circuitry (grey area). Process-related crystal defects in the active area of an integrated circuit after delineation by the Wright etch. 68

71 Multiscale Simulation for the Design of Highly-Reliable MEMS Devices Design Methodology for CMOS and MEMS Toshiba: Hanuka Kubo, Takayuki Masunaga; Mauro Ciappa NTT: Norio Sato; Mauro Ciappa, Dölf Aemmer, Hubert Kaeslin Toshiba NTT Toshiba NTT In the design of advanced Micro-Electro-Mechanical systems (MEMS) and semiconductor devices, the relevance of structural problems such as the deformation by residual stresses, fracturing by thermal processes and long term deformation by creeping phenomena is increasing. Therefore, to ensure long term product reliability, quantitative and predictive structural simulations are needed, which are based on a robust and accurate modeling of the properties of the thin films materials used in manufacturing. The latter is not a trivial task to be solved, since in general thin films material properties are notably different from those of bulk materials. Furthermore, experimental characterization techniques for thin films are inherently more difficult, due to the reduced specimen size, load, and deformation range. This project aims to develop a multiscale simulation methodology to predict the mechanical behavior of macroscopic thin film structures from the morphology at microscopic scale. The main material parameters are derived from microscopic level models, which take into account among other effects like sliding and diffusion along grain boundaries, as well as plastic deformation within the grains. The homogenization method is then used to simulate macroscopic deformations with the final scope to define a builtin reliability strategy to predict accurately the long-term degradation of the devices, in order to conceive highlyreliable products. Various kinds of key components are available as Micro- Electro-Mechanical Systems (MEMS). This is the case of accelerometers in mobile terminals, micromirrors in portable beamers and pressure sensors in industrial control equipment. Such MEMS devices convert physical quantities into electrical quantities, and vice versa. Combination of this conversion ability of MEMS devices and signal processing ability of CMOS integrated circuits will add new/ high functionality to electronic systems. In order to conceive new components, a design methodology is necessary as well as technology development. This is because CMOS MEMS are made more complicated than just the separated elements due to the coupling of the CMOS circuits with the MEMS devices. Starting from a thorough literature survey, a preliminary design methodology for CMOS MEMS has been defined in this project, which bases on the digital CMOS design flow. A system specification is broken down into minute specifications to CMOS and MEMS elements. This also includes the development of compact models for the MEMS elements according to a well-defined hierarchy within the MEMS design scheme. Thus, three-dimensional structures are reduced down to simpler expressions described by characteristic parameters. Three-dimensional simulation model of a polycrystalline thin film consisting of sixty columnar grains (major side is 1 µm). Scheme for designing CMOS MEMS which consist of MEMS, CMOS analog and CMOS digital elements. 69

72 Weak Coupling of Electric and Thermal Equations for Multiscale Simulation of Electronic Devices Reliability of the Thermal Interfaces in Power Modules Mauro Ciappa Mauro Ciappa ETHZ ECPE ECPE Large-scale simulation of electronic systems requires more and more to take into consideration the temperature dependency of the semiconductor equations on the junction temperature. The dependency is particularly relevant in the case of power devices, where the coupling of electrical and thermal parameters can result into a positive feed-back that can turn into thermal runaway phenomena. The solution of such a problem presents some basic constraints. In fact, in most cases the temperaturedependent heat sources are extremely concentrated in small space regions, while the local temperature is defined by the heat transport over large distances. This situation requires to use multiscale simulations techniques. Different approaches have been used in the past based on lumped element, or on VHDL-AMS behavioral models. The main limitations of these methods are well-known. As an example, no efficient discretization tools and numerical solvers are available at present for VHDL-AMS, such that simulations have to relay on very rough simulation and material models, cumbersome mesh schemes, as well as on long computation times. In this project, the excellent modeling, meshing, numerical, and scripting capabilities of standard simulation tool as Ansys have been exploited to solve electro-thermal coupled problems at a multiscale level. As first attempt, the active devices have been subdivided in small one-dimensional domains, whose power dissipation depends on the instantaneous local temperature. This weak coupling delivers excellent results in terms of computation time, development time and realism of the simulation model, as well as of accuracy of the results. The main limitations are related to the partitioning of the heat sources in independent one-dimensional subdomains, which does not model in full detail phenomena, where lateral current spreading is expected. Multichip modules for high power devices are complex multilayered structures consisting of different materials, which have to provide a good mechanical stability, good electrical insulation properties, and good power dissipaton capabilities. Thermal interface materials are widely used to reduce thermal resistance between the baseplate of a device and the cooling surface. For power modules the baseplate is typically kept in direct contact with the heat sink to dissipate the heat. In order to reduce the thermal contact resistance between the baseplate and the heat sink, a layer of thermal grease is required to fill the gap between them. Power modules experience significant warpage due to the large coefficient-of-thermal-expansion mismatch between the different materials. Therefore, traditional thermal greases can be gradually squeezed out from between the baseplate and the heat sink, every time the dies are heated up and cooled down. Consequently, repeated power on/off cycles during operation, can result in thermal grease pump-out, which causes significant degradation in thermal performance over time. This project aims to develop a simulation methodology to predict the temperature distribution, the local values of the thermal resistance, the warpage of the different layers, as well as the grease pumping effect. Traditional multichip power modules, as well as new generation modules without baseplate are been considered. Temperature distribution in an IGBT module where the all direct copper bounded plates are delaminated along their periphery by 10 % of the total solder surface. Warping of a baseplate-less power module due to the simultaneous effect of the spring-loaded clamps and of the thermo-mechanical mismatch of the different materials caused by self-heating during operation. The maximum deformation (red area) reaches seven micrometers. 70

73 Online and Offline Isolated Current Monitoring of Parallel Switched High- Voltage Multi-Chip IGBT Lifetime Modeling and Prediction of Power Devices Mauro Ciappa, Alberto Castellazzi; HVL-ETHZ: Luca Dalessandro, Nico Karrer Mauro Ciappa ETHZ ETHZ HVL-ETHZ References: [P10] The feedback current control and the switching losses characterization of semiconductor devices are fundamental procedures for the safe and reliable operation of power converters and for assessing the efficiency and reliability of modules. In high power applications, online and offline characterizations are usually carried out by using shunts or conventional cored and coreless current transformers, respectively. Two main issues have to be carefully considered for the safe operation of power modules. The first one, which can result into an excessive power dissipation in one or more devices, is related to the onstate and dynamic loss unbalances that mainly depend on the statistical spread of the device parameters, differences in wiring inductance, and on the uneven temperature distribution. The second one is the thermal stability of the device, i.e. the susceptibility of the device to thermal runaway phenomena. In both cases, the parallel connection of multiple IGBTs can turn into an uneven distribution of the load and hence of the losses. This project was intended to apply planar PCB air-coil based sensors for online current monitoring and offline switching losses characterization in high-voltage, multichip IGBT modules. Two novel types of sensors have been shown, i.e. a planar PCB Rogowski coil, for measuring alternating currents, and a prototype of a HOKA current sensor, capable of broadband current measurement from DC up to 100 MHz without derating. References: [P6, P9] Accurate lifetime prediction based on realistic mission profiles represents a challenge for the design of complex devices and systems. This problem is usually tackled by proper analysis, by dedicated physical modeling, and by efficient calculation tools. In the last years, the need to increase the reliability of high-power multichip modules has been one of the most powerful drivers that forced engineers to design new products, especially intended for traction (railway and automotive), for power transmission, and for power distribution applications. In the case of railway and automotive traction, the main requirements imposed by the increasing complexity of the systems are weight and space reduction, as well devices operating at high temperature and at increasing voltages. This also applies to other application fields, where this trend is leading more and more to the deployment of advanced integrated technologies. At present, new approaches are applied, which are based on the knowledge of the root cause of the failure mechanisms and on the relationship among the product specifications, its constituting elements, the variations in the manufacturing process, as well as the interactions of product materials with the loads and their impact on the product reliability. The best practices that are presently in use are a systematic combination of physical models for the dominating failure mechanisms with the proper statistical and stochastic procedures. HOKA current probe (Hall sensor, Rogowski coil, and evaluation circuit) with a bandwidth from DC to 10 MHz and current rating up to 500 A. The sensors are directly mounted on the top of the IGBT modules. Comparison of the number of cycles to failure due to lowcycle fatigue in power modules as obtained by three-dimensional finite element simulation with two different materials models and by a simplified analytical model. The analytical model is sufficiently accurate to predict the lifetime of the device for the most traction applications. 71

74 Electro-thermal Simulation of Electron Devices by Behavioral Models in VHDL- AMS Full Electro-Thermal Model of a 6.5kV Field-Stop IGBT Module Alberto Castellazzi, Mauro Ciappa Alberto Castellazzi, Mauro Ciappa ETHZ EU-CT PORTES, ALSTOM ALSTOM References: [P4, P3] In this project, an original approach is presented, which combines the flexibility of the VHDL-AMS language to define compact behavioral models for the semiconductor devices with the distributed discrete three-dimensional model of the thermal problem. The proposed methodology is particularly interesting, since it enables to investigate a variety of operational conditions of the devices at reduced cost with sufficient insight and, once further developed, it could constitute a viable simulation platform for virtual analysis. Capabilities and limitations of this approach have been illustrated by two simplifiled examples dealing with the thermal instability of IGBT devices in blocking state and with the design of a temperature control loop in an integrated MOSFET power switch. These simple examples have demonstrated that the electro-thermal behavior of the device can be quantitatively captured, and the results easily visualized. In general, the proposed methodology can be applied to the analysis of those problems, which are not easily treated analytically and do not require a very refined discretization of the simulation model. In fact, the lack of a dedicated tool for the development and optimization of the simulation models can result in a poorly accurate geometry, as well in a long calculation time. References: [P8] IGBT modules are used in the development of power systems, whose optimized design requires the analysis of a broad spectrum of operational conditions, ranging from full-system investigations over many periods of operation, down to the detailed analysis of a single switching transition. In this work, a comprehensive electrothermal compact model of an IGBT module rated at 6.5kV-600A has been developed. Then, the capabilities of the considered approach have been demonstrated with a variety of simulation examples in the framework of a scenario with relevance for railway traction applications. Indeed, the proposed model predicts effects such as the voltage overshoot, the short current tail of field-stop devices and the appearance of the Miller-plateau, which can be only rendered realistically, if electro-thermal coupling is taken into account correctly. The inclusion of coupled electro-thermal and package-related inductive effects is also essential when the effects of the load unbalance have to be simulated in some operation modes, such as short-circuit. In this case, the transistors dissipate a large amount of power and the junction temperature rapidly increases up to critical values. Global view of the modeling approach for the temperature control loop in an integrated MOSFET power switch for automotive applications. Schematic cross-sections of the semiconductor devices showing the intrinsic components which are taken into account in developing the model. The IGBT has a planar-gate field-stop technology, while the diode is of the emitter-controlled type and also features a backside buffer layer. 72

75 Packaging Reliability of Advanced Microelectronic Devices Mauro Ciappa; Uni Bordeaux: Yves Danto ETHZ Uni Bordeaux References: [P12] With the continuous evolution of technologies packaging and assemblies reliability assessment remains a challenge needing cooperative efforts from the research community. As for integrated devices, in some application fields very high reliability levels with failure rates down to 10-8 failure/hour are required. At the same time, there are harder and harder mission profiles as a consequence of the generalized use of electronics devices in almost any human activity. The packaging and assemblies engineering domain is characterized by a wide multidisciplinary aspect associating in the same device different processes and materials. For a coordinated implementation of builtin reliability programs, this needs to associate a large panel of skills, such as organic chemistry, mechanics, thermo-mechanics, material science, etc. The best practices for lifetime design also demand further progress in the field of degradation and failure modeling, in which physical simulation tools are powerful means if used in conjunction with experimental accelerated testing. In this project, the last trends in packaging reliability have been assessed worldwide by leading to the publication of a special issue of the IEEE Transactions of Material and Device Reliability. This technology survey especially focused on electrical, thermal, and stress-migration effects in solder bumps, modeling and simulation of lead-free BGA assemblies, design of smartcard modules, as well with the reliability of low-k bumped chip technology. Microprocessor mounted in a cavity-down pin grid array package 73

76 Research Projects Bio-Electromagnetics and Electromagnetic Compatibility Coordinator: Niels Kuster (Adjunct Professor of Information Technology and Electrical Engineering) 74

77 Numerical and Experimental Evaluation of the Thermal Load Caused by Cellphone-use by Adults and Children Analysis of Age Dependent Anatomical and Biophysical Changes of the Exposure of Brain to Cellphone Radiation IT IS: Marie-Christine Gosselin, Sven Kühn, Manuel Murbach, Andreas Christ, Niels Kuster IT IS: Marie-Christine Gosselin, Sven Kühn,Marcel Zefferer, Andreas Christ, Niels Kuster BfS BfS IT IS IT IS For the evaluation of age dependent changes in tissue heating due to cellphone-use, a combined study was carried out using head models of of adults and children and measurements of 24 volunteers (16 adults and 8 children). For the simulation of the temperature, the SAR was calculated for a generic mobile phone with monopole antenna and CAD model of a commercial phone. The SAR of the phones was measured for validation and for power normalization. The exposure set-up for the volunteers consisted of the two phones models mounted on the both sides of the heads and of four thermal probes placed into the auditory canals and on the cheeks of the volunteers. A temperature increase of about 0.05 C was observed in the adult volunteers after 7.5 minutes of exposure with the generic phone. Since the generic phone has no electrical parts which heat up during operation, this increase can be attributed to the RF losses in the tissue. For the commercial phone, a temperature increase was observed as soon as the device was switched on regardless of the actual RF output power. The evaluation of the measurements of the children was difficult because their movements caused substantial noise on the signal. The numerical results are of the same order of magnitude, but they suffer from a large uncertainty because of the high variance of the thermal tissue parameters reported in the literature. Neither the numerical nor the experimental evaluation suggested a higher risk of tissue heating due to mobile phone use in children than in adults. In order to assess age-dependent changes of the exposure of the head and the brain to cellphone radiation, four anatomically correct high-resolution models of the heads of three children and one adult were exposed to the radiation of mobile phone models with three different antenna types (monopole, helix, integrated dual band) working in the GSM 900 and 1800 bands. Additionally, the head tissues were assigned age-dependent sets of dielectric parameters using data from a recent experimental evaluation of pig tissue. One of the main determinants of the SAR in the head of a cell phone user is the thickness of the pinna when holding the phone against the ear. In order to assess potential differences between adults and children, a particular gauge was developed, the pinnae thicknesses of about 50 volunteers (adults and children) were assessed, and the pinnae of the anatomical models were adapted. The average SAR in particular regions of the brain was extracted and compared for all simulated configurations. The 10 g SAR for head tissue was also assessed and compared to the SAR in the SAM phantom, which is used for cell phone compliance testing. The study shows that the exposure of particular inner regions of the brains of young children can be higher by more than a factor of two in comparison to adults because of their relative positions with respect to the phone. No age dependent changes could be observed for the Peak Spatial Average SAR. The evaluation of the impact of the pinna thickness is ongoing. Temperature distribution in the head of the 11-year-old child head model exposed to one generic phone at 900 MHz; one volunteer during the experiment; thermal probe for insertion in the ear. Head of the Virtual Family Boy (6 years old) with some highlighted brain structures. 75

78 Analysis of the Exposure of the Unborn Child to ELF and RF Fields in Uncontrolled Environments Analysis of the Whole Body Exposure of Children with Respect to RF Safety Limits SNF NFP 57 IT IS: Roxana Djafarzadeh, Barbara Bühlmann, Nicolas Chavannes, Sven Kühn, Marcel Zefferer, Andreas Christ, Niels Kuster IT IS: Roxana Djafarzadeh, Gernot Schmid,Sven Kühn, Marcel Zefferer, Stefan Cecil, Richard Überbacher, Andreas Christ, Niels Kuster BfS IT IS IT IS, ARCS In its latest research agenda for radio frequency fields, the WHO recognizes the importance and need for research on the numerical modeling of pregnant women and the assessment of the exposure in the womb. This project aims at the comprehensive assessment of the exposure of the fetus to different field sources in uncontrolled environments in a frequency range from khz up to GHz. Anatomical models of a woman in different gestational phases (3 rd, 7 th and 9 th month of pregnancy) are developed. The models are based on magnetic resonance images of pregnant women and are complemented by different literature sources where necessary. The models of the fetuses in the wombs are integrated into the female adult of the Virtual Family. Based on a literature survey, electromagnetic field sources in uncontrolled environments are selected. These include ELF sources, such as electronic article surveillance systems, induction cook tops or high voltage transmission lines. In the high frequency sources, the exposure due to different types personal communication devices, wireless LAN transmitters and far-field like exposure is evaluated. The analyses are carried out using the finite-difference time-domain method (high frequencies) and a particularly developed quasi-static solver based on the finite-element method which is capable of handling complex anatomical models with several million mesh cells. Several recent publications have indicated that whole body plane wave exposure of children at field strengths corresponding to the ICNIRP safety limits may yield whole body averaged SAR (WB-SAR) values higher than the corresponding basic restriction of 0.08 W/kg. This can occur at the body resonance and in the frequency range around 2 GHz. The data available so far are based on a very low number of generic models of children which are based on scaled adult models. In order to investigate this issue in more detail, numerous FDTD simulations were performed using six highly detailed anatomically correct models of children (5-14 years of age) developed from- MR scans of volunteers. The figure shows the plane wave power density required to produce a whole body SAR of 0.08 W/kg. The results in the whole body resonance frequency range are only shown for the model of the six year old child (Thelonious). At whole body resonance, the power density required for a WB-SAR of 0.08 W/kg is approximately 15 % lower than the corresponding reference level. In the frequency range around 2 GHz it can be seen that this deviation is up to about 35 % for the smallest of the considered child models. Above approximately 5 GHz, the ICNIRP reference levels can again be regarded as conservative for all of the models used in the study. Additional models and further investigations are necessary to find an envelope for the reference levels that is conservative for any person, including even young children. Seven month old fetus in the womb of the female model. Power density for a whole body SAR of 0.08 W/kg for the different child models ranging from 14 years of age (Louis) to 5 years (Roberta). 76

79 Development of Standardized Techniques to Assess RF Induced Heating of Medical Implants during MRI Exams Development of an Anatomical CAD Model of an Obese Adult Male IT IS: Eugenia Cabot, Sven Kühn, Myles Capstick, Esra Neufeld, Michael Oberle, Andreas Christ, Niels Kuster IT IS: Eugenia Cabot, Andreas Christ, Michael Oberle, Sven Kühn, Jurriaan Bakker, Gerard van Rhoon, Niels Kuster SPEAG, Zurich MedTech ZonMW (NL) SPEAG, Zurich MedTech IT IS, Erasmus Medical Center Patients wearing electrically conducting medical implants are generally excluded from magnetic resonance imaging (MRI) because of hazardous tissue heating which can be caused by currents induced on the leads of medical implants by the radio frequency fields of the scanner. The standardized methods for the assessment of implant heating are currently under revision by different working groups, and the goals of this study are to contribute toward the accuracy and the repeatability of these testing methods. The evaluation of RF induced implant heating follows a combined numerical and experimental approach: The incident electric field the implant is exposed to is determined numericaly using high resolution body models considering a representative sample of the patient popupation. The incident fields are correlated to the magnetic RF field B 1. The implant is then exposed to well defined field conditions in a setup based on a birdcage coil (MITS 1.5, ZMT Switzerland) and a particularly developed body phantom with well defined field conditions. The near field scanner DASY 5 NEO (SPEAG, Switzerland) is used to measure SAR and temperature distribution around the implant tip. The tissue heating in the patient can then be assessed numerically based on the experimentally assessed RF energy at the lead tip, again using anatomical high resolution models of the human body. Currently, about 20 anatomical whole body models for dosimetric simulations are available to the scientific community. These models are based on computer tomography, magnetic resonance images or cryosection photographs of Asian or Caucasian subjects. For most models, volunteers with an average build were selected in order to warrant high representativeness with respect to the general population and good acceptance by the scientific community. However, actual representativeness cannot be assessed by evaluating a group of models with similar features. The variability must be quantified by considering extreme cases, such as highly obese models. For the dosimetric assessment of the exposure to electromagnetic fields, a model with a high body fat content is of particular interest because the dielectric properties of fat tissue differ distinctly from those of most other soft tissues. The realistic representation of the fat tissue distribution in the body of the model is of highest importance, because the dielectric contrasts are likely to cause hot spots due to, for example, standing wave effects. Within this framework, a CAD model of a 37 year old volunteer (1.75 m, BMI approx. 35 kg/m 2 ) is being developed based on high resolution magnetic resonance images. The model will distinguish about 80 different tissues and organs. The limbs of the model can be articulated using the software SEM- CAD. The application range of the model encompasses whole and partial body SAR assessment, e. g., during MRI examinations or the assessment of X-ray doses in radiation physics. Measurement setup: phantom inside the RF birdcage coil. Detail: SAR distribution measured for a generic test implant (insulated wire of 200 mm length). Reconstructed 3D image of the volunteer in a model of an MRI birdcage coil. 77

80 Experimental Evaluation of the SAR Induced in a Head Phantom of a Three Year Old Child Full Wave SAR Assessment in Front of Representative Base Station Antennas Sven Kuehn; IT IS: Marcel Zefferer, Emilio Cherubini, Marie-Christine Gosselin, Andreas Christ, Niels Kuster IT IS: Marie-Christine Gosselin, Sven Kuehn, Niels Kuster BfS MMF, GSMA SPEAG This study addresses the ongoing controversy over whether the current compliance test procedure based on a large adult head (SAM) is also appropriate for children. We experimentally evaluated the influence of the human head anatomy with respect to compliance testing of mobile phones on a SAM head and on a child head. A 3D CAD representation of a shell of a head model based on MRI scans of a 3 year old child s head was developed. Based on the shell data, an experimental child head phantom was manufactured using a laser-sintering process. The shell has a thickness of 2 mm (6mm at the ear) and is fully compatible with standard head tissue simulating liquids. The evaluations were based on two Generic Mobile Phones operated at 900 and 1800 MHz as well as a Motorola T250 mobile phone operated in the GSM900 and GSM1800 bands. The SAR of the mobile phones were experimentally and numerically assessed on the right hand side in standard touch and tilt positions using the standard tissue simulating liquid properties in accordance with IEC The results in the child head were compared to results obtained in the standard compliance test phantom (SAM) and to numerical results in heterogeneous head phantoms. Good agreement between the numerically and experimentally determined SAR distributions in the homogeneous child head was obtained. The results confirm those of previous numerical studies comparing the energy absorption in different human heads and the SAM, i.e., the SAM phantom also conservatively estimates the peak spatial specific absorption rate (SAR) exposure in children. The presented study has been conducted to support the International Electrotechnical Commission in the elaboration of a new international standard. The aim of this project is to use various detailed human models and generic base station antennas to assess the specific absorption rate (SAR) in workers in front of base station installations and to derive an estimation formula that could be used to easily estimate that SAR. Two different generic base station antennas have been modeled and validated with FDTD and MoM for six different frequencies ranging from 300 MHz to 5,000 MHz. Three human models of the Virtual Family have been used: an adult male, an adult female, and a 6-year-old boy. The models have been placed at six distances from every antenna, ranging from 10 mm to 3,000 mm. The whole-body average SAR and peak spatial average SAR have been evaluated in all possible 432 configurations of a human model, orientation (face and back), antenna and distance. An estimation formula for the whole-body average SAR and the peak spatial average SAR has been developed. The physical and electrical characteristics of the antennas have been used, as well as an homogeneous cuboid as a representation of the human body. The estimation formula is based on a worst-case exposure consideration in order to be conservative. Finally, the estimation formula has been validated against our simulation results. Experimental phantom for dosimetric assessments in child head with a generic mobile phone. Shown is the physical phantom with mobile phone (white) in overlay on top of the numerical repesentations of both. E-field and far-field pattern created by one antenna at 2,100 MHz; E-field around and inside the VFM model. 78

81 SAR Assessment from Mobile Phones Used with Wired and Wireless Hands- Free Kits Dosimetric Assessment of Human Epidermis Exposed In Vitro to 900 MHz Electromagnetic Field Sven Kuehn; IT IS: Eugenia Cabot, Niels Kuster IT IS: Manuel Murbach, Sven Kühn, Niels Kuster BfS SPEAG IT IS, SPEAG There has been debate on whether the use of handsfree kits (HFK) with mobiles phones could lead to an increased amount of absorbed radio-frequency energy in the users head. The confusion has mostly arisen due to the methodically problematic studies using unrealistic compliance test scenarios. Studies that reported a higher exposure, for instance, often neglected the attenuation along the cable of wired HFK. However, there still remains uncertainty about 1) the actual exposure when using wired and wireless HFK, and 2) sound compliance test procedures. The most important questions discussed in this study are whether separate compliance testing is required for HFK and the extent to which the use of wired and wireless HFK can reduce human exposure The SAR from wired HFK was evaluated experimentally while connected to mobile phones (GSM900/1800, UMTS1950) under maximized current coupling onto the HFK cable and various cable routing configurations along the absorbing bodies. The SAR from wireless HFK was also measured in a novel phantom for devices that are partially surrounded by tissue. Simulations were performed for a HFK and a mobile phone being operated on anatomical whole-body models. In conclusion, wired HFK reduce the exposure of the head region considerably compared to the phone operated at the head. Wired HFK may cause a localized increase in the exposure in the inner ear. Wireless HFK showed a low SAR. There is evidence that pulse-modulated radio frequency electromagnetic fields (RF EMF) elicit biological effects in a variety of organisms. Studies of human epidermis in vitro represent an alternative to in vivo studies, not only in cosmetics. The aim of this study is to provide dosimetric means for the exposure of human reconstituted epidermis to 900 MHz EMF. The epidermis layer with a thickness of about 10 mm is maintained on top of a dermis layer 2-5 mm thick, and surrounded by 2 ml of culture medium within a 35 mm Petri dish. Main difficulties consist of the high variability of size and shape of the dermis part, as well as dielectric measurements of material properties. Exposures are performed within the sxc900 exposure system already developed. Positioning of the epidermis at the H-field maximum of the waveguide results in high SAR levels while maintaining a very low thermal load. This novel approach of exposing human epidermis in vitro may lead to intriguing new findings. Virtual Family Billie and Duke models with mobile phone and wired hands-free kit as used in the FDTD simulation in order to estimate the human exposure in anatomically correct models. Numerical model of human reconstituted epidermis (green) on dermis layer within petri dish, and slice view of the SAR distribution. 79

82 Dosimetric Assessment of C. elegans Exposed In Vivo to 900 MHz Electromagnetic Field System to Study CNS Responses of ELF Modulation and Cortex Versus Subcortical RF Exposures IT IS: Manuel Murbach, Sven Kühn, Meike Mevissen, Niels Kuster IT IS: Manuel Murbach, Maria Christopoulou, Sven Kühn, Esra Neufeld, Andreas Christ, Peter Achermann, Niels Kuster SNF NFP57 SNF NFP57 IT IS, SPEAG, Uni Bern IT IS, SPEAG, Uni Zurich There is evidence that pulse-modulated radio frequency electromagnetic fields (RF EMF) elicit biological effects in a variety of organisms. The nematode C. elegans as an in vivo system is a well known model organism and qualified for research on EMF effects. However, dosimetric assessment has so far been restricted to thermal evaluations. The aim of this study is to provide detailed dosimetric data on in vivo exposure of C. elegans to 900 MHz EMF. The C. elegans nematodes were exposed on 9.5 ml AGAR within NUNC 60 mm Petri dishes inside the sxc900 exposure system. The dielectric properties of all materials were assessed. The measurement of the C. elegans was performed using a 1 ml sample of concentrated nematodes. This nematode paste was obtained by filtrating the C. elegans through a 0.22 μm filter. The numerical FDTD analysis was conducted using the simulation platform SEMCAD X (SPEAG). As the nematodes are fairly small (diameter < 60 µm, length < 1 mm), separate simulations were used for AGAR and C. elegans. The elaborated configuration results in an exposure nonuniformity of less than 3 db for the adult nematodes, and allows for exposure levels up to 5 W/kg without exceeding 0.1 C thermal load. There is increasing evidence that pulse-modulated radio frequency electromagnetic fields (RF EMF), such as those emitted by mobile phones, can alter brain physiology. Changes in EEG, regional cerebral blood flow (rcbf) and cognitive function have been reported. Subsequent studies must be designed to obtain information about the site of interaction as well as the interaction mechanism. Novel tools and setups for human brain EMF exposure were developed to achieve focused and distinguished exposures of selected functional brain regions with a variety of exposure signals. These setups will be employed in the Swiss Research Program NFP57 to test the following hypotheses: 1) the modulation is a key parameter, 2) the thalamus is the main site of interaction, and 3) adolescents are particularly sensitive to RF EMF exposure. A novel postprocessing module was implemented in SEM- CAD X that subtracts and analyzes the dosimetric information for all 1105 functional subregions of the Talairach- Space. Transformation of any brain can be conducted automatically by defining eight distinct landmarks in the brain. Setups emitting EMF with different carrier frequencies are being developed using this numerical tool. Nematode C. elegans in SAR model and microscopic view. Adults can grow up to 1 mm length, with a diameter of approximately 60 µm. SAR distributions for 900 MHz and 2140 MHz, resulting in different penetration depths, and Talairach mapping with functional subregions of the brain. 80

83 Evaluation of Artifacts by EEG Electrodes During RF Exposures Development of MRI Exposure Risk Probability Based on Local Temperature Safety Considerations IT IS: Manuel Murbach, Maria Christopoulou, Sven Kühn, Esra Neufeld, Andreas Christ, Peter Achermann, Niels Kuster IT IS: Manuel Murbach, Sven Kühn, Esra Neufeld, Andreas Christ, Michael Oberle, Niels Kuster SNF NFP57 KTI, Zurich MedTech IT IS, SPEAG, Uni Zurich IT IS, IBT-ETHZ, Philips, Siemens, Erasmus Medical Center, INTEC, Uni Athens, Charité Berlin, FDA, SPEAG, Zurich MedTech There is increasing evidence that pulse-modulated radio frequency electromagnetic fields (RF EMF), such as those emitted by mobile phones, can alter brain physiology. For practical reasons, the exposure prior to sleep is often performed with subjects having their EEG electrodes already attached in order to minimize time between exposure and sleep onset. While the shielding effect of the leads has been sufficiently assessed, possible artifacts from electrodes have been analyzed in respect to the spatial peak SAR only. The aim of this study is to (1) quantify possible field enhancements and currents coupled via EEG leads to the tissues around the electrodes leading to high temperature increases in skin and superficial brain structures and (2) the change of coupling of the incident field to the head by shielding of the conducting wires at 900 MHz and 2140 MHz. Results were compared with numerical simulations using SEMCAD X (SPEAG AG, Switzerland). The penetration depths of the field distortions caused by the electrodes were simulated using a flat human head tissue model. Findings were put in context to the dosimetric assessment of the exposure pattern. The purpose of this project is to reduce MRI scan times and optimize image quality at lower costs as well as increase the safety of patients (with and without implants) and MRI personnel. The research tasks are to investigate validated hazard threshold models as a function of the MRI equipment, scanning procedures and implants, to develop appropriate instrumentations and testing procedures, and to optimize scanning sequences. The project will be performed by an international consortium, including major MR manufacturers (Philips, Siemens), the regulatory agency FDA and seven leading academic partners in this field, including the MR research group at the ETH and the IT IS Foundation. The instrumentation and test systems will be developed and commercialized by ZMT, a Zurich based start-up company. Overall, the project results will have important economies for society at large, including patients and hospitals as a result of better and safer diagnostics and lower costs. SAR measurements without and with attached EEG electrodes. Very localized field distortions can be identified. SAR and incident field measurement within MRI bore (distortions due to high magnetic field strengths). 81

84 An Investigation into Occupational Exposure to EMF for Personnel Working With MRI Equipment Large-scale and Fast FDTD Calculation Using a GPU-Based Cluster (C-Type CIB) with Two or More Nodes IT IS: Manuel Murbach, Myles Capstick, Andreas Christ, Sven Kühn, Eugenia Cabot, Michael Oberle, Niels Kuster Guillermo del Castillo; IT IS: Nicolas Chavannes, Niels Kuster KTI, Zurich MedTech KTI, IT IS Partners IT IS, IBT-ETHZ, Philips, Siemens, Erasmus Medical Center, INTEC, Uni Athens, Charité Berlin, FDA, SPEAG, Zurich MedTech IT IS, SPEAG Magnetic Resonance Imaging (MRI) is a rapidly developing diagnostic technology that provides an unmatched view inside the human body without applying ionizing radiation. Improved image quality and novel applications, however, generally require higher electromagnetic field (EMF) strengths and faster image acquisitions, both of which may result in an increase in the EMF exposure of patients and workers. Recently, new safety directives are enforcing the ICNIRP guidelines for electromagnetic exposures. It is feared that these decisions might unnecessarily restrict current and future developments in the field of MRI technology. Our endeavor is aimed at filling gaps in knowledge about actual exposure levels for patients and occupational personnel during routine MRI procedures. Potential short-term hazards are, for example, nerve stimulation resulting from induced currents caused by gradient fields and movements in the static fields as well as thermal tissue damage from the exposure to radio frequency (RF) electromagnetic fields. Workers exposed occupationally include radiologists, interventionalists, nurses, researchers, technicians and other personnel such as cleaners. Our focus is on gaining comprehensive understanding of medical MRI procedures, identifying possible worst-case scenarios, and developing appropriate measurement instrumentations. The FDTD method applied to Maxwell s equations is ideal for distributed computing since the x, y and z components of the electric and magnetic fields can be integrated independently for each time-step. One approach takes advantage of the high memory bandwidth of graphics boards to accelerate computational intensive applications. Graphics cards possess much greater computational parallelism than single or multicore CPU-based systems. This is especially useful while using the FDTD method, since this particular scheme is very dependent on memory access. The downside is the maximum size of simulations that can be executed is fixed, and such systems are not easily scalable. In terms of CPU-based systems, the standard solution is to have a series of cores in a global shared memory network (using MPI, for instance). However, the global RAM is the major limitation and bottleneck in FDTD computations and has a greater impact than processing power. The net effect is slower solver speeds than GPU-based solutions. The current project at IT IS tests the viability of a system that combines the advantage of a having a global shared memory of the network -- large size simulations with the gain of using GPU-based components high solver speeds. This platform has been named C- Type cluster. MRI birdcage model exposure of occupational personnel standing next to scanner system. Highly Detailed Model of Hand and Portable Phone. 82

85 FDTD Calculation via GPU Using NVID- IA s Compute Unified Device Architecture (CUDA) Language Novel Hyperthermia Applicator for Head and Neck Region with Antenna Array Guillermo del Castillo; IT IS: Nicolas Chavannes,Niels Kuster Chung-Huan Li; IT IS: Nicolas Chavannes, Niels Kuster; BiWi: Esra Neufeld KTI, IT IS Partners KTI, IT IS Partners IT IS, SPEAG The FDTD method applied to Maxwell s equations has the characteristic that the x, y and z components of the electric and magnetic fields can be integrated independently for each time-step. This characteristic makes the method particularly suited for a parallelizing approach. One approach takes advantage of the high memory bandwidth of graphics boards to accelerate computational intensive applications. Graphics cards possess much greater computational parallelism than single or multicore CPU-based systems. This is especially useful while using the FDTD method, since this particular scheme is very dependent on memory access. RAM is, in fact, the major limitation and bottleneck in FDTD computations, and has a greater impact than processing power. Using NVIDIA graphics processing units (GPUs) and hardware designed by Acceleware, a partner company of SPEAG, it is possible to run highly detailed simulations in relatively inexpensive desktop computers. NVIDIA also provides a general programming platform, the Compute Unified Device Architecture or CUDA. This project intends to compute FDTD simulations using CUDA on NVIDIA GPU-based systems. Hyperthermia, or thermal therapy, is a type of cancer treatment where heating the target tissue (tumor) is heated to kill the cancer cells or enhance other treatments. The equipment which delivers the thermal energy is called an applicator. In the head and neck region (H&N), there are many important tissues. The side effects of standard treatments may seriously aect the patient s quality of life. On the other hand, so far there is only minor toxicity found due to hyperthermia treatment and this is an unique feature in cancer treatments. In addition, it is reported that radiation therapy or chemotherapy combined with hyperthermia in the tumors at H&N region can enhance the local tumor control and/or survival rates. In this study, the proposed applicator consists of a 40cm diameter ring antenna array (at 433MHz) with 20 cavity-backed slot antennas which delivers and focuses the EM power at to the target tumor to raise the temperature in the tumor. A water bolus lled with de-ionized water is placed between the applicator and the patient. However, most studies about the applicator design is only focus on the applicator itself, but the patient position is also great of importance to the SAR performance of the applicator. Therefore, for the hyperthermia treatment in the H&N region, the objective of this study is not only proposing an applicator, but also optimizing the patient position to the proposed applicator to achieve optimum SAR performance. H-field distribution in a car model with a Bluetooth antenna. Top: applied real patient model and proposed applicator. Bottom: SAR performance of the applicator to the patient. The EM power is concentrated on the tumor without heating other important tissues. 83

86 The Influence of the User Hand on Mobile Phone Antenna Performance in Data Mode Study of Quasi-Static H-Field Concentration on Hyperthermia Treatment Chung-Huan Li; IT IS: Nicolas Chavannes, Niels Kuster; SPEAG: Erdem Ofli Chung-Huan Li; IT IS: Nicolas Chavannes, Niels Kuster KTI 8969 PFIW-IW, LOVESim KTI, IT IS Partners IT IS, SPEAG Until now, the over-the-air (OTA) performance of mobile phones is determined by measuring the radiated 3D RF power and receiver performance in an anechoic chamber while the phone is in touch position at a SAM head filled with head simulation liquids. However, the grip of the hand (positioning of fingers and palm with respect to the phone) is also of great importance. Many studies have demonstrated that different positioning of the hand phantoms induces significantly different antenna performance. In addition, the influence of the user hand is not only in the talk mode (when the user is talking on the mobile phone), but also it is significant in the data mode (when the user is browsing or typing text with the mobile phone). The effect of the hand in the talk mode has been studied extensively in terms of the OTA performance. Therefore, the objectives of this study are to determine the effect of different hand grips and positions on the mobile phone antenna performance on the data mode. Instead of phone + head + hand on talk mode, the configuration of this study is phone + hand. The referenced parameters included radiation and mismatch efficiency as well as TRP. These data allow the setting of the necessary specifications and the general requirements for a hand phantom to evaluate mobile phone antenna performance. This study is investigating the possibility of having a focus area with a quasi-static magnetic field. If a quasi-static magnetic field can be concentrated inside the desired region it can be applied to hyperthermia treatment (HT), and the water bolus that is generally used on most HT applicators can be removed. In addition, the concept can be also applied to HT for different regions of the patient s body. Because of the quasi-static magnetic field, the Biot- Savart law was employed in this report to calculate the magnetic field in the treated area induced by current elements. The investigation is separated into three studies: 1) 1-dimension, analytical: the magnetic field concentration was studied in an analytical approach with 1-dimensional configuration. The current coefficient of each element is real number. Thus, all the elements can be different in magnitude with in-phase and anti-phase to each other. 2) 1-dimension, simulation: in this study, the current coefficients are represented by complex numbers in the simulation tool, that is, phase is included in the current coefficients. 3) 2- and 3-dimensions, simulation: a general 2-dimensional and a specific 3-dimensional loop configuration will be simulated to investigate the possibility of field concentration at a quasi-static situation. Top: the hand grips used in this study, the area above the antenna is divided in sixteen different locations. Bottom: the simulated TRP when the index finger of the hand phantom is on different location above the antenna. Top: the configuration for 1-dimensional hyperthermia treatment with quasi-static magnetic field. Bottom: the configurations for the 2- and 3-dimensional study, respectively. 84

87 Investigation of Cross-talk on Mobile Phone PCB with Shielding Optimization of a Metamaterial Inspired Antenna with Genetic Algorithms Chung-Huan Li; IT IS: Nicolas Chavannes, Niels Kuster; SPEAG: Peter Futter, George Tudosie Chung-Huan Li; IT IS: Nicolas Chavannes, Niels Kuster KTI, IT IS Partners KTI, IT IS Partners This project is an industrial case of PCB level EMI/EMC problem studied with a leading manufacturer by using a FDTD simulator, SEMCAD X. Usually, frequency domain simulators are popular in EMI problems investigation since time domain simulators need very long time to solve these problems. However, the simulation performance of FDTD has been dramatically improved in these years, therefore, now FDTD simulator is also possible to be a tool to solve EMI/EMC problems in real world with its advantages. In this case, a real mobile phone PCB model is applied in this study. There are sixteen sources at the center of the PCB and three 50 Ohm resistors, called victim ports. The desired parameter, Isolation, is defined as the ratio between the input power from the sources and the received power to the victim ports. In addition, three different configurations shielding on the PCB are integrated in the simulations to inspect the influence of the shielding to the isolation. Since the real PCB model is complicate, a simplified PCB model is built to analyze the coupling mechanism between the sources and victim ports. In metamaterial-based antenna design, a metamaterial shell is applied to surround an electrically small antenna to compensate for the strong reactive energy that an electrically small antenna inherently has and to create resonance for radiation. However, the realization of metamaterial is still difficult at arbitrary frequency and that makes the metamaterialbased antenna not currently practical. Therefore, applying a similar concept, a capacitive metal shell was built to surround an electrically small loop to compensate for the inductive energy generated by the loop. The compensation induces the resonance to make the antenna radiate efficiently. On the other hand, since antenna performance is very sensitive to the geometry of the antenna, impedance match at the desired frequency is a difficult and timeconsuming issue. Consequently, optimization with an EM simulator is significant in this case. In addition, as this geometry is characterized by more than ten parameters, a genetic algorithm can be an appropriate choice for the optimization. Top: the real mobile phone PCB model. Bottom: the simplified PCB model for studying the coupling mechanism on the real model. Top: the geometry of the metamaterial inspired antenna, electrically small antenna with a capacitive shell. Bottom: the optimized return loss of the antenna. 85

88 Realistic Skeleton Based Deformation of High-Resolution Anatomical Human Models for Electromagnetic Simulation Static and Low Frequency Extensions of EM Solver Package for Human Body Compliance Stefan Schild; IT IS: Nicolas Chavannes, Niels Kuster; SPEAG: Emilio Cherubini IT IS: Stefan Benkler, Nicolas Chavannes, Niels Kuster KTI 8969 PFIW-IW LOVESim KTI 8969 PFIW-IW LOVESim IT IS, SPEAG IT IS, SPEAG Several techniques have been presented to deal with skeleton-driven deformation of 3D skin models for visual purposes only. The work presented here extends and combines these techniques to deal with high-resolution full-body anatomical models, including deformation of all tissues and organs surrounding the rigid bones in an efficient way. This work also focused on a visual system to setup the hierarchical structure of bones that drive the anatomical deformation in an simple way. The goal of this work was the development of a system which takes a high-resolution anatomical model and allows a visual setup of the influencing bones. The bone hierarchy allows propagation of transformations through a whole limb if the user moves the parent bone, on the other side the tool makes use of known methods to solve the Inverse Kinematics problem to achieve a desired pose of the bone structure while satisfying user defined joint constraints. The next step is the actual computation of the deformation with immediate visual feedback to the user. The resulting transformation of an element of the model is computed using a method which blends the transformations of all influencing bones. To ensure a more realistic deformation, the rigidity of the bone is considered and a simple spring correction is used on the non-rigid parts of the model. The posed anatomical models are finally used to simulate exposure to and interaction with electromagnetic radiation. In the last decades, the finite-difference time-domain method (FDTD) has proven to be an efficient and powerful numerical tool. Especially for interactions of complex human body models and electromagnetic (EM) fields, the FDTD method is highly valuable to assess electromagnetic compatibility at radio frequencies. However, at lower frequencies the FDTD method becomes inefficient due to the explicit time integration scheme. Using quasistatic approximations of Maxwell s equations can lower the computational burden considerably. The electric and magnetic quasi-static approximations (EQS and MQS) to Maxwell s equations have been implemented using the finite element method (FEM) in frequency domain. The nonuniform but rectilinear computational grid of the FDTD method has been reused to benefit from the model discretization and postprocessing capabilities of the graphical user interface SEMCAD X. Another important reason for rectilinear grid is the usage of very detailed human body models, which can be only discretized efficiently on this kind of grid (almost one hundred distinguished tissues). Thus, these models are immediately applicable for the low frequency solver, which is an essential feature of this study. The new low frequency solver package was applied to highly complex human body configurations. The EQS model was used in assessing the impact of a person touching a power line at 50 Hz. Figure shows the current distribution of the person touching with her right hand a 600 MΩ rod connected to the power line. Future version of virtual family members will allow to position each part of the model individually (ongoing research). A special MQS model addressed the safety of workers operating close to a MRI machine, i.e., the magnetic fields of the gradient coils operated at 1 khz. Again the current distribution was of major interest. The numerical approach of this study has proven to be very effective to assess interactions between detailed human body models and electromagnetic fields at low frequencies. Figure shows a posed full body model. Preliminary result: a person holds a rod connected to a power line. The EQS model (ohmic current dominated) is used to assess the current distribution (right) inside the body. 86

89 The Power of Generalized Huygens Wave Excitation FDTD Calculation via GPU using NVID- IA s Compute Unified Device Architecture (CUDA) Language IT IS: Stefan Benkler, Nicolas Chavannes, Niels Kuster Guillermo del Castillo; IT IS: Nicolas Chavannes, Niels Kuster KTI 8969 PFIW-IW LOVESim KTI, IT IS Partners IT IS, SPEAG IT IS, SPEAG A wide range of powerful electromagnetic simulation tools are available today that are based on different methods of computational electromagnetics developed over the past four decades. Each of these software packages can simulate real world problems of large complexity but is limited to a certain problem category. These categories can be characterized as spatial dimensions in terms of wavelength. Examples are wave propagation in cities (Ray-Tracing), electrically large antennas and scatterers (MoM=Method of Moments), mobile phone mounted on the body (FDTD=Finite-Difference Time-Domain), microdevices implanted inside the body or structures on semiconductors (FEM=Finite Element Method). For example, FDTD method is well-suited for problem extensions between 0.01 to 10 wavelengths whereas the computational effort scales with the power of 4 (time step x number of cells) and the memory requirements with the power of 3 with respect to spatial refinements. To reduce the overall computational effort, one can (1) minimize the number of cells, (2) increase smallest spatial step (therefore the time step), and/or (3) decrease the resonant characteristic of the model (therefore smaller physical end time of simulation, i.e., less time steps needed to reach it). Exactly, these three items are the target of the novel Huygens FDTD source. The figure shows a possible simulation scenario, where the subsystems antenna, antenna-human and human are very weakly coupled. Therefore, it is sufficient to simulate one subsystem after the other in the sense of a unidirectional subgridding. The novel Huygens source can therefore act as a powerful hybridization platform linking other methods (e.g. MoM, FEM, ray-tracing, etc.) to FDTD or as a FDTD-FDTD subgridding scheme. The key point was to generalize the total field scattered field (TFSF) plane wave excitation and therefore, enabling virtually any incident field to be used as excitation field. The overall goal is to develop a method to non-invasively characterize cardiac blood-flow dynamics, including stroke volume and cardiac output along with spatial resolution of flow profiles. The research develops techniques to gather information about blood flow that can supplement present non-invasive ultrasound techniques for the evaluation of heart failure. This additional blood flow information is based on a new physiological marker. This marker is the magneto-hydrodynamic (MHD) signal recorded on the ECG (Electrocardiogram) while the subject is exposed to a strong static magnetic field. The MHD signal is caused by induced electrical currents in the blood due to the blood flow in the magnetic field and is detected as distortion in the electrocardiogram (ECG). Therefore, we hypothesize that the MHD signal is capable of rapid and non-invasive measurement of blood flow characteristics that are necessary for evaluating heart failure, particularly diastolic heart failure. Such signals have been collected in both animals and humans by other investigators. Electromagnetic modeling using anatomically accurate models of the human has been done. Currently available anatomical models, such as Virtual Family, will permit the exact calculation of the MHD signal locations as vectors that may be used as functional biomarkers for cardiac blood-flow dynamics. The developed MHD solver is able to calculate the induced current distribution and the equi-potentials in simple geometries. Preliminary validation of the MHD solver shows good agreement with values found in the literature. The implemented MHD solver is also able to calculate the induced fields in highly accurate models of the human anatomy. A MoM solution is used as input for the FDTD solvers (left). Different anatomies and postures can be analyzed without solving the entire problem. Highly vertical flow during flow reversal phase in the human abdominal bifurcation. 87

90 A Complete Framework for the Modelling of Third Order Nonlinear Effects in FDTD Refinement Schemes Applied to a Fully Interactive Novel Grid Generator in FDTD Stefan Schild; IT IS: Nicolas Chavannes, Niels Kuster Stefan Schild; IT IS: Nicolas Chavannes, Niels Kuster KTI 8969 PFIW-IW LOVESim KTI 8969 PFIW-IW LOVESim IT IS, SPEAG IT IS, SPEAG Modeling nonlinear effects such as the Kerr effect or Raman Scattering in FDTD pose significant challenges due to effects such as the generation of frequency components. Because such effects depend on the field strengths present in a nonlinear material during a simulation, their impact on the simulation stability is difficult to predict during the simulation setup. A novel framework provides a set of tools to minimize the probability of an unsuccessful simulation run. An estimate of the field strenghts to be expected in a given simulation is used to calculate the necessary discretization parameters in space and time. The approach is implemeted into an interactive grid engine to allow the most flexible control possible while ensuring a reliable discretization. The implemented nonlinear kernel is able to simulate arbitrary combinations of any number of first order Drude-, Debye-, and Lorentz-poles with the third order Kerr effect and Raman scattering. An eventual unstable simulation is analysed and used to adapt the discretization. Additionally, the framework implements a subcell smoothing scheme for all supported dispersion models as well as the necessary tools to extract information specific to nonlinear effects such as the effective refractive index observed in a nonlinear material at a given time. The first step in the process flow of an FDTD simulation is the generation of a spatial grid. For highly complex and very large simulations, this can be a crucial step in order to be able to run a successful simulation. Mainly, the available hardware as well as the available time impose restrictions and the maximal size and minimal resolution of a simulation which are not always easy to meet. A novel interactive grid generator can generate grid configurations in fractions of a second. Thus, it enables the user to instantly see the effects of parameter changes on the grid. This feedback mechanism optimizes the user interaction and enables the creation of a near-optimal grid configuration in the shortest possible time. The grid generator is enhanced with refinement tools designed to support the user in the two most important cases: An interactive scaling tool enables the user to approach bot not exceed the limit of the total grid size imposed by the available hardware. Thus, the highest possible accuracy for a given simulation can be exploited. An interactive tool to find the smallest grid steps and manually adjust them is used to avoid overly discretized regions and maximize the simulation time step. Simulation of a gap-soliton with the new algorithm and framework. The recorded waveform at four different points in space shows a stable envelope but also the forming of a typical precursor wave. Interactive gridding session. The scaling tool is used to discretize the helix antenna with the maximally possible resolution while the feedback window gives information about expected simulation time and total grid size. 88

91 A Novel Unified Material Architecture to Simultaneously Model Multiple Material Types Investigation of Suitability of Unstructured Meshing Techniques to Complex Biomedical Data. Stefan Schild; IT IS: Nicolas Chavannes, Niels Kuster IT IS: Dominik Szczerba, Esra Neufeld, Niels Kuster KTI 8969 PFIW-IW LOVESim BIOEM IT IS, SPEAG IT IS, SPEAG Advanced material models are gaining in importance due to today s increased computational power. At the same time, state-of-the-art research demands the investigation of such materials in very complex simulations. This creates new challenges for FDTD solvers which need to be able to succesfully simulate multiple material types in one simulation. A novel FDTD framework allows an arbitrary combination of the following material types to be present in a simulation: Lossy dielectrica Perfect metallic/magnetic conductors Lossy metallic conductors Thin conductive sheets Dispersive media (Drude, Debye, Lorentz) Nonlinear media (Kerr, Raman) The framework encompasses algorithms and an advanced user interface to ensure to reliable simulation pre-conditioning including an interactive grid engine. The impact of the different material types on the simulation stability is inherently analysed and the necessary discretization parameters in space and time are chosen automatically. Additionally, the novel pre-processing algorithm employs a subcell smoothing scheme for all material types to ensure maximum accuracy for all simulations. Generating a mesh is a necessary pre-condition when obtaining numerical solutions of partial differential equations. Since the inception of the finite element method dating back to the middle of the last century, automatic high quality mesh generation over an arbitrary domain hasremained a central topic of intensive research. We have developed a few methods to recover high quality finite element meshes from low-quality, oversampled and possibly non-consistent inputs that are often obtained via 3D image acquisition systems. Our approach exploits the following approaches: Marching cubes Constrained banded smoothing Level set based surface extraction Back-projection Decimation/simplification Surface reconstruction (alpha shapes, Poisson, power crust) Surface quality optimization Advancing front tet-mesh generation When compared to commonly used approaches based on smoothing our technique does not result in any feature loss and naturally offers refinement options. A modern UMTS PCB (CAD model and voxel representation) containing a vast number of different material types. High-quality adaptive finite-element mesh of a human ventricle. 89

92 MRI Induced Implant Heating Hardware Accelerated Thermal Simulations IT IS: Esra Neufeld, Sven Kuehn, Nicolas Chavannes, Niels Kuster IT IS: Esra Neufeld, Nicolas Chavannes, Niels Kuster; Uni Basel: Matthias Christen, Olaf Schenk KTI, IT IS Partners KTI, IT IS Partners IT IS, SPEAG, Boston Scientific IT IS, Uni Basel, SPEAG The heating of tissues around implants during MRI can pose severe health risks. A recent interlaboratory comparison study has shown that different groups can produce widely varying results when performing measurements according to current guidelines. To derive optimized procedures, generic lead structures have been investigated using simulations and measurements. The leads have been mounted and exposed in an ASTM phantom placed in a MITS1.5 birdcage coil. Volumetric EM field measurements have been performed in a liquid filled ASTM phantom with E- and H-field probes and a robot scanner system. Temperature measurements have been made in gel. EM fields have been calculated using unidirectional subgridding and graded meshes (0.1 mm resolution at leads) using SEMCAD X. Thermal simulations with a novel thin structure model have been performed. A detailed uncertainty budget has been determined. Excellent agreement between the simulations and measurements has been obtained with 96% of all measurement points corresponding within the expected combined uncertainty. When performing thermal simulations (EM induced tissue heating, electronics cooling) in the time domain using a finite differences method, the presence of highly thermo conductive or low density structures can lead to very small time steps and consequently long simulation times (e.g. MRI induced heating of metallic implants). In addition, optimization problems can require the execution of a large number of thermal simulations. These problems have led us to investigate possibilities to speed up thermal simulations. Three different approaches have been compared: GPU: This approach takes advantage of the high memory bandwidth of graphics boards. Also, graphics cards offer much greater computational parallelism than single or multi-core CPU-based systems. Cell Broadband Engine: Bandwidth-saving algorithms have been applied along with two levels of on-chip parallelism (SIMD, 8 compute cores per chip) to achieve fast simulation kernels. Parallelization: MPI-based parallelization has been implemented (CPU and Cell clusters). With these approaches speed-ups by 2-3 orders of magnitude have been obtained. Setup for measurement of MRI induced implant heating: Left: temperature measurements. Right: SAR measurements. The Cell Broadband Engine can be used to speed up thermal simulations. 90

93 Simulation the Thermal Impact of Blood Flow Time Domain Circuit Co-Simulation IT IS: Esra Neufeld, Nicolas Chavannes, Niels Kuster IT IS: Nicolas Chavannes, Niels Kuster; SPEAG: Francisco Nunez, Wayne Jennings KTI, IT IS Partners KTI 8969 PFIW-IW LOVESim IT IS, SPEAG IT IS, SPEAG Tissue heating (e.g., by EM fields) can be a relevant safety issue or a wanted behavior (hyperthermic cancer treatments). Simulation tools capable of modeling it in a realistic manner are therefore highly valuable. One of the most relevant factors to be considered is the influence of blood flow (perfusion). A thermal solver optimized for living tissue behavior has been developed. It considers microperfusion by using a homogeneous heat sink term (as introduced by Pennes) with the option of using anisotropic effective heat conductivities to account for the directivity of blood flow. Larger vessels are handled by coupling the 3D thermal simulation with a simulation of the vessel tree (pseudo 1D) able to handle laminar flow. Complex flow patterns in large blood vessels (e.g. aorta) are modeled by a convection term employing imported flow simulation results. The model can handle thermoregulation, coagulation, phase transitions as well as cell water evaporation and rehydration. Both a transient and a steady-state solver are available. The model permits for realistic simulations of heat related phenomena in living tissue. The simulation of actual RF-circuits embedded on EMsimulation has become a need in fields like mobile phone industry, wireless communications, etc... The most common technique, used on commercial EM-packages, make use of the frequency characterization of microwave devices (antennas, filters, etc...) by using full wave solvers, combining then the correspondent frequency response with RF-circuits at a circuit level, by means of a circuit simulation solver (SPICE like solvers in frequency domain). One of the main disadvantages of this approach is that real EM-efects, as coupling, are neglected, and the modelling of those at a circuit level is, in most of the cases, cumbersome and not generalizable for all situations.by treating the entire system, integrated circuits (IC) and EM-simulation, in time domain, the non-linear effects from embedded IC are naturally included in our fullwave simulation, allowing us to detect electromagnetic interference (EMI) among the electronics, being then possible identify and optimize noise sources. This works presents a direct signal modulation application. This kind of technique allows to transmit low frequency signals on the top of a high frequency carrier which can be radiated with a small integrated antenna (e.g. microstrip patch antenna resonant at the carrier frequency). The figure bellow presents the three signals involved on the tx part: pulsed data signal(black), carrier(blue) and RF modulated signal (red). The chosen antenna corresponds to a dipole centered at the carrier frequency. The receiver system corresponds to the same dipole model but including the Rx electronics. The presence of a nearby vessel affects the temperature distribution during a thermal ablation procedure. Top: Tx signal at different stages within the simulated IC+ antenna. Bottom: Dipole antenna and microstrip lines containing Tx circuit. 91

94 Implementation of Novel High-Speed SAR Averaging Routines in FDTD Talairach Based Extraction - Implementation and Application IT IS: Andreas Christ, Nicolas Chavannes, Niels Kuster; SPEAG: Pedro Crespo Sven Kuehn; IT IS: Nicolas Chavannes, Niels Kuster; SPEAG: Pedro Crespo KTI 8969 PFIW-IW LOVESim KTI 8969 PFIW-IW LOVESim IT IS, SPEAG IT IS, SPEAG This work presents the implementation of a novel highspeed technique for the evaluation of Specific Absorption Rate (SAR) averaging values within highly inhomogenous and complex tissue structures, as human bodies. In the process of SAR averaging, the adjustment of the averaging volume constitutes a major computational burden in the method. In the computation of large problems this implies that only the time required for SAR averaging might even surpass that employed in the resolution of the electromagnetic (EM) problem itself. Some of the techniques presented so far overcame this problem by using approximations on the averaging volumes that took advantage of the imprecision of the tissue models. Due to the complexity of the tissue models, the Finite- Difference Time-Domain (FDTD) method has been used to estimate the dissipated EM energy and provide a map of the tissue density necessary for SAR computation. The IEEE standard proposes a cubic region of a specific mass as the averaging volume. This shape can be easily fit in the FDTD grid, simplifying the procedure. The cube fitting has been accelerated by dividing the process in a fast coarse and final fine tuning steps. The algorithm has been applied to realistic scenarios involving the EM exposure of human bodies as the example presented in the figure below, obtaining outstanding improvement with respect to conventional algorithms. The study of the electromagnetic exposure in the human brain tissue requires the identification of functional and anatomical sites in the brain models. For this purpose, a number of different atlases is available. Among these, the stereotactic atlas developed by Talairach and Tournoux has become one of the most popular resources for the identification of the functional brain regions. It is based on a sample brain conveniently segmented and labeled which defines a standard reference for comparison. The identification and labeling of an individual patient data can then be achieved using a coordinate transformation onto the atlas brain space. A tool for the automatic identification and labeling of the brain in human models has been implemented. It detects the brain tissue in the anatomical model and locates nine reference points, denoted as Talairach landmarks, that are used to map the brain data into the atlas normalized space. Three different stereotactic atlases have been generated using a non-uniform segmentation and different accuracy. The identification of these regions enhances the accuracy of the study of the radiation exposure on the brain since any specific information for each functional region can now be extracted from the overall EM simulation results. In particular, the current implementation provides the average dissipated power, minimum/maximum SAR, mass and volume of every region within the 1105 sites located in the model brain. 10g-SAR in an adult male model exposed to a plane wave. Grid resolution 414 x 233 x 1298 ~ 125Mcells. Evaluation time = 8.5 hours (conventional algorithm) and ~3 minutes (this algorithm) on a Dual-Core AMD 2.8 GHz, 8 GB RAM. Identification of Talairach regions in a brain model: (a) Reference landmarks and detected regions at the (b) hemisphere level, (c) lobe level, (d) gyrus level, (e) tissues level and (F) cell level. 92

95 Education Program Student Semester and Master Projects Coordinator: Norbert Felber 93

96 Teaching microelectronics is one of the core activities of the Integrated Systems Laboratory. Shortly after the laboratory was founded in 1986, it started to offer projects in IC design to master students (during the 7th semester of the studies; in the following, the term student is used for students in the Master Course 7th to 10th semester). Probably as the first European university, ETH Zürich financed the fabrication of student chips. This gave students the opportunity to carry out a VLSI design project from the specification to the test of their own silicon chips. Still today, many of the semester projects at IIS are in practical chip design, and many master projects include the realization of integrated circuits or the development of components as contribution to research ASICs. Since the first VLSI course offered by IIS, around 560 engineering students have had the chance of designing real silicon. During times of a prospering market, our students had all the chances of finding jobs in- and outside Switzerland. More important, also during the periodic low-phases of the electronics industry, hardly any student specialized in VLSI had problems to find an adequate job in less than a few months. Although microelectronics companies are rare in Switzerland, many other institutions need knowledge in the design of electronic circuits for their products. Education in Microelectronics During the first four semesters, students are motivated towards microelectronics by several PPS (Practicals, Projects, Seminars) ( In semester 5 and 6, practical training (Fachpraktika, fachpraktika.en.html) offered by IIS aim at the same goal. The three VLSI lectures from the 6th to the 8th semester illustrated in the figure on page 114 and described on pages 116ff form the main block in microelectronics education by the Integrated Systems Laboratory. Students who want to further deepen their experience in microelectronics often choose a master s thesis in the framework of a research project of IIS as culmination of their education. Some then stay in these research fields for a PhD thesis. ASIC Design Projects Students who have decided to realize an integrated circuit will learn a professional design flow with the same tools as used in research and by our main industry partners. They realize an often challenging and complex project. Despite the hard work with many traps and complications, almost all chips finally work as intended. During the 14 weeks of a semester project, the design students put official 50 % of their work load into the realization of the chip, often considerably more. First-time-right digital ICs of industrial complexity level often result:the ones from 2008 are shown on the next page. This is only possible due to the sound VLSI education and an excellent support for design and test offered by the PhD students of our Laboratory and the Microelectronics Design Center of the Department of Information Technology and Electrical Engineering (see pages 124ff and Further Student Projects at IIS Student projects at IIS during the last ten years. The yellow bars indicate the number of students which did a digital VLSI project during the indicated year. The blue bars include also the semester and master projects in the other research groups of IIS. Next to digital ASIC design, students are offered projects in HW and SW system design, as well as in the fields of all other research groups of IIS and IT IS. This regards analog and mixed-signal IC design, TCAD tool development and applications, physical characterization of semiconductor devices, optoelectronics device development and simulation, as well as tool, measurement and experiment contributions in bio-electromagnetics. The graphics above gives an overview over the number of student projects at IIS (blue bars) during the last ten years with emphasis to VLSI student projects (yellow bars). Conference contributions by students from semester and master projects at IIS. Organization of this Chapter In the following pages, student projects are reported in the order mentioned in the paragraph above. A special case are some student projects which are direct and important contributions to research projects. This work is included in the corresponding research sections on pages 37, 38 (left), 39 (right), 41 (left), 42, 43 (right), 45 (right). As a last remark, it is worth to mention the student papers of some of the projects that have been accepted in international conferences and presented by the students as their first contribution to the research community. In the header of the project descriptions, references to the student s publications on pages 129ff are given, and the figure to the left illustrates the growing number of papers with major student contributions. 94

97

98 Ellipitc Curve Cryptography ASIC for Radio Frequency Authentication VLSI Implementation of the Whirlpool Hash Function Daniel Hein; Assistants: Luca Henzen, Matthias Braendli, Norbert Felber; Johannes Wolkerstorfer (TU Graz) Michael Hotz, Fabian Gut; Assistant: Luca Henzen Thesis: Master Thesis Thesis: Semester Project TU Graz Radio Frequency Identification (RFID) technology is currently revolutionizing supply chain management. Cloningresistant RFID tags could put a permanent stop to product piracy. Tag authentication based on Elliptic Curve Cryptography (ECC), a sound and standardized cryptographic methodology, will provide this copy-protection facility. The small key sizes achievable with ECC render it the only public-key cryptosystem viable for an RFID application. This work presents a new approach for ECC on devices with a fiercely constrained die-area and power budget. It employs a data path with a word size of 16 bits. A design-space exploration of word-level algorithms led to the development of a new multiplication with interleaved modular reduction method. Minor modifications to a multiply-accumulate (MAC) unit led to a hardware component capable to implement this and all other algorithms required for the elliptic-curve point multiplication most efficiently. The point multiplication is the operation that lends security to ECC-based cryptographic primitives like authentication. The ECCon ASIC designed and fabricated as part of this thesis is rounded off by an ISO compliant digital RFID frontend augmented with the capability to perform a restricted version of the elliptic curve digital signature algorithm (ECDSA). Special attention was paid to the possibility of side-channel attacks and measures were implemented to provide high resilience against them. The ECCon processor was fabricated using the UMC 180 nm CMOS technology. The area it requires equals to 3,685 gate equivalents. It performs an elliptic curve point multiplication in 306,587 clock cycles and has a power consumption of 11.4 mw at a clock frequency of 106 khz. Cryptographic hash functions are ubiquitous algorithms used in numerous schemes like digital signatures, public-key encryption, or MAC s. Hash functions process an arbitrary-length message to produce a small, fixed-length digital fingerprint. They need to satisfy a variety of security properties (pre-image resistance, collision resistance, pseudo-randomness, etc.). The SHA-2 hash family was added to the National Institute of Standards and Technology (NIST) Federal Information Processing Standard (FIPS) in 2002, in anticipation of the increase in security afforded by the Advanced Encryption Standard (AES) symmetric key algorithm. In February 2003, the Whirlpool hash function was chosen as part of the New European Schemes for Signatures, Integrity and Encryption (NESSIE) initiative, as new advanced cryptographic hash standard. The main goal of this semester project was to find, evaluate, and develop a low-area/low-power implementation of the Whirlpool hash function. Since Whirlpool, like many new hash algorithms, relies on an AES-based structure, the investigation of a compact solution of its computational core becomes of primal interest for resourceconstrained applications. The final lightweight whirlpool design requires only 8.0 kge and consumes 18 mw at 1.8 V and 200 MHz. The maximal achievable throughput is 62 Mbps. Top: Photograph of an RFID tag. Bottom: Chip layout of the ECCon processor. Chip layout with the implemented lightweight hash function cores. The lower whirlpool design contains a scan chain for testability purposes, the upper has none. Both architectures rely on three 512-bit register-file memories. 96

99 Matrix Decomposition Processor for MIMO Communication Systems 8-State Radix-4 M-BCJR Decoder Richard Emler, Giselher Wichmann; Assistants: Christian Senning, Patrick Mächler, Christoph Studer, Stefan Eberli Sandro Belfanti, Simon Schläpfer; Assistants: Christoph Studer, Christian Benkeser Thesis: Semester Project Thesis: Semester Project Celestrius, KTI Receivers for multiple-input multiple-output wireless communication systems can be designed using different matrix decomposition algorithms. Some of them have been implemented with processor-like architectures controlled by hard-coded finite state machines (FSM). For example, the QR-decomposition and the SVD could be realized with similar architectures and similar computational blocks, but different hard-coded FSMs. The aim of this project was to implement a processor being able to perform virtually all matrix decomposition algorithms on the same hardware. Hence, all operations required to efficiently calculate the desired matrix decompositions have been identified. Then, a processor with a master-slave CORDIC, extended by an angular unit, a complex-valued multiply-accumulate unit (CMAC), and a general-purpose arithmetic logic unit (ALU) has been implemented. All these computational units are controlled by a programmable state machine. This approach grants high flexibility. It can be used as a reference design for future implementations of dedicated matrix decomposition algorithms. The matrix decomposition processor has been implemented in 180 nm CMOS technology. The gate count is 75 kge, approximately 70 percent larger than a dedicated SVD core. The maximal clock frequency is 100 MHz. Turbo codes are used in various communication standards due to their excellent error-rate performance. One of the throughput bottlenecks of turbo decoders is the M- BCJR algorithm, which forms the core processing unit. In this project, an 8-state radix-2 max-log M-BCJR architecture designed in a previous semester project has been optimized for high throughput. A radix-4 architecture has been chosen which processes two data items in one clock cycle (compared to one data item in one clock cycle for a corresponding radix-2 architecture). Additionally, all memories have been realized as arrays of latches, which has the benefit of a lower circuit area (compared to SRAM macro-cells), while not limiting the maximum clock frequency. The resulting throughput-optimized 8-state radix-4 maxlog M-BCJR decoder has been implemented in 180 nm 1P/6M CMOS technology. It achieves a sustained decoding throughput of 700 Mbits/s at 350 MHz. The radix-4 M- BCJR implementation requires a circuit area of 0.79 mm 2. Compared to the reference radix-2 M-BCJR implementation (area 0.36 mm 2 at 375 MHz), the radix-4 implementation has shown to be slightly less efficient in terms of area per throughput, but achieves twice the throughput of the reference implementation at the same clock frequency. ASIC layout of the matrix decomposition processor implemented in 180 nm CMOS technology. 8-state radix-4 max-log M-BCJR layout in 180 nm 1P/6M CMOS technology. The SRAM macro-cell in the lower left is required for testing purposes only. 97

100 Virtual Component for the Division Operation PCP - Pulse-Control Processor for Qubit Manipulation Victoria Goode; Assistants: Hubert Kaeslin; Reto Zimmermann (Synopsys) Claudio Botta, Andreas Müller; Assistants: Markus Wenk, Felix Bürgin; Martin Göppl (SOLID-ETHZ) Thesis: Master Thesis Thesis: Semester Project Synopsys SOLID-ETHZ The aim of this project was to provide a reusable building block for fixed-point division. Following a study of many diverse divider concepts known from the literature, three architectures have been investigated in greater detail, namely nonrestoring division, radix-2 SRT, and radix-4 SRT. While standard sequential division computes just one quotient bit per clock cycle, the SRT algorithm can be made to compute two bits in a single cycle, in which case one speaks of a radix-4 division. For each of the above concepts, a VHDL model has been established, debugged, and synthesized for various quotient widths. Evaluation was based on the area and delay data estimated from pre-layout netlists for a 180 nm CMOS process under worst-case conditions. Data include both the constant-selection logic and the final correction stage mandated by radix-4 SRT division, but not present in competing architectures. The fact that a radix-4 SRT architecture results in significantly longer signal propagation paths, but takes only half as many clock cycles, has also been factored in. Results are summarized in the graph below, where a commercial component of undisclosed nature has been included for reference. Among the original three alternatives, nonrestoring division occupies the largest area for only very minor speed gains, and this only at word widths of 32 bits or less. Synthesis of the SRT-4 code was found to consistently produce the smallest circuit with no speedwise benefit over SRT-2. Overall, the commercial divider is almost always the preferred choice except in terms of area occupation from 40 bit upwards, where the radix-4 SRT yields an alternative Pareto-optimal solution. The Quantum Device Lab at the physics department of ETHZ investigates quantum properties of novel microand nano-structured electronic devices and their interaction with classical and quantum electromagnetic fields. To study and manipulate so-called quantum bits (Qubits), the generation of fast pulse sequences is necessary, which are currently generated by an arbitrary waveform generator (AWG). The goal of this project was to replace the AWG by a programmable pulse-control processor ASIC. The pulse-control processor architecture contains an instruction memory, the pulse-control processor (PCP) itself, and a pulse-control arithmetic unit. The computation of the arbitrary waveforms is based on the method of finite differences and is carried out by the pulse-control arithmetic unit. The instruction set of the PCP developed during this thesis consists of 13 specific 16 bit instruction words that allow to generate any required waveform. The realized ASIC contains two PCP cores and was designed to achieve a maximum clock frequency of 300 MHz. The silicon area occupied by the two cores is 0.74 mm 2. The latency is three clock cycles. One core has 8 MByte instruction memory, while the other core is equipped with 4 MByte instruction memory. The ASIC was manufactured in UMC 180 nm CMOS technology. Four architectures for fixed-point division compared for quotients of 16, 24, 32, 40, 52, and 64 bits respectively. The pulse-control processor ASIC produces arbitrary waveforms for the manipulation of so-called quantum bits. 98

101 High-Definition Audio Interface for Digital Audio Systems Virtual Analog Synthesizer: Digital Implementation of an Analog Synthesizer Simon Umbricht, Christoph Keller; Assistants: Norbert Felber, Felix Bürgin, Matthias Brändli; Thierry Heeb, Eduard Kohler (Anagram) Simon Hügi, Ragesh Nair; Assistants: Norbert Felber; Andreas Looser (chip design student) Thesis: Semester Project Thesis: Semester Project Anagram Technologies Intel s High-Definition Audio (HDA) standard supports the exchange of multi-channel high-resolution audio signals. Up to 16 channels with up to 32 bits per sample at 192 khz sampling rate can be handled. Independent of the signal s sampling rate, the HDA interface uses a 24 MHz bit clock for the frame-oriented data transfer. The sampling frequency for the conversion to the analog world therefore requires special reconstruction methods. The aim of this semester project was an ASIC prototype which demonstrates an 8-channel HDA interface that adapts the data streams and clock rates to digital-to-analog converters on the same chip. The task for the students was the design of the HDA interface. Beside the interface control and audio stream management, the sample clock needs to be regenerated to the precise conversion frequency. By only using digital standardcells, for nonrational clock frequencies this can only be achieved by introducing jitter. One task was to minimize this jitter as much as possible. The sample-rate converter (SRC)-based digital-to-analog converters were provided by Anagram as virtual components (VHDL code). The students implemented the whole system on the chip. Six channels could be placed on the restricted silicon size available to student projects. Tests of the system proved that the converter s quality could be sustained through the HDA interface. In a former student IC design project, a digital ASIC has been developed which imitates famous analog music synthesizers as Moog or Sequential Prophet-10. These machines consist of a multitude of analog components that can be interconnected to realize an almost infinite variety of different systems. The main components are voltage-controlled oscillators (VCO), voltage-controlled filters (VCF), and voltage-controlled amplifiers (VCA). The VCOs are controlled to generate the frequency of the note including strong harmonics. Therefor, pulse trains, triangular or saw-tooth waves are made available. The VCFs then form the harmonic spectral behavior while VCAs in conjunction with envelope generators start and end the tone comparable to musical instruments. The goal of this semester project was the design of the synthesizer system, consisting of eight synthesizer ASICS. The FPGA on the developed PCB provides an interface to a DSP board with analog and digital audio ports. It collects the serial audio signals from the ASICs into a time-domain multiplexed stream. Furthermore, it provides access to the registers of the synthesizer ASICs. Microphotograph of the high-definition audio interface ASIC. The CMOS 180 nm chip has a total size of 2.5 mm by 2.5 mm (including the padframe). Detail of the PCB board design with overlaid chip microphotographs (not to scale, for illustration only). At the bottom left, the footprint for the FPGA can be identified. 99

102 Modular Hardware Platform for IEEE n Transceiver Robust Data Embedding in Audio Marco von Arb; Assistants: Daniel Baum (IKT-ETHZ); Andreas Burg Tobias Grämer, Raphael Rolny; Assistants: Christoph Studer, Felix Bürgin Thesis: Master Thesis Thesis: Semester Project IKT-ETHZ, Celestrius An IEEE n wireless LAN transceiver is composed of a radio-frequency (RF) subsystem, the high-performance digital signal processing at the physical layer (PHY), and the medium access control (MAC) layer. A prototype ASIC (CLSN601P) for a 4-stream IEEE n PHY layer has been developed in a research project between ETHZ and Celestrius AG. The goal of this thesis was to develop a testbed infrastructure that serves as a basis for the development of the MAC on an FPGA, for the real-time demonstration of the CLSN601P, and for the verification and interoperability testing of the complete system. The basic idea behind the developed testbed architecture is to allow connectivity between two terminals on all layers in order to verify the individual system components independently. To this end, the hardware is composed of four main components: A commercial FPGA board with PCIe interface serves as the basis for the development of the MAC. An ASIC carrier board carries the CLSN601P PHY layer ASIC. A custom FPGA board with a XILINX Spartan FPGA provides a flexible interface between the CLSN601P and the RF subsystem. The latter can be realized for example by using the RF components (wing boards) of the ETHZ realtime MIMO testbed. In 2006, a research group of the Japanese mobile operator NTT DOCOMO presented an OFDM-based method to embed and broadcast digital data in audio streams. The main motivation of such a data-broadcast system is, that the required infrastructure is already available: Transmitters (i.e., loudspeakers) are installed almost everywhere, e.g. in shops, restaurants, etc. Receivers (i.e. microphones) are present in every mobile phone. The goal of this project was to design an acoustic data broadcast system based on dirty-paper coding (DPC) instead of using OFDM or direct-sequence spread spectrum (DSSS). In theory, DPC offers the key advantage that the channel capacity is not degraded (compared to an AWGN channel) in the presence of a known interferer, e.g., music radiated by the loudspeakers in this setup. However, DPC poses significant challenges in practice. Acoustic channels suffer from fading and inter-symbol interference (ISI). Additionally, no channel-state information is available at the transmitter as the considered wireless link is unidirectional. To this end, a novel approach has been developed to combat fading without channel knowledge in the transmitter. In the presence of ISI, however, DPC-based data broadcasting was shown to fail, and hence, other techniques, such as DSSS or OFDM, need to be considered instead. Illustration of the system components and the system-verification concept for an IEEE n transceiver. The ASIC carrier and the RF interface boards were both realized in this project. Top right: Error-rate performance advantage of dirty-paper coding (DPC) compared to direct-sequence spread spectrum (DSSS) in an AWGN system without ISI. Bottom: Illustration of the acoustic broadcast system. 100

103 FPGA - ASIC Prototyping System Meteo Station on Spartacus Pascal Gubler: Assistants: Markus Wenk, Peter Lüthi Georg Oberholzer; Assistants: Markus Wenk, Christian Senning, Thomas Koch Thesis: Semester Project Thesis: Semester Project Every year, various interesting application-specific integrated circuits (ASIC) are designed, integrated, and tested at the Integrated Systems Laboratory. However, only rarely, they make it into a nice demonstration or a real-world application. The goal of this semester thesis was to develop a hardware platform that allows easy interfacing to an ASIC in order to provide a convenient possibility to demonstrate its functionality. To this end, an existing FPGA board is chosen as basis and an ASIC adapter board has been realized that can be stacked onto the FPGA board. The FPGA provides the required logic and storage capabilities for the ASIC interface, as well as a computer interface for control possibilities. The ASIC adapter board contains the pad- and core-power supplies for the ASIC, a socket for the standard ASIC package (CLCC-84), and IO connections to the FPGA for each data pin of the ASIC. The second part of the semester thesis was to establish the operation to demonstrate a recently developed ASIC. This included the design of a VHDL wrapper in the FPGA to interface the ASIC and of a data connection to a computer. In the final demonstration, generic stimulus data were generated in Matlab on a computer, written over the USB interface to the FPGA, and applied to the ASIC. The responses from the ASIC were recorded on the FPGA and read back into Matlab. The Spartacus board is a small general-purpose FPGA board containing a XILINX Spartan 3E500 FPGA, a USB interface, SRAM memory, buttons and LEDs, and IO connectors for various adapter boards. The main goal of this semester thesis was to create a meteo extension board and to make the entire platform ready to become part of a PPS lecture for second-semester students. The goal of this semester project was a meteorologic extension board that contains an on-board temperature sensor and an interface to an external temperature sensor, a pressure sensor, and a humidity sensor. Furthermore, an interface to a DCF-77 module to obtain the current time of day and an EEPROM to store extremal values are included. Last but not least, an integrated acceleration sensor on the board enables seismic measurements. The implemented application acquires the data from the meteo sensors and stores them in a buffer on the FPGA. Most sensors can be addressed over the well-known SPI interface. A visualization unit is responsible to extract the measured data from the buffer and to present the results over the VGA adapter board on a display. Realized ASIC adapter board with dedicated power supply. It is stacked onto the FPGA base board. The Spartacus board with the meteo and the VGA adapter boards attached. 101

104 Real-Time Compression of 3D Structures in FPGA FIR Filter Design Support for Signal Processing in FPGAs Pascal Gubler; Assistants: Norbert Felber; Markus Berner (MHT Optic) Andrin Maggi; Assistants: Norbert Felber; Martin Heimlicher (Enclustra) Thesis: Master Thesis Thesis: Semester Project MHT Optic Enclustra MHT Optic Research AG is developing a new high-resolution 3D scanner for dental-medical purposes. It is based on confocal microscopy combined with low-coherence tomography. For the high data rate, the USB data connection is the bottle neck of performance. In order to use the full potential of the 3D scanning device, the acquired signal needs to be compressed. The approach taken during this master thesis adapts known data compression methods to the specific 3D data acquired by the scanner. Several algorithms, such as Run Length Encoding (RLE), Silence Compression, and JPEG/ MPEG have been tested and evaluated with MATLAB. It turned out that Silence Compression combined with RLE and surface pre-detection provides the best result concerning performance and reliability. In order to verify the feasibility, the algorithm was implemented on a Xilinx 3S1000 FPGA. The solution includes the necessary data preprocessing stage with offset compensation and rotation of the data in the memory prior to the actual data compression algorithm. FIR filters are important building blocks in digital signal processing. Due to their (possible) phase linearity, regular structure, and low design effort, this type of filter is often used. Opposed to IIR filters, FIR versions most often require high filter orders and therefore a huge number of multiplications per processed sample. Current FPGAs offer a multitude of efficient built-in multipliers. A certain task can be implemented in a large variety of architectures, reaching from processor-like structures with a single multiplier to isomorphic solutions with one multiplier per filter order. The storage of the state variables poses a comparable problem: Flipflops provide high speed, RAMs save a lot of silicon area. The aim of this semester project was to realize a design framework which supports circuit designers by providing proposals for FIR filter architectures. Depending on the filter specifications and the requirements of the other circuits on the FPGA, i.e., the remaining resources, the framework helps to find optimal implementations for the FIR filter. It considers DSP units and memory blocks of XILINX Virtex FPGAs, derives sufficient word lengths, and optimizes the filter architecture for size and power. 3D scanner system by MHT Optic Research AG for measuring teeth. FPGA real-time support has been developed in this master thesis. Illustration of the FIR filter design framework which proposes optimal structures for implementation in FPGAs under given specifications and available resources. 102

105 Digital Audio Algorithms for Reconfigurable Processor Analysis and Design of GSM/EDGE Receivers Jürg Schellenberg; Assistants: Norbert Felber; Matthias Tramm (BridgeCo) Andreas Bubenhofer; Assistants: Christian Benkeser, Andreas Burg Thesis: Semester Project Thesis: Master Thesis BridgeCo Equalizing can be used to enhance non-ideal frequency responses of multi-media systems. For example, to compensate loudspeaker responses, the filter parameters can be determined off-line. Pre-selectable equalizer modes for special sound characteristics are another example. For this kind of effects, the student has developed optimized code for a given reconfigurable signal processor. This reconfigurable signal processor has earlier been developed by a partner company in collaboration with the Integrated Systems Laboratory for other multimedia applications. The main task of the project was to reach the specified quality by using the hardware resources available in the reconfigurable signal processor, which were optimized for other applications than sound processing. The given word widths of the arithmetic blocks led to inacceptable signal-to-noise ratios. A correction method has been introduced to enhance the quality without the need of too many resources. The implementation enables 2-channel equalizing with five second-order corrections per channel. The 16-bit input audio quality is roughly sustained through the equalizer. Bit-true C and Matlab models have been realized both for the development of the equalizer on the reconfigurable signal processor and to support the evaluation of new applications. EDGE and EDGE-Evolution as the latest TDMA based communication standards offer a simple solution to increase the spectral efficiency of GSM mobile communication systems. These standards offer sufficient performance for most mobile applications and the benefit of reusing the existing hardware for mobile operators. This can be interesting for rural areas and developing countries, where large cell areas and low infrastructure costs are demanded by the communication services companies. In this master thesis, a simulation framework of a baseband receiver has been implemented. Different channelequalizer solutions have been evaluated, compared and simulated. The cellular standard GSM with all extensions GPRS, EDGE and Evolved-EDGE for higher data rates including 22 channel decoder schemes and 4 different modulation types (GMSK, 8PSK, 16QAM, 32QAM) is supported by the final solution. Finally, two complete receiver ASIC models have been designed for comparing different solutions in CMOS hardware implementations in terms of power and speed. The multitude of operating modes requires flexible hardware design at little overhead to keep the power consumption and cost low. The parametric equalizer implemented on a reconfigurable signal processor (block diagram) enables frequency responses (blue) to be corrected (green) in order to optimize the overall result (red). The latest GSM standard extensions EDGE and Evolved- EDGE for high data rates comprise many operating modes with different modulation orders, each with a specific tradeoff between transmission speed and reliability. 103

106 Turbo Equalization for GSM/EDGE Implementation of Receiver for GSM/EDGE Claudio Foelmli; Assistants: Christian Benkeser, Andreas Burg Christina Hediger, Matthias Vetter; Assistants: Christian Benkeser, Andreas Burg Thesis: Master Thesis Thesis: Semester Project EDGE is an extension to the cellular standard GSM. It was introduced in 1999 and allows up to three times higher data rates than GSM. Due to the introduction of 8-PSK modulation in the GSM/EDGE standard, the channel equalizer used in GSM systems becomes too complex for hardware implementation, hence new equalization strategies are required. This master thesis dealt with the design and the hardware implementation of a Turbo Equalizer for the cellular standard EDGE. A simulation environment comprising the baseband transmitter part, the cellular channel and the baseband receiver part has been implemented and applied for simulations. In these simulations, architecture alternatives like different channel decoders, channel estimators and channel equalizers were compared and verified against each other. The results have been used for implementing a cellular baseband receiver chip with Turbo Equalization for EDGE. This ASIC hardware implementation has been realized in cooperation with the semester thesis reported in the contribution to the right. This semester thesis dealt with the ASIC implementation of a baseband receiver for the cellular standard EDGE. The simulation results of the master thesis of Claudio Foelmli have been used for finding a fixed-point model, which shows a good trade-off between demodulation performance and hardware complexity. The channel equalizer in the design uses the concept of linear equalization operating in the frequency domain for reducing the hardware implementation complexity. An efficient realization of this frequency domain equalizer (FDE) has been implemented together with an 8-PSK demodulator. Furthermore, solutions for the burst demapper, de-interleaver and channel decoder have been found, supporting several operating modes as specified for EDGE. A major difficulty in this project was the efficient implementation of flexible design blocks, which enable the receiver to support several operating modes with different transmission block sizes, puncturing rates, and interleaving patterns as specified for EDGE. With three system clocks running on different frequencies and 15 RAM macro blocks, the backend design has been another complex task in this VLSI semester project. The final ASIC design has been verified and tested on the digital tester of the institute. The upper part of the image shows the implemented simulation framework. A block diagram of the realized turbo equalizer is shown in the lower part of the image. It illustrates its iterative working principle. ASIC layout of the implemented baseband receiver for the EDGE cellular standard including the channel estimator, channel equalizer, de-interleaver, and channel decoder. 104

107 Design of a Multi-Band CMOS RF Receiver Frontend for Mobile WiMAX Frontend Topologies for Low-Power Wireless Receivers in CMOS Dan Liu; Assistants: Thomas Dellsperger, Yangjian Chen Boming Jin; Assistants: Thomas Dellsperger, Thomas Burger Thesis: Semester Project Thesis: Semester Project Mobile WiMAX is a relatively new standard based on the IEEE family of Wireless Metropolitan Area Network (WMAN) standards. It is data-centric and aims at mobile applications. Mobile WiMAX fills the gap between low-mobility data-centric standards such as WLAN and high-mobility voice-centric standards such as GSM. It will operate in the GHz and GHz frequency range, necessitating multi-band transceivers. In this project, a multi-band RF receiver frontend covering the relevant bands has been designed on schematic level in 130 nm CMOS technology. Two broadband LNA topologies have been investigated. Both topologies are based on a common-source input stage and exploit the Miller effect to achieve a broadband match. The first topology forms an equivalent 3 rd -order Chebychev band pass filter at its input, and the second one uses the Miller effect to generate an equivalent 50 W series resistance at its input. For the implementation of the RF receiver frontend, the second LNA topology has been chosen for its higher gain and lower noise figure. Besides the LNA, the pros and cons of a single-balanced passive mixer have been explored. A current-mode logic (CML) I/Q divider was designed to drive the mixer. The simulated performance of the RF receiver frontend yields: voltage gain > 24 db, noise figure < 2 db, input compression point > -27 dbm, and input 3 rd -order intercept point (iip3) > -16 dbm. The current consumption from a 1.2 V supply was simulated to be 13 ma. The direct conversion receiver (DCR) principle provides a suitable architecture to meet the needs of softwaredefined radio. A DCR essentially consists of a low-noise amplifier (LNA), a down-conversion mixer, and a baseband filter. The goal of this project was to evaluate promising DCR topologies, with focus on the down-conversion mixer and its interface to the LNA and BB filter. The use of a passive mixer instead of an active mixer is a promising approach to reduce flicker noise at base band, which is a major drawback of the DCR. Two different single-balanced passive mixing concepts were explored: the current-switching mixer (CSM), which switches the input AC current between a positive and negative branch, and the voltage-switching mixer (VSM), which works in the voltage domain and stores the input AC voltage by means of a track-and-hold process alternately on a capacitive positive and a capacitive negative node. After a set of improvements, modifications, and tradeoffs, the results of this project show that both variants can achieve good performance while the CSM is the circuit with less complexity, area, and power consumption. The VSM remains conceptually interesting with some useful properties like a positive conversion gain of up to 6 db. Schematic of the 2 nd investigated LNA for a Mobile WiMAX receiver frontend. Switching gain vs. duty cycle D for the current-switching mixer (CSM, above) and the voltage-switching mixer (VSM, below). 105

108 Multi-Bit Sigma-Delta DAC for WLAN Applications Discrete Distribution of Doping Atoms in 3D Devices Anh Tung Tran; Assistants: Craig Keogh, Thomas Christen Jan Müller; Assistants: Simon Brugger, Andreas Schenk Thesis: Master Thesis Thesis: Semester Project The digital-to-analog converter (DAC) is a crucial building-block in modern radio frequency (RF) systems. Traditionally, high-performance DACs have been almost exclusively implemented using current-steering (CS) architectures. However the CS approach has the disdvantage that glitches arising from the switching of current sources can distort the output and hence reduce the conversion accuracy. On account of noise-shaping, sigma-delta (SD) techniques require fewer elements to achieve the same in-band performance and often have superior linearity performance than the CS approach. Historically, SD converters have relied on the use of a high oversampling ratio (OSR) in conjunction with an inherently linear, single DAC element to achieve high-resolution data conversion. Due to the larger bandwidth requirements at radio frequencies, the use of a high OSR in RF applications is not feasible. To cope with this constraint, without unduly sacrificing performance, it is often necessary to utilize a multi-bit DAC. This project investigates the use of the SD conversion technique in realising a DAC for Wireless LAN applications. To this end, a switched-capacitor, multi-bit, SD DAC has been designed using a 1.2 V CMOS 130 nm technology. The SD DAC processes signals within a 10 MHz bandwidth and operates at a clock frequency of 160 MHz. A 2nd-order, error-feedback topology with 32 quantization levels has been selected for the all-digital SD modulator. Simulation results indicate that the design achieves a maximum dynamic range of 62.5 db with a corresponding power consumption of approximately 20 mw. According to Moor s Law, the number of transistors that can be placed on an integrated circuit is doubling approximately every two years. To compete with this tendency, today s electronic devices have to get smaller at a comparable rate. The industry faces new problems when it comes to the simulation of such small devices. Even for undoped MOSFET channels, a few doping atoms from the highly doped source and drain regions can diffuse into the critical region and considerably change the performance of the device. The intention of this work has been to extend the in-house Monte Carlo simulator SimnIC with the ability to simulate an electronic device with assumed discrete distributions of doping atoms. The latter should be randomly distributed over the device according to the doping concentration. To increase the simulation accuracy, the mesh around a doping atom must be refined. Efficient refinement strategies were developed. Finally, the new implemented discrete method was used to simulate deca-nanometer devices and to compare the results with those for homogeneously doped devices. (a) Circuit of the analog part of the SD DAC. (b) Output of DAC in the time-domain (with a 9.3 MHz sinusoidal input). (c) Plot of the output in the frequency domain. Top: Mesh refinement around discrete doping atoms. Bottom: Mobility simulations of discretely and homogeneously doped resistors with different doping levels. 106

109 CNT-FET Simulator: A Green s Function Simulator for Nanoscopic CNT-based Strain Sensors Coupling the Monte-Carlo Method with Semi-Analytical Solutions of the Boltzmann Transport Equation Nils Ketter; Assistants: Andreas Schenk, Mathieu Luisier Vincent Peikert; Assistants: Simon Brugger, Andreas Schenk Thesis: Master Thesis Thesis: Master Thesis MAVT-ETHZ (Cosmin Roman) References: [T2] In this thesis, a novel modeling method for Carbon Nano Tube (CNT) based FETs has been developed. It is based on the Non-equilibrium Green s Function (NEGF) approach with complex contour integration to rigorously calculate the electron density within the device. Starting from commonly used methods referred to as point-charge model, the validity of the intrinsic Fermi-level assumption was investigated which does not hold at the CNT-metal interfaces. A more rigorous charge integration technique, called orbital-charge model was put forward. However, the new charge density lead to diverging potentials close to the interfaces. An original new way of calculating the Hartree potential was developed with an accuracy exceeding the previous one by far. The two new approaches were finally integrated into the self-consistent cycle using mixing and predictor-corrector strategies. Results of the new model were compared with state-of-the-art results and significant differences were found. The Current-Based one-particle Monte Carlo (CBOPMC) approach is a statistical method for solving the Boltzmann transport equation (BTE) in condensed matter. The basis for this method is a recent theory about exact moments of the inverse scattering operator (MISO) which was developed at IIS. One of the many advantages of the CBOPMC is that MC-extracted transport parameters can be selectively replaced by models. This hybrid method utilizes the latter fact: it applies a newly deduced semi-analytical series in the areas of convergence and reduces the time-consuming MC simulation to some essential regions. The new series emerges by simply inverting the BTE and rearranging the terms without further assumptions. It turns out that the influences of higher order derivatives (of the electric potential and the quasi Fermi potential) on transport parameters are not negligible. To avoid statistical bottlenecks, a statistical enhancement method is upgraded and a new convergence criterion is suggested. Top left: Scheme of the strain sensor. Upper right: Part of the generated mesh for a given CNT-FET with sidegate. Bottom: Comparison of output characteristics. Top: Analytical corrections to the equilibrium transport parameters. Middle: The analytical solution converges in the red regions. Bottom: Simulated N+NN+ device. 107

110 Simulation of InGaN / GaN Nano-LEDs Ab-Initio Simulations for Constructing Envelope Theories in Nanostructures Christoph Boecklin; Assistants: Ratko Veprek, Sebastian Steiger Reto Rhyner; Assistants: Sebastian Steiger Ratko Veprek Thesis: Master Thesis Thesis: Master Thesis References: Phys.Rev. B 76, / (2007) Recent advances in device fabrication allow the growth of novel nanocolumnar LEDs. Due to the finite lateral extension, such nanocolumns are almost defect-free. GaN nanocolumns with InGaN active layers may therefore serve as the basis for the realization of highly efficient, energy-saving white LEDs. The finite lateral size allows to relax the lattice-mismatchinduced strain within the active layer, resulting in an inhomogeneous strain distribution. As a consequence of the polar nature of the III-nitride semiconductors, inhomogeneous polarization charges result. Hence, a fully coupled, three dimensional simulation including strain, carrier transport, polarization charges and quantum confinement is required to understand the physical behavior of such devices. Therefor, the recently developed simulation framework AQUA/tdkp has been applied to nanocolumns, to first study the carrier confinement caused by the inhomogeneous strain distribution and the polarization charge. Then, using AQUA s coupled 3D and 2D carrier transport model, the lateral carrier transport, polarization charge screening and inhomogeneous carrier transport have been analyzed in such devices. k p envelope Hamiltonians are the most commonly used band structure models in the numerical simulation of optoelectronic devices. However, their parameters need to be determined from more fundamental, atomistic methods. Furthermore, the validity of the envelope approach near heterointerfaces is a matter of ongoing dispute. Recently, Foreman (see reference) made an effort to investigate these issues by deducing the effective mass parameters from an atomistic calculation using the program ABINIT. He then showed how the correct operator ordering is retained, and investigated the validity of certain approximations. The aim of this project was to reproduce Foreman s work and then propose ways to construct numerically feasible nonstandard k p zincblende Hamiltonians with improved accuracy and correct operator ordering. The atomistic simulations could be successfully reproduced and the atomically resolved potential and density is in agreement with published results. Subsequently a multipole expansion of these results was carried out and effective mass parameters were extracted using polynomial fitting in k-space of the Hamiltonian in a basis of 300 plane waves. The work has laid the foundation for further investigations. It now needs to be extended by verifying the fitting parameters and Löwdin renormalization to n bands. Probability distribution of an electron state in the InGaN active layer of a GaN nanocolumn. Due to the inhomogeneous strain distribution and the piezo-electric field, the electron is localized towards the boundary. Approximation of the Fourier-transformed atomic density using a fourth-order multipole expansion around each reciprocal lattice vector. 108

111 Nitride-Based Back Contacts for CIGS Solar Cells Noise in Avalanche Photodiodes Patrick Bloesch; Assistants: Sebastian Steiger, Ratko Veprek; Dominik Guettler, Ayodhya Tiwari (SOLID-ETHZ) Emre Ilguensatiroglu; Assistants: Hektor Meier, Friedhard Römer Thesis: Master Thesis Thesis: Semester Project Flisom (David Brémaud) BCI (H. Zimmermann) Thin film solar cells, such as the popular poly-crystalline Cu(In,Ga)Se 2 (CIGS) cells, are on the rise due to improved efficiency and less material requirements. The electrical back contact thereby plays an important role in the longterm stability. Conventional Mo back contacts have the disadvantage of being relatively expensive, not stable against moisture, and not acting as an impurity barrier. The aim of the present project was to experimentally investigate whether using nitride as a substitute can yield an improvement. Of crucial importance to the device performance are the electrical resistivity of the device, the film density, the surface roughness, the optical reflectivity, and the induced mechanical stress. Applied experimental techniques include electrical characterization, SEM imaging of the layer structure, AFM imaging of the surface roughness, and light microscopy for the observation of cracks and stress. The quality of the cell naturally varies with the process parameters, and a trade-off exists between cost and quality. Some decisive parameters include the substrate temperature, the partial pressure of the Ar gas in the growth chamber, the cathode power, and the substrate bias. Variations were investigated with respect to all these parameters. Furthermore, different substrates (glass, steel foil and polymide foils with different thickness) were used. The dependence of the overall cell performance on the choice of substrate turned out to be relatively large. Modern avalanche photodiodes (APDs) are used in optical receiver circuits for fiber-optical networks. APDs provide an internal signal amplification by avalanche multiplication of photon-generated carriers. Unfortunately, this amplification is not noise-free. The randomness of the impact ionization process causes an additional noise term, the excess noise factor. The goal of this semester thesis project was to measure the excess noise factor in state-of-the-art APDs. The excess noise factor depends, among other things, on the DC gain, the material composition, and the device geometry, due to the non-local nature of the impact ionization process. First, a literature study has been performed to understand the underlying mechanism of APDs and excess noise. Then, state-of-the-art APDs have been characterized in the Optolab. This included the measurement of dark- and photo-current, DC gain, bandwidth, and the calibration of the high-frequency measurement setup on the wafer prober. Finally, the excess noise factor has been calculated for various gains based on the measurements of the spectral noise density. Using local impact ionization theory, the ratio of electron and hole impact-ionization rate has been estimated. Furthermore, LABVIEW routines have been implemented to automate the measurement setup. Scanning Electron Microscope (SEM) cross-section image of a CIGS solar sell with Ti/TiN back contact, together with a fully processed sample. Schematic representation of the excess noise measurement setup. 109

112 Simulation of Plasmonic Waveguides with the Finite Element Method Finite Element Simulation of the Bimetallic Effect in Power Modules Eugen Zgraggen; Assistants: Friedhard Römer, Jan Kupec Ugo Pelosi; Asssitant: Mauro Ciappa Thesis: Semester Project Thesis: Master Thesis Uni Cagliari Plasmonic waveguides can be used to direct light through structures that are small compared to the wavelength. This property can lead to new applications, such as optical signal processing and integrated optical circuits. In contrast to a dielectric waveguide, the electromagnetic power is carried along an interface between a metal and a dielectric. At optical frequencies, the conductivity of the metal surface is determined by surface plasmons and the resulting attenuation is significant. Therefore, the design of the waveguide has to minimize the confinement of the guided wave in the metal in order to avoid loss, while constraining a large fraction of the electromagnetic power flux to the proximity of the interface in order to keep the dimensions of the waveguide compact. A distinct challenge of the present problem lies in the modeling of the sharp dielectric contrast at the interface. The accuracy of the finite-element calculation of these high-contrast structures was verified with respect to semianalytical solutions. The numerical simulations were performed with the 2.5 D vectorial waveguide solver, which is a part of the package LUMI3, that was developed in previous projects. It was shown that the method employed is suitable for the calculation of propagation modes for all geometries of relevance. At relative errors of less than 1 %, the computational demand was still low. All significant eigensolutions were observed in the numerical simulation. The traditional power module architecture is defined by a multilayered structure consisting basically of a solid base plate (either in Copper or AlSiC) and of an insulated ceramic substrate (direct bonded ceramic). Usually, modules are mounted on a heat sink by bolts with given pretensioning. Recently, new module designs have been proposed to reduce, among other, the thermal resistance, and to prevent the solder fatigue failure in the substrate solder. This is the case of assemblies that do not make use of the base plate and, which are fixed on the top of the heat sink by spring-loaded contacts. During thermal and power cycles, power modules are warped due to the bimetallic effect. The periodic deformation leads to the modulation of the gap between the base plate and the heat. This has an impact both on the cooling characteristics and on the reliability of the modules. The scope of this Master thesis was to calculate the dependency of the gap shape on the instantaneous power dissipated by the active devices in traditional and baseplate-less modules. The work has been carried out by three-dimensional thermo-mechanical simulations performed by Ansys Workbench The simulation models were developed to take into account the main mechanical and thermal peculiarities of the system, including in particular the initial stresses due to the assembly process. Suitable meshing strategies have been used for fast convergency and accurate calculation of the temperature field, as well as of the deformation. Finally, efficient models for the pretensioning of the bolts have been developed in the case of traditional modules, by leading to an original approach to couple the thermal and the mechanical problem. Dispersion relation of a plasmonic waveguide. The numerical solution is illustrated in color, the semi-analytical solution in black. Deformation during a passive thermal cycle of an IGBT module mounted on an aluminum heat sink at the top end temperature of 125 C. 110

113 PhD Theses Abstracts Low Power Circuit Architectures and Clocking Strategies for Digital Hearing Aids Felix Bürgin This thesis aims at evaluating different low-power VLSI circuit design techniques that are especially suited for low-frequency audio applications, such as hearing aids. Thereby, several circuit architectures are compared for different levels of resource sharing, number formats, and clocking strategies in established VLSI technologies (minimum transistor lengths of 0.25 μm and 0.18 μm). Additionally, cell redesign for reduced gate capacitance and hence lower dynamic power consumption is investigated. All these techniques have been verified by simulations and measurements of several state-of-the-art hearing aid signal processing algorithms that have been implemented and integrated on silicon. Prof. Dr. W. Fichtner, ETH Zürich, examiner Dr. Paul Zbinden, Phonak AG, co-examiner Diss. ETH-Nr ISBN Theory and Design of Broadband Active Optoelectronic Devices Martin Loeser This Ph.D. thesis is divided into two parts. In the first chapters a broadband optical model for optoelectronic devices is derived and implemented into an existing device simulator. This novel model is then employed for two- and three-dimensional electro-opto-thermal simulations of various super-luminescent LEDs. After a calibration step measured and simulated emission characteristics agree very well for different device designs. In the last chapters of this thesis the Ultra-Weak Variational Formulation is shown to be an efficient approach to numerically analyze the radiation characteristics of optically large structures. It is illustrated how information reduction techniques can be applied to significantly reduce the computational cost without affecting the accuracy of the solution. Prof. Dr. W. Fichtner, ETH Zürich, examiner Prof. Dr. H. Jäckel, ETH Zürich, co-examinerr Diss. ETH-Nr ISBN not yet known A Power Efficient Linear Multi-Mode CMOS Radio Transmitter Dimitris Papadopoulos In order to achieve a highly integrated single chip solution, a generic radio transmitter is required. Although the mixer-based (I/Q) transmitter architecture has the advantage of being generic, there are many noise sources and, hence, the spurious, out-of-band emissions are significant. As a consequence, external SAW filters are required which complicate the integration of a multi-band system. In this thesis, two innovative circuit techniques to improve the performance of the I/Q modulator have been introduced. The first of these techniques relies on a novel structure of three interconnected feedback loops at the input stage of the mixer. The second technique takes advantage of the speed that scaled CMOS technology offers and forms a new paradigm of digitally assisted RF circuits which improves the switching pair distortion. Measurements validate both techniques and the low noise TX design. Hence the external TX SAW filters can be removed. Prof. Dr. Q. Huang, ETH Zürich, examiner Prof. Dr. C. Enz, CSEM, co-examiner Diss. ETH-Nr

114 Master Theses Overview Spring Semester 2008 Andreas Bubenhofer Receiver for GSM/EDGE Roger Ulrich Low-Power Multi-Mode DAC and Reference for 2.5G/3G/4G Applications Christoph Rüegg VLSI Architectures for QR Interpolation Pascal Gubler Realtime Compression of Specific 3D Structures in FPGA Rhyner Reto Validation of the kp Method using First-Principle Function Theory Patrick Blösch Nitride based Back Contacts for Cu (In,Ga) Se2 Solar Cells Tung Tran Anh Multi-Bit Sigma Delta DAC for WLAN Autumn Semester 2008 Marco von Arb High-Performance Signal Processing Platform Fateh Schekeb Hannes Friederich Ugo Pelosi Christoph Böcklin Lukas Bruderer Johann Ertl Alberto Rizzi VLSI Implementation of Soft-Input Soft-Output MMSE Parallel Interference Cancellation From Linear to Sphere Detection - Implementation of Detection Algorithms for MIMO-OFDM Testbed Finite Element Simulation of Reliability-relevant Thermomechanical Effects in Traditional and Base Plate-less Power Modules Simulation of InGaN/GaN Nanocolumn LEDs VLSI Implementation of the LLL Lattice Reduction Algorithm for MIMO Detection Low-Power Secure Circuits for RFID Tags Thermomechanical Simulation of the Grease Pumping Effect in High-Power IGBT Modules 112

115 Semester Projects Overview Spring Semester 2008 Eugen Zgraggen Emre Ilgünsatiroglu Jonas Balmer Jürg Schellenberg Simulation of Plasmonic Waveguides with the Finite Element Method Noise in Avalanche Photodiodes Automatic Gain Control for Multi-User MIMO Testbed Parametric Equalizer for Embedded Audio Processing DSP Autumn Semester 2008 Georg Oberholzer Meteo Station on Spartacus Boming Jin Front-End Topologies for Low-Power Wireless Receivers in CMOS Dominik Bischoff Noise Variance Estimation for MIMO-OFDM Testbed Fabian Gut VLSI Implementation of the Whirlpool Hash Function Michael Hotz Richard Emler Matrix Decomposition Processor for MIMO Communication Giselher Wichmann Sandro Belfanti High-Throughput Turbo Decoder for 3GPP LTE Simon Schläpfer 113

116 Education at IIS 114

117 115

118 Lectures Halbleiterbauelemente Semiconductor Devices A. Schenk 4th Sem. EE This lecture gives an introduction to the basics of modern semiconductor devices for micro-, opto-, and power-electronics. It bases on semiconductor physics and covers band structures, band models, dispersion relations, statistics, transport equations, macroscopic models, and the characteristics of silicon and other semiconductors. An overview on device families is presented. The part on technologies covers the properties of materials, and introduces the steps of modern process technologies as well as packaging. To understand the basic principles of devices, ohmic and rectifying contacts, physical and electrical characteristics of pn junctions, and types of diodes are explained. The lecture continues with the bipolar transistor s function, working regions, characteristic diagrams, and its simulation. MOS devices are treated based on band diagrams, and the MOSFET behavior is deduced. Power devices, their working regions and static and dynamic behavior are followed by examples of optoelectronic devices as photo conductor, photodiode, LED, and fiber. Semiconductor measurement and characterization methods conclude the course. Kommunikationselektronik Communications Electronics Q. Huang 5th Sem. EE This course provides basic design and circuit techniques for communications electronics. As a starting point, bipolar and MOS transistors are reviewed. The discussion of circuit design begins with basic amplifier topologies, impedance matching concepts, and a bit of two-port theory. Important non-ideal aspects such as non-linearity and noise are discussed. This sets the ground for more involved topics. Important building blocks of communications equipment, such as mixers and oscillators, are examined in detail. The discussions include the basic topologies, mathematical descriptions, and a thorough analysis of non-ideal behavior, from which finally guidelines for the design can be derived. The exercises form an integral part of this course. The definitions and concepts presented in the lecture will be reinforced by small design examples, therefore providing a link between the theoretical description and real-world problems. Solid State Electronics Festkörperelektronik B. Witzigmann 5th Sem. EE The lecture Solid State Electronics explains the fundamental physical effects and properties for the operation of modern semiconductor devices. The focus is put on the solid state description by means of statistics, classical, and quantum physics. Device aspects play only a minor role, however, students learn the fundamentals for studying device operation in subsequent advanced lectures. In the beginning an introduction to quantum mechanics principles is given that helps understand the basic concepts from an engineering standpoint. The goal of the lecture is to get familiarized with the unique properties of semiconductors using a microscopic view, such as crystal structure, doping, energy bands, carrier dynamics and magnetic and optical properties. VLSI I: Von Architektur zu hochintegrierter Schaltung und FPGA VLSI I: From Architectures to Very Large Scale Integration Circuits and FPGAs N. Felber, W. Fichtner, H. Kaeslin 6th Sem. EE/CS/Phys/CSE As becomes clear from the subsequent list of topics, the first course in this series of three is mainly concerned with systemlevel issues of VLSI. Terminology, overview on design methodologies and fabrication avenues, levels of abstraction used for circuit description and simulation, VLSI design flow, dedicated VLSI architectures, how to obtain an architecture for a given processing algorithm, architectural transformations for meeting throughput, area, and power requirements. Hardware Description Languages (HDL) and their underlying concepts, VHDL for simulation and synthesis, the IEEE-1164 logic system, Register Transfer Level (RTL) synthesis. Timing models, Anceau diagrams, functional verification of digital circuits and systems, building blocks of digital VLSI circuits, case studies of actual circuits, comparison with microprocessors and DSPs. During the exercises students learn how to model digital ICs with VHDL. They write testbenches for simulation purposes and synthesize gate-level netlists for ASICs and FPGAs. 116

119 VLSI II: Entwurf von hochintegrierten Schaltungen VLSI II: Design of Very Large Scale Integration Circuits N. Felber, W. Fichtner, H. Kaeslin 7th Sem. EE/CS/Phys/CSE The second course begins with a thorough discussion of various technical aspects at the circuit and layout level. It then moves on to economic issues of VLSI. Topics include: limitations of functional design verification, techniques for improving controllability and observability, design for test, block isolation, scan-path techniques, partial scan and its caveats. Evaluation of various synchronous clocking disciplines, skew margins, clock distribution techniques. Asynchronous inputs, data inconsistency and metastability problems, synchronization. Cell libraries, Process-Temperature-Voltage (PTV) variations, transistor models, characteristics of CMOS inverters, complex gates. Power estimation and low-power design. Layout parasitics, transport delay, switching currents, ground bounce, controlling noise problems, power distribution, floorplanning, chip assembly. Layout design at the mask level, symbolic layout. Timing verification, physical design verification. Cost structures of microelectronics design and fabrication, avenues to low-volume fabrication, management of VLSI projects. Exercises are concerned with physical design and sound engineering practices for avoiding timing, testability, and layout parasitics problems. Industrial CAD tools are being used for place and route, clock tree generation, chip assembly, and physical design verification. Students that elect to carry through a term project at the laboratory are offered the opportunity to complete a full IC design cycle on a circuit of their own which gets actually fabricated. VLSI III: Test und Fabrikation von hochintegrierten Schaltungen VLSI III: Test and Fabrication of Very Large Scale Integration Circuits N. Felber, W. Fichtner, Kaeslin 8th Sem. EE/CS/Phys/CSE Whereas the preceding courses deal with design aspects of VLSI circuits, this one addresses manufacturing, testing, physical analysis, and packaging issues, such as: Effects of fabrication defects, abstraction from physical to transistor- and gatelevel fault models, fault grading of large ASICs. Generation of efficient test vector sets, enhancement of testability by built-in self-test techniques. Modern IC testers: Architectures and application. Deep-submicron CMOS fabrication processes with multi metal levels and the physical analysis of their devices. Packaging problems and solutions. Technology outlook. Exercises teach students how to use CAE/CAD software and automatic test equipment for verifying ASICs after fabrication. Students that submitted a design for manufacturing at the end of the 7th semester do so on their own circuits. Physical analysis methods with professional equipment (AFM, DLTS) complement this training. Analog Integrated Circuits 6th Sem. Q. Huang EE This course provides a foundation in analog integrated circuit design: After a review of bipolar and MOS devices and their small-signal equivalent circuit models, building blocks in analog circuits such as current sources, active load, current mirrors, supply independent biasing are presented. Other topics are differential amplifiers, cascade amplifiers, high gain structures, and output stages, and comparators, gain bandwidth product and stability of op-amps. Second-order effects in analog circuits such as mismatch, noise, and offset are investigated. More complex circuits such as A/D and D/A converters, analog multipliers and oscillators are analyzed. An introduction to switched-capacitor circuits from an IC designer s point of view is given. The exercise sessions aim to reinforce the lecture material by well-guided step-by-step design tasks. Cadence design tools are used to facilitate the tasks. There is also an experimental session on op-amp measurements. Advanced Optoelectronics 5th/7th Sem. B. Witzigmann EE This lecture consists of two main parts. First, it briefly reviews the fundamentals of semiconductor optoelectronic devices. They include the electronic properties of semiconductors, electromagnetics theory and waveguides, and the interaction of light and matter. A chapter on fibers is included as well. Second, the design principles and the functionality of the most important semiconductor optoelectronic devices are explained. These include e.g. lasers, modulators and photodiodes. The student will be able to connect the design criteria and the typical specifications to the fundamentals that are treated in the first part. 117

120 Halbleiter-Bauelemente: Physikalische Grundlagen und Simulation Semiconductor Devices: Physical Principles and Simulation A. Schenk 7th Sem. EE/Phys This course aims at understanding the principles behind the physics of modern electronic silicon semiconductor devices and the foundations of physical modeling of transport and its numerical simulation. During the course basic knowledge on quantum mechanics, semiconductor physics, and device physics is also provided. The main topics are: Transport models for semiconductor devices (quantum transport, Boltzmann equation, drift-diffusion model, hydrodynamic model), physical characterization of silicon (intrinsic properties, band gap narrowing, scattering processes), mobility of cold and hot carriers, recombination (SRH statistics, lifetimes for tunnel-assisted transitions), interband tunneling (Zener diode), impact ionization, metal-semiconductor contact, MIS structure, and heterojunctions. The exercises focus on the theory and the basic understanding of special devices, such as pn-diodes, bipolar transistors, MOSFETs, and thyristors. Numerical simulations of these devices with an advanced simulation package are compared with corresponding measurements, which are also part of the exercises. Halbleitertransporttheorie und Monte-Carlo Bauelementsimulation Semiconductor Transport Theory and Monte-Carlo Device Simulation F. Bufler, A. Schenk 8th Sem. EE/CSE The aim of the course is, on the one hand, to establish the link between microscopic physics and its concrete application in device simulation and, on the other hand, to introduce the numerical techniques involved. The scope encompasses therefore the basics of quantum mechanics, transport theory, and the Monte-Carlo method for the solution of the Boltzmann transport equation. The topics include second quantization, crystal symmetries, band structure calculation, phonons, Boltzmann equation, probability calculus, Monte-Carlo techniques, and device simulation. The exercises comprise problems to illustrate the contents of the lecture, simple Monte-Carlo related programming tasks as well as the application of various professional tools for device simulation. Material Properties and Characterization (Masters Course in Micro/Nano Electronics, Chapter on Electrical Properties of Materials) B. Witzigmann 7th Sem. EE/MPE This lecture focuses on the material properties in micro- and nanosystems. The discussion of material properties begins with basic continuum mechanics concepts where the constitutive laws, crystal, and anisotropy properties are discussed. In the following, fracture mechanics and failure mechanisms are treated. After this introduction into structural mechanics, the electrical, thermal, optical, and surface properties are discussed in detail, using a microscopic view. The goal of the course is to get familiarized and to understand the mechanisms behind the various properties of materials as they are relevant in specific situations when building micro- and nano-size systems. Elektrotechnik I Electrical Engineering I Q. Huang 3rd Sem. MPE This course provides the basic foundation in the specific field of electrical engineering. Starting from the basic concepts of voltage and currents, it covers the basic analyses of DC and AC networks. This includes series and parallel circuits, resistive circuits, circuits including capacitors and inductors, as well as the Kirchhoff s laws governing such circuits, and other network theorems. Transient response of RC-circuits, analysis of resonant circuits, concept of filtering, and simple filter circuits are all among the subjects covered in this course. The understanding of the basic concepts of electrical engineering, particularly of circuit theory, shall be advanced. At the end of the course, the successful student knows the basic elements of electric circuits and the basic laws and theorems for determining voltages and currents in circuits with such elements. He/she is also familiar with basic circuit calculations. Abbreviations: CS Computer Science CSE Computational Science and Engineering EE Electrical Engineering MPE Mechanical and Process Engineering Phys Physics 118

121 IC Design Projects Overview Projects in Progress Type Kind of Project VLSI Implementation of the Whirlpool Hash Function ASIC contribution to research project Matrix Decomposition Processor for MIMO Communication Systems ASIC contribution to research project Turbo Decoder for 3GPP LTE ASIC contribution to research project Low-Power Secure Circuits for RFID Tag ASIC contribution to research project Noise Estimation for MIMO-OFDM Testbed FPGA contribution to EU project Advanced Detection on MIMO-OFDM Testbed FPGA contribution to EU project VLSI Implementation of the LLL Algorithm ASIC contribution to EU project 2x2 MIMO-OFDM Baseband Processing on a Reconfigurable Processor ASIC contribution to KTI project VLSI Implementation of SISO MMSE PIC ASIC contribution to research project Receiver for GSM/EDGE ASIC contribution to research project Receiver for GSM/EDGE/Evolved EDGE ASIC contribution to research project Highly Linear D/A Converters as a Building Block for High-Performance ADCs ASIC contribution to research project Multi-Mode Delta-Sigma ADC ASIC contribution to research project High-Speed Pipelined A/D Converter in Deep-Submicron CMOS Technology ASIC contribution to research project Multi-Mode RF Receivers for Cellular Communications ASIC contribution to research project Completed IC Designs Type Result Pulse-Control Processor for Qubit Manipulation ASIC silicon fully functional MMSE-SQRD based on Gram-Schmidt ASIC silicon fully functional MMSE-OSIC Detector, Linear and SIC Detector for a MIMO-OFDM System ASIC silicon fully functional LDPC Decoder for MIMO Communication ASIC silicon fully functional High-Speed BCJR Decoder for MIMO Communication ASIC silicon fully functional Digital Audio Chip with High-Definition Audio Interface ASIC silicon fully functional High-Speed Folding and Interpolating A/D Converter Employing Digital Calibration ASIC silicon fully functional Matrix Preprocessing for MIMO-OFDM on the SOL-Processor ASIC silicon fully functional Fast AES Cipher Core with New Cells based on CMOS and Pass-Transistor Logic ASIC silicon fully functional Elliptical Curve Hardware Module for an RFIF Application ASIC silicon fully functional Automatic Gain Control for MIMO-OFDM Testbed FPGA successfully verified FPGA-ASIC Prototyping System FPGA successfully verified Meteo Station on Spartacus FPGA successfully verified VLSI Architectures for QR Interpolation BB successfully simulated Virtual Component for the Division Operation BB successfully simulated Front-End Topologies for Low-Power Wireless Receivers in CMOS BB successfully simulated Design of a Multi-Band CMOS RF Receiver Front-End for Mobile WiMAX BB successfully simulated Multi-Bit Sigma-Delta DAC for WLAN Applications BB successfully simulated Abbreviations: ASIC: Application-Specific Integrated Circuit BB: Building Block (contribution to research or industrial ASIC) FPGA: Field-Programmable Gate Array 119

122 Overview of IC Design Projects Completed in

123 Research Projects Overview Subject: IC and System Design and Test Algoritms and Software Programmable VLSI Architectures for Multi-Antenna Wireless LAN BridgeCo AG, Dübendorf (Switzerland) Computer Engineering and Networks Laboratory, ETH Zürich, Zürich (Switzerland) Period: October 06 March 08 Funding, Number: Subject: KTI*, NMPP BridgeCo AG, Dübendorf (Switzerland) MASCOT - Multiple Access Space-Time Coding Testbed (European IST Project) Computer Engineering and Networks Laboratory, ETH Zürich, Zürich (Switzerland MASCOT Consortium Period: January 06 December 08 Funding, Number: European Union, IST Subject: Quantum Cryptography Based Point-to-Point Secure Data Communication System (ESCRYPT II) id Quantique SA, Carouge (Switzerland) Fachhochschule Nordwestschweiz, Windisch (Switzerland) Period: December 08 May 10 Funding, Number: Subject: KTI*, PFNM-NM id Quantique SA, Carouge (Switzerland) Period: March 08 June 09 Funding, Number: Subject: Algorithmen und Archtekturen für drahtlose Heimnetztwerke der nächsten Generation (MIMO) (Algorithms and Architectures for Next Generation Wireless home Networks) Celestrius AG, Zürich (Switzerland) Computer Engineering and Networks Laboratory, ETH Zürich, Zürich (Switzerland) KTI*, PFNM-NM Celestrius AG, Zürich (Switzerland) Analog and Mixed-Signal IC Design Advanced Data Conversion and Digital Front-End Signal Processing for Multi-Standard Radios (ADEMAR) ACP AG, Zürich (Switzerland) Period: February 07 July 09 Funding, Number: KTI*, NMS ACP AG, Zürich (Switzerland) Subject: Advanced Multi-Mode Transceivers Beyond 3G (AMXCV3) Hasler Stiftung, Bern (Switzerland) Period: February 08 January 10 Funding, Number: Hasler, Bern (Switzerland) Subject: Technology CAD SUGERT Strategic User Group for European Research on TCAD (European IST Project) SUGERT Consortium Period: February 05 January 08 Funding, Number: European Union, IST Subject: Pilot Users: Improvement of Dopant Diffusion and Activation Models in Strained Silicon by Ab Initio Simulations on the Atomic Scale (ATOMDIFF) Synopsys Switzerland LLC, Zürich (Switzerland) Applied Materials, Inc., Sunnyvale, CA (USA) Fujitsu Laboratories, Atsugi (Japan) NEC Corporation, Kanagawa (Japan) Samsung Electronics, Yongin-City (Korea) ST Microelectronics, Crolles (France) Varian Semiconductor Equipment Associates, Inc., Gloucester, MA (USA) 121

124 Period: May 06 April 09 Funding, Number: KTI*, NMPP NM Synopsys Switzerland LLC, Zürich (Switzerland) Subject: PULLNANO - PULLing the Limits of NANOCMOS Electronics (European IST Project) PULLNANO Consortium Period: June 06 December 09 Funding, Number: European Union, IST Subject: Non Equilibrium Quantum Transport in Semiconductor Nanostructures: Bridging the Ballistic and Dissipative Regimes (NEQUATTRO 2) Period: October 07 September 08 Funding, Number: SNF*, Subject: Silicon.based nanostructures and nanodevices for long term nanoelectronics applications (NANOSIL) Period: January 08 - December 10 Funding, Number European Union, IT Subject: Evaluation and Comparison of Monte-Carlo Simulation Codes for Modeling of Electron Beam Lithography (EVAL-LITHO) Synopsys Switzerland LLC, Zürich (Switzerland) Period: September 08 Funding, Number: Synopsys Switzerland LLC, Zürich (Switzerland) Subject: Physics Based Simulation and Physical Characterization of MEMS (MEMS) Toshiba Corporation, Yokohama (Japan) Period: October 08 September 09 Funding, Number: Toshiba, Yokohama, (Japan) Subject: Multi physics simulation and modeling of advanced CMOS technologies (DEVICE) Toshiba Corporation, Minato-ku (Japan) Period: December 08 December 11 Funding, Number: Toshiba, Yokohama, (Japan) Subject: Computational Optoelectronics Microscopic Investigation of Optical Properties in Quantized Semiconductors Structures (GAIN) Period: April 05 March 08 Funding, Number: SNF*, Subject: Correct Wavelength-Scale Computer Simulation of Resonant Cavity Light-Emmitting Diodes as High Efficiency Light Sources (SERCLED) Fiber Optics Communication Laboratory, State Engineering University of Armenia, Yerevan (Armenia) Period: October 05 September 08 Funding, Number: SNF*, SCOPES IB Subject: Design and Fabrication of Electrically Pumped Ultrafast Vertical-External Cavity Laser using Physics-based Simulation (E-VECSEL) Institute for Quantum Electronics, ETH Zürich, Zürich (Switzerland) Period: October 05 - September 08 Funding, Number: ETH Zürich, Zürich (Switzerland), TH-46/ Subject: Optical Mode Analysis in External Cavity Semiconductor Lasers and Application to Blue Lasers (X-Mode) Period: April 07 September 09 Funding, Number: SNF*, Subject: Bookham VCSEL Bookham (Switzerland) AG, Zürich (Switzerland) Period: June 07 October 08 Funding, Number: Bookham Subject: Photodetectors for Next Generation Broadband Access Passive Optical Networks (PONDETECT) Enablence Switzerland AG, Rüschlikon (Switzerland) 122

125 Period: July 07 June 10 Funding, Number: KTI*, PFNM-NM Albis Optoelectronics Subject: Blue-Light Superluminescent Light-Emitting Devices IPEQ-LASPE, EPF Lausanne, 1015 Lausanne (Switzerland) Exalos AG, Zürich (Switzerland) Synopsys Switzerland LLC, Zürich (Switzerland) Period: November 07 October 08 Funding, Number: Subject: KTI* PFNM NM, Exalos AG, Zürich (Switzerland) Synopsys Switzerland LLC, Zürich (Switzerland) Towards directly modulated VCSELs at 40 Gbit/s (NCCR - VCSEL) QP-NCCR, Lausanne (Switzerland) Period: October 07 June 09 Funding, Number: SNF* Subject: Period: August 08 July 11 Funding, Number: Subject: Physics and simulation of electro-optical properties in non-polar nitride-based heterostructures (NONPOLAR) SNF*, 20PA Physical Characterization and Technology Development PORTES Power Reliability for Traction Electronics (European MC Project) PORTES Consortium Period: February 05 - January 08 Funding, Number: European Union, MTKI-CT Subject: PORTES Power Reliability for Traction Electronics (Alstom) Alstom Period: February 07 - January 09 Funding, Number: Alstom, Levallois-Perret (France) Subject: Thermal Interface Reliability ECPE Engineering Center for Power Electronics GmbH, Nürnberg (Germany) Period: December 06 November 08 Funding, Number: ECPE, Nürnberg (Germany) Subject: Design for Reliability (DfR) for SPT9 InfineonTechnologies Austria AG, Villach (Austria) Period: January 08 December 10 Funding, Number: Infineon Austria, Villach (Austria), Subject: Modeling and Optimization of Electron Beam Cross-Linking Processes for Electrical Wires, Cables, and Optical Fibers (EBX-Link) Huber + Suhner AG, Pfäffikon (Switzerland) Period: September 08 August 11 Funding, Number: KTI*, PFIW-IW Huber + Suhner, Pfäffikon (Switzerland) Subject: Bio Electromagnetics and Electromagnetic Compatibility Forschungskooperation IT IS ETH Zürich (Research Cooperation IT IS ETH Zürich) Foundation for Research on Information Technologies in Society (IT IS), Zürich (Switzerland) Period: since January 00 Funding, Number: IT IS, Zürich (Switzerland) Abbreviations KTI SNF Commission for Technology and Innovation (a Swiss Government Agency) Swiss National Science Foundation 123

126 Microelectronics Design Center (DZ) Personnel Dr. H. Kaeslin (head, VLSI CAE), Dr. F. Gürkaynak (VLSI technology, VLSI CAE/CAD), B. Muheim (software operation, VLSI CAE/CAD), R. Köppel (PCB CAD). A baseband processor for MIMO communication DZ staff has heavily contributed to designing the first VLSI chip for a joint and KTI-funded research project of IIS and Celestrius, a young ETH spin-off company. The chip is to act as baseband processor for MIMO OFDM (orthogonal frequency division multiplex) communication and has rather impressive characteristics. 49 on-chip RAMs (!) for a total of more than bits standard cells more than ten million transistors (!) 370 MHz clock 1 phase-locked loop 19-level clock tree of roughly buffers (!) 130 nm single-poly 8-metal CMOS 14 mm2 core area 268 pins 27 m of interconnect Figure 1: Plot of MIMO OFDM baseband processor chip 124

127 A new low-cost path for VLSI fabrication is the name for a special multi-project wafer (MPW) service offered by Europractice to stimulate universities and research institutes to prototype small ASIC designs for education or publicly funded research. While 5 mm x 5 mm is a typical die size on a regular MPW, this area is subdivided into nine dies of identical size to account for the fact that relevant circuits can be manufactured on relatively small chips today as a consequence of the growing integration densities. Let us give one example here, but be informed that the mini@sic program covers many more processes from five silicon vendors. 180 nm 1P6M CMOS process by UMC mm x mm die size up to gate equivalents 48 pads including power and ground 5 tape-outs per year EUR plus packaging and taxes A ready-to-go padframe and a test fixture can be made available, for further details please consult student/constraints/index.en.html. Figure 2: Typical mini@sic padframe. Cadence Academic Network While the license agreement concluded with Cadence in the year 2000 has worked very well, the recent Cadence Academic Network (CAN) program has opened new doors to European universities, notably in the fields of EDA training courses, exchange of know-how, and possibly also access to design kits for advanced process technologies. ETH has been accepted as a CAN member in 2008, and DZ plans to organize two on-site training courses on low-power digital and on analog-andmixed-signal design respectively in February Clearly, the usage of any EDA software at ETH remains confined to university research and teaching, any sort of commercial usage is off limits. Preparatory course on circuit and PCB design upgraded Since 2006 DZ has been offering a 8-half-day preparatory course to interested students in their 6th to 8th grade that planned to design PCBs as part of a term or thesis projects. Demand and positive feedback have encouraged us to go one step further in that a board now gets produced from each participant s layout data. While board manufacturing happens externally, the very designers assemble their board, put the circuit into operation, and test the result. A simple digital thermometer has been chosen as course vehicle. The circuit not only includes a precision temperature sensor, a transresistance amplifier, and a digital voltmeter module with an LCD display, but also a rectifier, capacitors, and voltage regulators. Auxiliary components such as bypass capacitors, connectors, switches, test pads, and even three small heat sinks offer opportunities to practice their proper sizing, selection, placement and mounting. Separate analog and digital grounds are yet another built-in feature that requires special attention. 125

128 The perspective of working on an actual circuit greatly motivates participants, provides them unexpected insights, and permits them to acquire first-hand experience with most of the realities of physical circuits and many of the mundane details of industrial engineering, including tolerances, standard EIA value series (E12, E24, E48, etc.), usage of zero-ohm resistors, PCB materials and layer stacks, mil vs. mm grids, cost awareness, and more. The two instructors, R. Köppel and M. Nussberger (external consultant), focus on showing students what matters to make a circuit manufacturable, something that is not normally taught in academia. The upgraded course now extends over 10 half-days and is offered in the first weeks of both spring and autumn terms. Figrue 3: PCB design in an industrial context (after R. Thüringer and F. Hillebarnd). Supported fabrication processes DZ has installed and maintains design flows for a wide range of VLSI fabrication processes and cell libraries. A summary overview is given in the table below. As this list is per force outdated by the time it gets printed, we kindly ask prospective IC designers to refer to our documentation on the Intranet available at for upto-date and more complete informations on the resources available. Please contact DZ staff as early as possible if you feel our current offerings do not meet your needs. Foundry Technology Litho. [nm] Isolation Layer Stack Metal Supply [V] Design Type AMS AMS IBM IBM IBM IBM NXP NXP NXP STM STM STM UMC UMC UMC BiCMOS CMOS CMOS CMOS CMOS BiCMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS LOCOS LOCOS STI STI STI DT, STI STI STI STI STI STI STI STI STI STI 2P4M 2P3M 1P10M 1P10M 1P8M 1P7M 1P9M 1P5M 1P6M 1P7M 1P9M 1P6M 1P8M 1P6M 1P5M Al Al Cu Cu Cu AlCu Cu Cu Cu Cu Cu Cu Cu Al/Cu Al Analog/Digital Analog/Digital Analog/Digital Analog/Digital Analog Analog Analog Analog Analog Analog/Digital Analog/Digital Analog/Digital Digital Digital Digitall Abbreviations: STI: Shallow Trench Isolation DT: Deep Trench xpym: x layers of poly, y layers of metal 126

129 Design Activities A statistical overview of all IC design activities conducted in 2008 with software installations operated by DZ and with support by DZ staff is given in the table below along with the laboratory involved and with the target process. Only manufactured chips are listed, FPGA-based design projects and dry runs are not included in the numbers below. IC Design Teaching Research Total Process family Foundry IIS-ETHZ IfE-ETHZ 180 nm CMOS 130 nm BiCMOS 130 nm CMOS 180nm BiCMOS UMC UMC STM IBM Total Courses Practical Circuit and PCB Design Organized by: Microelectronics Design Center Trainers: M. Nussberger, R. Köppel Dates: 8 half-days from February 28 to April 24, 2008 Practical Circuit and PCB Design Organized by: Microelectronics Design Center Trainers: M. Nussberger, R. Köppel Dates: 10 half-days from October 18 to December 4,

130 Joint Research Cooperation with the IT IS Foundation Profile The IT IS Foundation was established on November 15th, 1999 through the initiative and support of the Swiss Federal Institute of Technology in Zurich (ETHZ), the global wireless communications industry, and several governmental agencies. IT IS stands for Information Technologies in Society. The aim of IT IS is to create a flexible and dynamic research institution capable of addressing the research needs of society in the explosively expanding field of information technologies and the utilization of electromagnetic energies in general. Some of the areas encompassed are: evaluation of the safety and risks related to current and emerging information technologies exploration of information technologies for medical, diagnostic, and life support systems improvement of the accessibility of information technologies for all members of society including disabled persons. IT IS is committed to the advancement of science for the benefit of society at large and to maintaining strict independence from any particular interest groups. These principles are reflected in the Foundation s charter as well as the balance of the composition of its board, with distinguished personalities from science, the public sector, and the global wireless communications industry. IT IS is a non-profit tax-exempt research organization. Infrastructure and Cooperation The IT IS Foundation maintains the world s finest nearfield laboratories and is situated in downtown Zurich. It includes a large semi-anechoic chamber for general nearfield and dosimetric measurements. In 2007, new laboratories were built, designed for accredited testing of bodymounted transmitters as well as implants. IT IS Foundation s closest and most important cooperative tie is with the Integrated Systems Laboratory. Close cooperation has also been established with the Laboratories of Computer Vision and Biomedical Engineering as well as other laboratories of ETH Zurich. In addition, the IT IS team has substantial experience in multidisciplinary cooperation through a multitude of projects, resulting in an international network of over 80 academic and industry research partners in Europe, the USA, and Asia. Current Research Focus IT IS Foundation s current research focus of lies in the three areas of 1) sensing and computational techniques for electromagnetic analysis, 2) health risk assessment, and 3) health support systems. In addition, IT IS offers various services to governments and industry, including antenna engineering, device optimization for operation in EMF-hostile environments, testing of compliance, and safety white papers. The first area, Sensing and Computational Techniques, consists of several projects, ranging from new sensor technologies and new measurement procedures for testing the compliance of wireless devices and base stations with safety limits, to extensions and improvements of FDTD for near-field applications and optics. The technologies have been integrated and commercialized in products such as DASY5, EASY4, isar and SEMCAD X. These products have become the standard in the wireless as well as medical device industries for R&D, testing compliance and virtual prototyping. The second research area is Health Risk Assessment. This mainly involves the development, provision, and maintenance of exposure setups as well as the provision of detailed dosimetry for more than thirty experiments conducted in cooperation with biological and medical research groups in Switzerland, Europe, USA, China, and Japan. These include in vitro, in vivo, and human provocation studies involving various mobile communications bands as well as ELF experiments. In addition, IT IS is conducting basic and review studies for many different agencies. The Health Support System group, formed in 2003, is developing rapidly. Of particular mention are the projects on MR safety, MR safe implants and interventions under MR guidance, on applicators and treatment planning tools of hyperthermia and ablation, controllable nerve stimulation for neuroprothetics, optimized signal transmission over the body, and antenna designs for on-body and implanted antennas. In addition to providing research results for governmental agencies through participation in standardization bodies and providing consultation to governments, IT IS also provides courses to members of the public, industry, and universities. Current research projects are being supported by public funds such as those of NIH (USA), Framework Programs (EU), EUREKA (EU), CTI (CH), SNF (CH), health agencies such as BAG (CH) and BfS (D), as well as other governmental institutions (e.g., BAKOM). Funding from industry comes from major mobile communications manufacturers, medical device companies and service providers as well as from smaller companies. Director Prof. Dr. Niels Kuster kuster@itis.ethz.ch Main Office Address IT IS Foundation Mailing Address and Labs IT IS Foundation ETH Zurich, ETZ Zeughausstrasse 43 CH-8092 Zurich Switzerland Phone: Fax CH-8004 Zurich Switzerland info@itis.ethz.ch 128

131 IC and System Design and Test [D1.] [D2.] [D3.] [D4.] [D5.] [D6.] [D7.] [D8.] [D9.] Publications J.P. Aumasson, L. Henzen, W. Meier, R. Phan SHA-3 proposal BLAKE, NIST cryptographic hash Algorithm Competition, Oct 2008 F. Carbognani Low-Power Techniques for Low-Frequency VLSI Applications, PhD Thesis ETH-No , Hartung-Gorre Printing House, Konstanz, Germany, 2008 F. Carbognani Low-Power Techniques for Low-Frequency VLSI Applications, PhD Thesis ETH-No , Hartung-Gorre Printing House, Konstanz, Germany, 2008 F. Carbognani, F. Bürgin, N. Felber, H. Kaeslin, W. Fichtner A Low-Power Transmission-Gate-Based 16-bit Multiplier for Digital Hearing Aids, Analog Circuits and Signal Processing edited by Springer, vol. 56, no. 1, Aug 2008 F. Carbognani, F. Bürgin, N. Felber, H. Kaeslin, W. Fichtner Transmission Gates Combined with Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency Multipliers, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 7, pp , Jul 2008 S. Eberli, D. Cescato, W. Fichtner Divide-and-Conquer Matrix Inversion for Linear MMSE Detection in SDR MIMO Receivers, Proc. of NORCHIP 2008, Tallinn, Estonia, Nov 2008 S. Haene VLSI Circuits for MIMO-OFDM Physical Layer, PhD Thesis ETH-No , Hartung-Gorre Printing House, Konstanz, Germany, 2008 S. Haene, D. Perels, A. Burg A Real-Time 4-Stream MIMO-OFDM Transceiver: System Design, FPGA Implementation, and Characterization, IEEE Journal on Selected Areas in Communications, vol. 26, no. 6, pp , Aug 2008 S. Heinzle, O. Saurer, S. Axmann, D. Browarnik, A. Schmidt, F. Carbognani, P. Luethi, N. Felber, M. Gross A Transform, Lighting and Setup ASIC for Surface Splatting, Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), Seattle, WA, USA, May 2008 [D10.] L. Henzen, F. Carbognani, N. Felber, W. Fichtner FPGA Implementation of a 2G Fibre Channel Link Encryptor with Authenticated Encryption Mode GCM, Proc. of IEEE International Symposium on System-on-Chip, Tampere, Finland, Nov 2008 [D11.] L. Henzen, F. Carbognani, N. Felber, W. Fichtner VLSI Hardware Evaluation of the Stream Ciphers Salsa20 and ChaCha, and the Compression Function Rumba, Proc. of IEEE International Conference on Signals, Circuits & Systems, Hammamet, Tunisia, Nov 2008 [D12.] L. Henzen, F. Carbognani, N. Felber, W. Fichtner Hardware Comparison of the Hash Function Candidates RADIOGATUN, MAME, and LAKE, Proc. of IEEE NORCHIP, Tallinn, Estonia, Nov 2008 [D13.] P. Luethi, C. Studer, S. Duetsch, E. Zgraggen, H. Kaeslin, N. Felber, W. Fichtner Gram-Schmidt-based QR Decomposition for MIMO Detection: VLSI Implementation and Comparison, Proc. of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Macao, China, pp , Nov 2008 [D14.] P. Luethi, M. Wenk, T. Koch, M. Lerjen, N. Felber, W. Fichtner Multi-User MIMO Testbed, Proc. of ACM MobiCom 08 / WiNTECH 08 Workshop, San Francisco, CA, USA, pp , Sep 2008 [D15.] S. ONeil, K. Nohl, L. Henzen EnRUPT Hash Function Specification, NIST cryptographic hash Algorithm Competition, Oct 2008 [D16.] D. Perels Frame-Based MIMO-OFDM Systems: Impairment Estimation and Compensation, PhD Thesis ETH-No , Hartung-Gorre Printing House, Konstanz, Germany, 2008 [D17.] C. Senning, C. Studer, P. Luethi, W. Fichtner Hardware-Efficient Steering Matrix Computation Architecture for MIMO Communication Systems, Proc. of IEEE International Symposium on Circuits and Systems, Seattle, Washington, USA, May 2008 [D18.] C. Studer, H. Bölcskei Soft-Input Soft-Output Sphere Decoding, Proc. of IEEE Int. Symposium on Information Theory (ISIT), Toronto, ON, Canada, pp , Jul 2008 [D19.] C. Studer, A. Burg, H. Bölcskei Soft-output Sphere Decoding: Algorithms and VLSI Implementation, IEEE Journal on Selected Areas in Communications, vol. 26, no. 2, Apr

132 [D20.] C. Studer, P. Luethi, W. Fichtner VLSI Architecture for Data-Reduced Steering Matrix Feedback in MIMO Systems, Proc. of IEEE International Symposium on Circuits and Systems, Seattle, Washington, USA, May 2008 [D21.] C. Studer, N. Preyss, C. Roth, A. Burg Configurable High-Throughput Turbo Decoder Architecture for Quasi-Cyclic LDPC Codes, Proc. of 42th Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, USA, Oct 2008 [D22.] C. Studer, D. Seethaler, H. Bölcskei Finite Lattice-Size Effects in MIMO Detection, Proc. of the 42th Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, USA, Oct 2008 Analog and Mixed-Signal Design [A1.] C. Benkeser, A. Burg, T. Cupaiuolo, Q. Huang A 58mW 1.2mm2 HSDPA Turbo Decoder ASIC in 0.13μm CMOS, Proc. of International Solid-State Circuits Conference, S. Francisco, CA, USA, 3-7 Feb 2008, San Francisco, California, USA, vol. 51, pp , Feb 2008 Technology CAD [T1.] [T2.] [T3.] [T4.] [T5.] [T6.] [T7.] [T8.] [T9.] S.C. Brugger, V. Peikert, A. Schenk Coupling the Monte-Carlo Method with Semi-Analytical Solutions of the Boltzmann Transport Equation, Proc. of Int. Conf. on Simulation of Semiconductor Processes and Devices (SISPAD), Hakone, Japan, pp , Sep 2008 S.C. Brugger, V. Peikert, A. Schenk Exact Method to Solve the Boltzmann Equation to any Order in the Driving Forces: Application to Transport Parameters, phys. stat. sol. (c), vol. 5, no. 1, pp , Jan 2008 S. Brugger, V. Peikert, A. Schenk Coupling the Monte-Carlo Method with Semi-Analytical Solutions of the Boltzmann Transport Equation, Proc. of IEEE International Conference on Simulation of Semiconductor Devices and Processes (SISPAD), pp , Sep 2008 F.M. Bufler, R. Gautschi, A. Erlebach Monte Carlo Stress Engineering of Scaled (110) and (100) Bulk pmosfets, IEEE Electron Device Letters, vol. 29, no. 4, pp , Apr 2008 F.M. Bufler, F.O. Heinz, A. Tsibizov, M. Oulmane Simulation of <110> nmosfets With a Tensile Strained Cap Layer, ECS Transactions, Honolulu, HI, USA, vol. 16, no. 10, pp , Oct 2008 F.M. Bufler, L. Sponton, A. Erlebach FinFET Stress Engineering Using 3D Mechanical Stress and 2D Monte Carlo Device Simulation, Proc.of European Solid-State Device Research Conference ESSDERC, Edinburgh, Scotland, UK, pp , Sep 2008 W. Fichtner Overview of Technology Computer-Aided Design Tools and Applications in Technology Development, Manufacturing and Design, Journal of Computational and Theoretical Nanoscience, vol. 5, pp. 1-17, Jan 2008 M. Frey, A. Esposito, A. Schenk Simulation of Intravalley Acoustic Phonon Scattering in Silicon Nanowires, Proc. of ESSDERC 2008, Edinburgh, UK, pp , Sep 2008 J. Lorenz, D. Aemmer, B. Sahli, et al. International Technology Roadmap for Semiconductors ITRS, 2007 Edition, chapter Modeling and Simulation, ITRS and Worldwide Semiconductor Industry Associations, Austin TX, USA, 2008 [T10.] M. Luisier, A. Schenk Atomistic Simulation of Nanowire Transistors, Journal of Computational and Theoretical Nanoscience, vol. 5, no. 6, pp , Jun 2008 [T11.] M. Luisier, A. Schenk Two-Dimensional Tunneling Effects on the Leakage Current of MOSFETs With Single Dielectric and High-κ Gate Stacks, IEEE Trans. on Electron. Dev., vol. 55, no. 6, pp , Jun 2008 [T12.] M. Luisier, A. Schenk, W. Fichtner, T.B. Boykin, G. Klimeck A Parallel Sparse Linear Solver for Nearest-neighbor Tight-binding Problems, Proc. of 14th Int. Conf. on Parallel and Distributed Computing, Las Palmas de Gran Canaria, Spain, Aug

133 [T13.] B. Sahli, K. Vollenweider, N. Zographos, C. Zechner Ab Initio Calculations of Phosphorus and Arsenic Clustering Parameters for the Improvement of Process Simulation Models, Nucl. Instrum. Meth. B , p , 2008, Strasbourg, France, Nov 2008 [T14.] B. Sahli, K. Vollenweider, N. Zographos, C. Zechner, K. Suzuki Phosphorus Diffusion and Activation in Silicon: Process Simulation Based on ab Initio Calculations, Mater. Res. Soc. Symp. Proc 1070-E03-03, 2008, San Francisco, California, USA, Mar 2008 [T15.] A. Schenk, M. Luisier Three-dimensional Quantum Simulation of Silicon Nanowires, Proc. of IEEE Silicon Nanoelectronics Workshop (SNW), Honolulu, HI, USA, Jun 2008 [T16.] A. Schenk, M. Luisier 2D Simulation of Gate Currents in MOSFETs: Comparison between S-Device and the Quantum Mechanical Simulator GreenSolver, Proc. of Int. Conf. on Simulation of Semiconductor Processes and Devices (SISPAD), Hakone, Japan, pp , Sep 2008 [T17.] A. Schenk, M. Luisier, M. Frey, A. Esposito Simulation of Quantum Effects in Nanoscale Devices, Proc. of 3rd SINANO Summer School, Bertinoro, Italy, Sep 2008 Computational Optoelectronics [O1.] [O2.] [O3.] [O4.] [O5.] [O6.] [O7.] [O8.] [O9.] A. Bäcker, S. Odermatt, R. Santschi, F. Römer, B. Witzigmann, P. Royo, V. Iakovlev, A. Caliman, A. Mereuta, A. Syrbu, E. Kapon Transverse Optical Mode Analysis of Long-wavelength VCSELs in High Single-Mode Power Operation, Proc. of 8th International Conference on Numerical Simulation of Optoelectronic Devices (NUSOD), Nottingham, UK, Sep 2008 F. Intonti, S. Vignolini, F. Riboli, A. Vinattieri, D.S. Wiersma, M. Colocci, M. Guriolia, L. Balet, C. Monat, L.H. Li, N. Le Thomas, R. Houdre, A. Fiore, M. Francardi, A. Gerardino, F. Römer, B. Witzigmann Near-field Mapping of Quantum Dot Emission from Single Photonic Crystal Cavity Modes, Physica, vol. 40, no. 6, pp , Apr 2008 P. Kreuter, B. Witzigmann Combined Analytical-finite Difference Time-domain Full Wave Simulation of Mode-locked Vertical-extended-cavity Semiconductor Lasers, Journal of the Optical Society of America B, vol. 25, no. 7, pp , Jul 2008 P. Kreuter, B. Witzigmann, D. Maas, Y. Barbarin, T. Südmeyer, U. Keller On the Design of Electrically Pumped Vertical-external-cavity Surface-emitting Lasers, Applied Physics B, vol. 91, no. 2, pp , Mar 2008 V. Laino Performance Analysis of Edge Emitting LASERs in the Mid Infra-Red and Visible Spectrum, PhD Thesis ETH-No , Hartung-Gorre Printing House, Konstanz, Germany, 2008 M. Loeser, B. Witzigmann Multi-Dimensional Electro-Opto-Thermal Modeling of Broadband Optical Devices, IEEE Journal of Quantum Electronics, vol. 44, no. 6, pp , Jun 2008 H. Meier, B. Witzigmann Investigation of Bandwidth Limitations in Separate Absorption, Charge and Multiplication (SACM) Avalanche Photodiodes (APD), Proc. of CLEO, San Jose, USA, pp. 1-2, May 2008 F. Römer, B. Witzigmann Spectral and Spatial Properties of the Spontaneous Emission Enhancement in Photonic Crystal Cavities, Journal of the Optical Society of America B, vol. 25, no. 1, pp , Jan 2008 F. Römer, B. Witzigmann Spectral and Spatial Emission Properties of Photonic Crystal Cavities, Proc. of SPIE, San Jose, CA, USA, vol. 6901, pp , Feb 2008 [O10.] S. Steiger, R. Veprek, B. Witzigmann Unified Simulation of Transport and Luminescence in Optoelectronic Nanostructures, Journal of Computational Electronics, vol. 7, pp , Dec 2008 [O11.] R.G. Veprek, S. Steiger, B. Witzigmann Ellipticity and Spurious Solutions in k.p Calculations of III-Nitride Nanostructures, Proc. of 8th International Conference on Numerical Simulation of Optoelectronic Devices, Nottingham, UK, Sep

134 [O12.] R.G. Veprek, S. Steiger, B. Witzigmann Reliable k.p Band Structure Calculation for Nanostructures Using Finite Elements, Journal of Computational Electronics, vol. 7, no. 4, pp , Dec 2008 [O13.] R.G. Veprek, S. Steiger, B. Witzigmann GaN based Nanocolumns: Impact of Strain Engineering on the Electro-Optical Performance, Abstracts of International Workshop on Nitride semiconductors, Montreux, Switzerland, pp. 165, Oct 2008 [O14.] B. Witzigmann, A. Bäcker, S. Odermatt Physics and Simulation of Vertical-Cavity Surface-Emitting Lasers, Journal of Computational and Theoretical Nanoscience, vol. 5, pp. 1-14, Jun 2008 [O15.] B. Witzigmann, F. Römer Physics and Simulation of Photonic Crystal Purcell Light Emitters, Proc. of SPIE Photonics West Conference, Physics and Simulation of Optoelectronic Devices, San Jose, CA, USA, Jan 2008 [O16.] B. Witzigmann, M. Tomamichel, S. Steiger, R.G. Veprek, K. Kojima, U.T. Schwarz Analysis of Gain and Luminescence in Violet and Blue GaInN/GaN Quantum-wells, IEEE Journal of Quantum Electronics, vol. 44, no. 2, pp , Feb 2008 Physical Characterization [P1.] [P2.] [P3.] [P4.] [P5.] [P6.] [P7.] [P8.] [P9.] G. Banckaert, M. Mermet-Guyennet, A. Castellazzi A Study of Pressed Contact Technology on IGBT Devices between -40 degc and +200 degc, Proc. of the 5th International Conference on Integrated Power Electronics Systems, Nuerenberg, Germany, Mar 2008 A. Castellazzi, E. Batista, M. Ciappa, J.M. Dienot, M. Mermet-Guyennet, W. Fichtner Full Electro-Thermal Model of a 6.5kV Field-Stop IGBT Module, Proc. of Poster Presentation at the 39th IEEE Power Electronics Specialists Conference, Rhodes, Greece, Jun 2008 A. Castellazzi, M. Ciappa Multi-Level Electro-Thermal Modeling for Circuit Simulation of Packaged Power Devices, Proc. of 11th IEEE Workshop on Control and Modeling for Power Electronics (COMPEL), Zurich, Switzerland, vol. 11, Aug 2008 A. Castellazzi, M. Ciappa Novel Simulation Approach for Transient Analysis and Reliable Thermal Management of Power Devices, Proc. of 19th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF), Maastricht, The Netherlands, vol. 48, pp , Sep 2008 A. Castellazzi, M. Ciappa Novel Simulation Approach for Transient Analysis and Reliable Thermal Management of Power Devices, Microelectronics Reliability, vol. 48, pp , Aug 2008 A. Castellazzi, M. Ciappa, M. Mermet-Guyennet, W. Fichtner VHDL-AMS Simulation of Integrated Power Systems: a Unified Solution for Multi-Domain Multi-Level Abstraction Analysis, Proc. of the 5th International Conference on Integrated Power Electronics Systems, Nuernberg, Germany, Mar 2008 M. Ciappa Lifetime Modeling and Prediction of Power Devices (Invited Paper), Proc. of International Conference on Integration of Power Electronic Systems (CIPS), Nuremberg, Germany, vol. 5, pp , Mar 2008 M. Ciappa Extraction of Accurate Thermal Compact Models for Fast Electro-Thermal Simulation of Power Modules (Invited Paper), Proc. of International Workshop on Built-in Reliability into Power Electronic Systems, Toulouse, France, Jun 2008 M. Ciappa Lifetime Modeling and Prediction of Power Devices (Invited Paper), Proc. of International Workshop on Built-in Reliability into Power Electronic Systems, Toulouse, France, Jun 2008 [P10.] M. Ciappa Reconstruction of Scanning Electron Microscopy Images by Monte Carlo Simulation to Improve the Accuracy of Critical Dimension Measurement in Advanced CMOS Devices (Invited Paper), Proc. of International Workshop on Remote Scanning Electron Microscopy, Pula, Italy, Oct 2008 [P11.] L. Dalessandro, N. Karrer, M. Ciappa, A. Castellazzi, W. Fichtner Online and Offline Isolated Current Monitoring of Parallel Switched High-Voltage Multi-Chip IGBT Modules, Proc. of Poster Presentation at the 39th IEEE Power Electronics Specialists Conference (PESC 2008), Rhodes, Greece, Jun

135 [P12.] Y. Danto, M. Ciappa TDMR Packaging Special Issue, IEEE Transactions on Device and Materials Reliability, vol. 8, no. 3, pp , Sep 2008 [P13.] M. Mermet-Guyennet, A. Castellazzi, P. Lasserre, J. Saiz 3D Integration of Power Semiconductor Devices based on Surface Bump Technology, Proc. of the 5th International Conference on Integrated Power Electronics Systems, Nuernberg, Germany, pp , Mar 2008 [P14.] L. Vignaux, J. Saiz, A. Castellazzi, P. Ladoux VHDL-AMS Traction Drive Model Including a 3D Description of Thermal Effects., Proc. of the 19th International Symposium on Power Electronics, Electrical Drives, Automation and Motion (SPEE- DAM 2008), Ischia, Italy, Jun 2008 Bio-Electromagnetics and Electromagnetic Compatibility [B1.] [B2.] [B3.] [B4.] [B5.] [B6.] [B7.] [B8.] [B9.] B.B. Arnetz, L. Hillert, T. Akerstedt, A. Lowden, N. Kuster, S. Ebert, C. Boutry, S. Moffat, M. Berg, C. Wiholm Effects from 884 MHz Mobile Phone Radiofrequency on Brain Electrophysiology, Sleep, Cognition, and Well-being, Proc. of XIX General Assembly of the International Union of Radio Science (URSIGA), Chicago, IL, USA, Aug 2008 R. Benfante, R. Adele Antonini, N. Kuster, J. Schuderer, C. Maercker, F. Adlkofer, F. Clementi, D. Fornasari The Expression of PHOX2A, PHOX2B and of their Target Gene Dopamine-beta-hydroxylase (DbetaH) is not Modified by Exposure to Extremely-low-frequency Electromagnetic Field (ELF-EMF) in a Human Neuronal Model, Toxicology in Vitro, vol. 22, no. 6, pp , Jan 2008 S. Benkler, N. Chavannes, N. Kuster Real-world Low Frequency Simulations of Full Body Interactions, Proc. of 30th Annual Meeting of the Bioelectromagnetics Society (BEMS 2008), San Diego, CA, USA, Jun 2008 S. Benkler, N. Chavannes, N. Kuster Highly Detailed Low Frequency Full Body Electromagnetic Field Simulations in 3-D, Proc. of XIX General Assembly of the International Union of Radio Science (URSIGA), Chicago, IL, USA, Aug 2008 S. Benkler, N. Chavannes, N. Kuster Mastering Conformal Meshing for Complex CAD-based C-FDTD Simulations, IEEE Antennas and Propagation Magazine, vol. 50, no. 2, pp , Jan 2008 S. Benkler, E. Neufeld, N. Chavannes, N. Kuster Efficient 3-D Low Frequency Electromagnetic Simulations of Detailed Body Models as Basis for RF Ablation Simulations, Proc. of the 1st ESHO Educational School on Clinical Hyperthermia and the 10th International Congress on Hyperthermic Oncology, Munich, Germany, Apr 2008 G. Bit-Babik, A. Faraone, C. Penney, T. Wittig, A. Prokop, A. Christ, J. Shen, J. Chen Standardization of Computational Techniques for Compliance Evaluation of the Human Exposure in Automotive Environments: Bystander and Passenger RF Exposure from Mobile Radios with Vehicle-mount Antennas, Proc. of 2nd International Conference on Bioinformatics and Biomedical Engineering (icbbe), Shanghai, China, May 2008 C.M. Boutry, S. Kühn, P. Achermann, A. Romann, J. Keshvari, N. Kuster Dosimetric Evaluation and Comparison of Different RF Exposure Apparatuses Used in Human Volunteer Studies, Bioelectromagnetics, vol. 29, no. 1, pp , Jan 2008 E. Cabot, M. Capstick, S. Kuehn, A. Christ, N. Kuster Accurate Assessment of the MRI Benchmark for Implanted Leads, Proc. of 30th Annual Meeting of the Bioelectromagnetics Society (BEMS 2008), San Diego, CA, USA, Jun 2008 [B10.] E. Cabot, A. Christ, N. Kuster Whole Body and Local SAR in Anatomical Phantoms Exposed to RF Fields from Birdcage Coils, Proc. of XIX General Assembly of the International Union of Radio Science (URSIGA), Chicago, IL, USA, Aug 2008 [B11.] M.H. Capstick, J.O. Jekkonen, A.C. Marvin, I.D. Flintoft, L. Dawson A Novel Indirect Method to Determine the Radiation Impedance of a Handheld Antenna Structure, IEEE Transactions on Instrumentation and Measurement, pp. 8, Dec 2008 [B12.] M. Capstick, N. Kuster, S. Kühn, V. Berdinas-Torres, J. Ladbury, G. Koepke, D. McCormick, J. Gauger, R. Melnick A Radio Frequency Reverberation Chamber Exposure System for Rodents, Proc. of XIX General Assembly of the International Union of Radio Science (URSIGA), Chicago, IL, USA, Aug 2008 [B13.] M. Capstick, N. Kuster, S. Kühn, V. Berdinas-Torres, J. Ladbury, G. Koepke, D. McCormick, J. Gauger, R. Melnick A Radio Frequency Radiation Reverberation Chamber Exposure System for Rodents, Proc. of Cranfield University Multi-Strand Conference, Bedfordshire, UK, May

136 [B14.] E. Cherubini, N. Chavannes, N. Kuster Realistic Skeleton Based Deformation of High-resolution Anatomical Human Models for Electromagnetic Simulation, Proc. of 30th Annual Meeting of the Bioelectromagnetics Society (BEMS 2008), San Diego, CA, USA, Jun 2008 [B15.] E. Cherubini, N. Chavannes, N. Kuster Realistic Skeleton Based Deformation of High-resolution Anatomical Human Models for Electromagnetic Simulations, Proc. of XIX General Assembly of the International Union of Radio Science (URSIGA), Chicago, IL, USA, Aug 2008 [B16.] A. Christ, M.C. Gosselin, M. Murbach, S. Ryf, M. Christopoulou, E. Neufeld, C. Gabriel, A. Peyman, N. Kuster Age Dependent Changes in SAR and Temperature Distribution Induced in the User s Head by Cellular Phones, Proc. of 30th Annual Meeting of the Bioelectromagnetics Society (BEMS), San Diego, CA, USA, Jun 2008 [B17.] A. Christ, G. Schmid, M. Bouterfas, R. Überbacher, M. Zefferer, E. Neufeld, N. Kuster Development of Anatomical CAD Models of Children for the Assessment of EM Field Exposure, Proc. of 30th Annual Meeting of the Bioelectromagnetics Society (BEMS), San Diego, CA, USA, Jun 2008 [B18.] M. Christen, O. Schenk, P. Messmer, E. Neufeld, H. Burkhart Accelerating Stencil-based Computations by Increased Temporal Locality on Modern Multi- and Many-core Architectures, Proc. of First International Workshop on New Frontiers in High-performance and Hardware-aware Computing (HipHaC 08), Lake Como, Italy, Nov 2008 [B19.] M. Christopoulou, M. Murbach, A. Christ, P. Crespo-Valero, M. Zefferer, S. Kuehn, P. Achermann, N. Kuster Exposure Systems for Testing Hypotheses of Site and Mechanism of Interaction in the Human Brain, Proc. of 30th Annual Meeting of the Bioelectromagnetics Society (BEMS), San Diego, CA, USA, Jun 2008 [B20.] P. Crespo-Valero, N. Chavannes, N. Kuster Efficient and Versatile Implementation of Different Spatial-averaging Schemes for SAR, Proc. of 30th Annual Meeting of the Bioelectromagnetics Society (BEMS), San Diego, CA, USA, Jun 2008 [B21.] P. Crespo-Valero, N. Chavannes, N. Kuster Efficient Implementation of Cubical, Spherical and Contiguous Schemes for SAR Averaging, Proc. of XIX General Assembly of the International Union of Radio Science (URSIGA), Chicago, IL, USA, Aug 2008 [B22.] P. Crespo-Valero, N. Chavannes, N. Kuster Efficient Implementation of SAR Averaging Techniques in Computational Dosimetry for Highly Detailed Human Models, Proc. of XIX General Assembly of the International Union of Radio Science (URSIGA), Chicago, IL, USA, Aug 2008 [B23.] P. Crespo-Valero, I. Stevanovic, D. Llorens del Rio, J.R. Mosig On the Coupling Integrals Arising in the Method of Moments Formulation of Laterally Bounded Structures, IEEE Transactions on, Microwave Theory and Techniques, vol. 56, no. 12, pp , Nov 2008 [B24.] A.S. Dawe, R. Nylund, D. Leszczynski, N. Kuster, T. Reader, D.I. De Pomerai Continuous Wave and Simulated GSM Exposure at 1.8 W/kg and 1.8 GHz do not Induce hsp16-1 Heat-shock Gene Expression in Caenorhabditis Elegans, Bioelectromagnetics, vol. 28, no. 2, pp , Jan 2008 [B25.] P. Futter, N. Chavannes, R. Tay, M. Meili, A. Klingenböck, K. Pokovic, N. Kuster Reliable Prediction of Mobile Phone Performance for Realistic In-use Conditions Using the FDTD Method, IEEE Antennas and Propagation Magazine, vol. 50, no. 1, pp , Jan 2008 [B26.] T. Gohil, K. Muralidhar, D. Szczerba Simulation of Oscillatory Flow in an Aortic Bifurcation, Proc. of Fluid Mechanics and Fluid Power Conference 2008, Bangalore, India, pp , Dec 2008 [B27.] M.C. Gosselin, A. Christ, M. Murbach, S. Ryf, S. Kühn, M. Christopoulou, E. Neufeld, C. Gabriel, A. Peyman, N. Kuster Influences of Age Dependent Tissue Parameters and Anatomical Structures on SAR and Temperature Increase in the Heads of Cellular Phone Users, Proc. of XIX General Assembly of the International Union of Radio Science (URSIGA), Chicago, IL, USA, Aug 2008 [B28.] L. Hillert, T. Akerstedt, A. Lowden, C. Wiholm, N. Kuster, S. Ebert, C. Boutry, S.D. Moffat, M. Berg, B. Birger Arnetz The Effects of 884 MHz GSM Wireless Communication Signals on Headache and Other Symptoms: An Experimental Provocation Study, Bioelectromagnetics, vol. 29, no. 3, pp , Jan 2008 [B29.] L. Hillert, A. Torbjörn, A. Lowden, M. Anderson, H. Svensson, C. Wiholm, N. Kuster, B.B. Arnetz Factors Affecting Radiofrequency Power Output of Mobile Phones, Proc. of 30th Annual Meeting of the Bioelectromagnetics Society, San Diego, CA, USA, Jun

137 [B30.] R. Hruby, G. Neubauer, N. Kuster, W. Kainz, M. Frauscher Study on Potential Effects of 902-MHz GSM-type Wireless Communication Signals on DBMA-induced Mammary Tumours in Sprague-Dawley Rats, Mutation Research/Genetic Toxicology and Environmental Mutagenesis, vol. 649, no. 1, pp , Jan 2008 [B31.] S. Kühn, P. Achermann, A. Romann, J. Keshvari, N. Kuster Dosimetric Evaluation and Comparison of Different RF Exposure Apparatuses Used in Human Volunteer Studies, Bioelectromagnetics, vol. 29, no. 1, pp , Jan 2008 [B32.] S. Kühn, M.C. Gosselin, A. Christ, M. Zefferer, E. Cherubini, N. Kuster Experimental Evaluation of the SAR Induced in a Head Phantom of a Three Year Old Child, Proc. of 30th Annual Meeting of the Bioelectromagnetics Society (BEMS), San Diego, CA, USA, Jun 2008 [B33.] M. Kelsh, A.R. Sheppard, M. Shum, L. Erdreich, E. Lau, N. Kuster, M. McNeely Factors Affecting Radiofrequency Power Output of Mobile Phones, Proc. of 30th Annual Meeting of the Bioelectromagnetics Society (BEMS 2008), San Diego, CA, USA, Jun 2008 [B34.] S. Kuehn, W. Jennings, M.C. Gosselin, A. Christ, N. Kuster Inconsistency of Reference Values and Spatial Averaging of IEEE/ICNIRP Guidelines with Basic Restrictions, Proc. of 30th Annual Meeting of the Bioelectromagnetics Society (BEMS 2008), San Diego, CA, USA, Jun 2008 [B35.] N. Kuster Health Aspects of the Proliferation of Wireless Communications in a Deregulated Arena, Abstracts of the XIX General Assembly of the International Union of Radio Science (URSIGA), Chicago, IL, USA, Aug 2008 [B36.] N. Kuster Latest Progress and Future Needs for Experimental and Numerical Em Field Analysis, Design and Optimization (Invited Paper), Abstracts of the KIEES 12th Workshop on Health Effects on EMF and Bioelectromagnetic Environment, Seoul, South Korea, Sep 2008 [B37.] N. Kuster Does Dosimetry Support the Possibility of Non-thermal Effects? (Invited Paper), Proc. of the 30th Annual Meeting of the Bioelectromagnetics Society (BEMS), San Diego, CA, USA, Jun 2008 [B38.] N. Kuster, M. Murbach, M. Christopoulou, S. Kühn, A. Christ Experimental Outcome of Human Provocation Studies Depend on the Design Specifics of the Exposure Setup, Proc. of XIX General Assembly of the International Union of Radio Science (URSIGA), Chicago, IL, USA, Aug 2008 [B39.] N. Kuster, E. Neufeld Easy-to-use, Real-time & Reliable Hyperthermia Treatment Planning: Expectations & Reality, Proc. of 1st ESHO Educational School on Clinical Hyperthermia and the 10th International Congress on Hyperthermic Oncology, Munich, Germany, Apr 2008 [B40.] N. Kuster, F.J. Nuñez, S. Benkler, N. Chavannes Latest Advances in Hybrid FDTD Approaches (Invited Paper), Abstracts of the VI Iberian Meeting on Computational Electromagnetism (EIEC ), Chiclana de la Frontera, Cadiz, Spain, Sep 2008 [B41.] C.H. Li, E. Ofli, N. Chavannes, E. Cherubini, H.U. Gerber, N. Kuster Effects of Hand Phantom and Different Use Patterns on Mobile Phone Antenna Radiation Performance, Proc. of IEEE International Symposium on Antennas and Propagation, San Diego, California, USA, Jul 2008 [B42.] B.A. Lloyd, D. Szczerba, M. Rudin, G. Székely A computational Framework for Modelling Solid Tumour Growth, Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences, vol. 366, no. 1879, pp , Jan 2008 [B43.] R. McGregor, D. Szczerba, M. von Siebenthal, K. Muralidhar, G. Székely Exploring the Use of Proper Orthogonal Decomposition for Enhancing Blood Flow Images via Computational Fluid Dynamics, Proc. of Medical Image Computing and Computer-Assisted Intervention - MICCAI 2008, New York, NY, USA, Lecture Notes in Computer Science Vol 5242, pp , Sep 2008 [B44.] E. Neufeld, N. Chavannes, M. Paulides, G. van Rhoon, N. Kuster Fast (re)-optimization for Hyperthermia: Bringing Treatment Planning Into the Treatment Room, Proc. of 1st ESHO Educational School on Clinical Hyperthermia and the 10th International Congress on Hyperthermic Oncology, Munich, Germany, Apr 2008 [B45.] E. Neufeld, N. Chavannes, M.M. Paulides, G. van Rhoon, N. Kuster Latest Breakthroughs in Treatment Planning Tools for Hyperthermia (Invited Paper), Proc. of Annual Meeting of the Bioelectromagnetics Society Winter Workshop (BEMS), Washington, DC, USA, Feb

138 [B46.] E. Neufeld, N. Chavannes, M.M. Paulides, G. van Rhoon, N. Kuster Fast SAR and Temperature Field (re-)optimization for Hyperthermia: Bringing Treatment Planning Into the Treatment Room, Proc. of 30th Annual Meeting of the Bioelectromagnetics Society (BEMS), San Diego, CA, USA, Jun 2008 [B47.] E. Neufeld, T. Samaras, N. Chavannes, G. Szekely, N. Kuster From Vessels to Wires and 1-D Boundaries: A Technique for Simulating the Thermal Impact of Thin Structures, Proc. of the 1st ESHO Educational School on Clinical Hyperthermia and the 10th International Congress on Hyperthermic Oncology, Munich, Bavaria, Germany, Apr 2008 [B48.] E. Neufeld, T. Samaras, N. Chavannes, G. Szekely, N. Kuster From Vessels to Wires and 1D Boundaries: A Technique for Simulating the Thermal Impact of Thin Structures, Proc. of 30th Annual Meeting of the Bioelectromagnetics Society (BEMS), San Diego, CA, USA, Jun 2008 [B49.] F.J. Nunez, P. Futter, W. Jennings, N. Chavannes, N. Kuster Solving EMI by Using SPICE-FDTD CO-SIMULATION Engine for Active Integrated Circuits, Proc. of IEEE International Symposium on Antennas and Propagation (APS), San Diego, CA, USA, Jul 2008 [B50.] F.J. Nunez, W. Jennings, P. Futter, N. Chavannes, N. Kuster Dispersive Material Model Optimization for FDTD Applications, Proc. of IEEE International Symposium on Antennas and Propagation (APS), San Diego, CA, USA, Jul 2008 [B51.] M. Oberle System for Hyperthermia Cure of Neck and Head Tumors (HYCUNEHT), Proc. of CTI Medtech Event, Bern, Switzerland, Sep 2008 [B52.] E. Ofli, C. Li, N. Chavannes, N. Kuster Analysis and Optimization of Mobile Phone Antenna Radiation Performance in the Presence of Head and Hand Phantoms, Turkish Journal of Electrical Engineering & Computer Sciences, vol. 16, no. 1, pp , Feb 2008 [B53.] E. Ofli, C.H. Li, F. Nunez, N. Chavannes, G. Castillo, N. Kuster Genetic Algorithm Optimization of Mobile Phone Antenna Performance under Real Usage Conditions, Proc. of IEEE International Symposium on Antennas and Propagation, San Diego, California, USA, Jul 2008 [B54.] M.M. Paulides, J.F. Bakker, E. Neufeld, P.P. Jansen, P.C. Levendag, J. van der Zee, G.C. van Rhoon Application of Hyperthermia in the Head and Neck Using the HYPERcollar, Proc. of 1st ESHO Educational School on Clinical Hyperthermia and the 10th International Congress on Hyperthermic Oncology, Munich, Germany, Apr 2008 [B55.] S. Schild, M. Ammann, N. Chavannes, N. Kuster A Fast ADE-FDTD Method for Linear and Nonlinear Dispersion, Proc. of XVIIth International Workshop on Optical Waveguide Theory and Numerical Modelling, Eindhoven, Netherlands, Jun 2008 [B56.] S. Schild, M. Ammann, N. Chavannes, N. Kuster A Novel Approach to Model Linear and Nonlinear Dispersion with ADE-FDTD, Proc. of IEEE International Symposium on Antennas and Propagation (APS), San Diego, CA, USA, Jul 2008 [B57.] S. Schild, S. Blum, N. Chavannes, N. Kuster Integration of Nonlinear Magnetic Materials in FDTD, Proc. of IEEE International Symposium on Antennas and Propagation (APS), San Diego, CA, USA, Jul 2008 [B58.] D. Szczerba, B. Lloyd, M. Bajka, G. Székely A Multiphysics Model of Myoma Growth, Proc. of Computational Science (ICCS 2008), Krakow, Poland, vol. 5104, pp , Jun 2008 [B59.] D. Szczerba, R. McGregor, K. Muralidhar, G. Székely Mechanism and Localization of Wall Failure During Abdominal Aortic Aneurysm Formation, Proc. of 4th International Symposium on Biomedical Simulation, London, Great Britain, Lecture Notes in Computer Science Vol 5104, pp , Jul 2008 [B60.] S. Tuchschmid, M. Bajka, D. Szczerba, B.A. Lloyd, G. Székely, M. Harders Modeling Intravasation of Liquid Distension Media in Surgical Simulators, Medical Image Analysis, vol. 12, no. 5, pp , Jan 2008 [B61.] G.C. van Rhoon, M. De Bruijne, N. Kuster, E. Neufeld, J. Van der Zee Latest Breakthroughs in Treatment Planning Tools for Hyperthermia (Invited Paper), Proc. of BEMS 2008 Winter Workshop, Washington, DC, USA, Feb 2008 [B62.] G. van Rhoon, M. Paulides, J. Bakker, N. Kuster, E. Neufeld, C. van der Zee, P. Levendag Hyperthermia Treatment Planning Targets Heating to the Tumor, Proc. of 27th annual congress of the European Society for Therapeutic Radiology and Oncology (ESTRO), Goeteborg, Sweden, Sep 2008 [B63.] C. Wiholm, A. Lowden, N. Kuster, L. Hillert, B.B. Arnetz, T. Akerstedt, S.D. Moffat Mobile Phone Exposure and Spatial Memory, Bioelectromagnetics, vol. 30, no. 1, pp , Sep

139 Microelectronics Design Center [M1.] [M2.] H. Kaeslin Digital Integrated Circuit Design, from VLSI Architectures to CMOS Fabrication, Cambridge University Press, , Cambridge, UK, pp. 862, 2008 H. Kaeslin, N. Felber Why do Electrical Engineering Students Love VLSI Design? (Invited talk), Proc. of 7th European Workshop on Microelectronics Education (EWME 2008), Budapest, Hungary, pp. 6-9, May

140 IC and System Design and Test Presentations S. Eberli, D. Cescato, W. Fichtner Divide-and-Conquer Matrix Inversion for Linear MMSE Detection in SDR MIMO Receivers, NORCHIP, Tallinn, Estonia, Nov 2008 S. Heinzle, O. Saurer, S. Axmann, D. Browarnik, A. Schmidt, F. Carbognani, P. Luethi, N. Felber, M. Gross A Transform, Lighting and Setup ASIC for Surface Splatting, IEEE International Symposium on Circuits and Systems (ISCAS), Seattle, WA, USA, May 2008 L. Henzen, F. Carbognani, N. Felber, W. Fichtner FPGA Implementation of a 2G Fibre Channel Link Encryptor with Authenticated Encryption Mode GCM, IEEE International Symposium on System-on-Chip, Tampere, Finland, 4-6 Nov 2008 L. Henzen, F. Carbognani, N. Felber, W. Fichtner VLSI Hardware Evaluation of the Stream Ciphers Salsa20 and ChaCha, and the Compression Function Rumba, IEEE International Conference on Signals, Circuits & Systems, Hammamet, Tunisia, 7-9 Nov 2008 L. Henzen, F. Carbognani, N. Felber, W. Fichtner Hardware Comparison of the Hash Function Candidates RADIOGATUN, MAME, and LAKE, IEEE NORCHIP, Tallinn, Estonia, Nov 2008 P. Luethi, C. Studer, S. Duetsch, E. Zgraggen, H. Kaeslin, N. Felber, W. Fichtner Gram-Schmidt-based QR Decomposition for MIMO Detection: VLSI Implementation and Comparison, IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Macao, China, 30 Nov - 3 Dec 2008 P. Luethi, M. Wenk, T. Koch, M. Lerjen, N. Felber, W. Fichtner Multi-User MIMO Testbed, Poster Presentation at ACM MobiCom 08 Conference - WiNTECH 08 Workshop with Demo Contest, San Francisco, CA, USA, 19 Sep 2008 C. Senning, C. Studer, P. Luethi, W. Fichtner Hardware-Efficient Steering Matrix Computation Architecture for MIMO Communication Systems, IEEE International Symposium on Circuits and Systems, Seattle, Washington, USA, May 2008 C. Studer, H. Bölcskei Soft-Input Soft-Output Sphere Decoding, IEEE Int. Symposium on Information Theory (ISIT), Toronto, ON, Canada, 10 Jul 2008 C. Studer, P. Luethi, W. Fichtner VLSI Architecture for Data-Reduced Steering Matrix Feedback in MIMO Systems, IEEE International Symposium on Circuits and Systems, Seattle, Washington, USA, May 2008 C. Studer, N. Preyss, C. Roth, A. Burg Configurable High-Throughput Turbo Decoder Architecture for Quasi-Cyclic LDPC Codes, 42th Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, USA, 28 Oct 2008 C. Studer, D. Seethaler, H. Bölcskei Finite Lattice-Size Effects in MIMO Detection, Proceedings of the 42th Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, USA, 26 Oct 2008 Analog and Mixed-Signal Design C. Benkeser, A. Burg, T. Cupaiuolo, Q. Huang A 58mW 1.2mm2 HSDPA Turbo Decoder ASIC in 0.13μm CMOS, International Solid-State Circuits Conference, S. Francisco, CA, USA, 3-7 Feb 2008, San Francisco, California, USA, 3-7 Feb 2008 Q. Huang Progress of RFICs and 4G Challenges Technische Universiteit Eindhofen, The Netherlands, 9 May 2008 T. Christen A CMOS EDGE/UMTS/WLAN Tri-Mode Delta-Sigma ADC, IEEE CAS/ED Sigma-Delta Late Afternoon Seminar, Brugg, Switzerland, 2 Sep 2008 Technology CAD S.C. Brugger, V. Peikert, A. Schenk Coupling the Monte-Carlo Method with Semi-Analytical Solutions of the Boltzmann Transport Equation, Int. Conf. on Simulation of Semiconductor Processes and Devices (SISPAD), Hakone, Japan, 9-11 Sep

141 S. Brugger, V. Peikert, A. Schenk Coupling the Monte-Carlo Method with Semi-Analytical Solutions of the Boltzmann Transport Equation, IEEE International Conference on Simulation of Semiconductor Devices and Processes (SISPAD), 9-11 Sep 2008 F.M. Bufler Monte Carlo Stress Engineering of Scaled (110) and (100) Bulk p-mosfets, International Summer School on Modeling and Optimization in Micro- and Nano-Electronics MOMiNE, Ragusa, Sicily, Italy, 17 Jun 2008 F.M. Bufler, F.O. Heinz, A. Tsibizov, M. Oulmane Simulation of <110> nmosfets With a Tensile Strained Cap Layer, Electrochemical Society Meeting ECS; SiGe, Ge and Related Compounds: Materials, Processing and Devices, Honolulu, HI, USA, Oct 2008 F.M. Bufler, L. Sponton, A. Erlebach FinFET Stress Engineering Using 3D Mechanical Stress and 2D Monte Carlo Device Simulation, European Solid-State Device Research Conference ESSDERC, Edinburgh, Scotland, UK, Sep 2008 A. Esposito, A. Schenk Limitations of the Effective Mass Approximation: A specific Example, Schweizer Numerik Kolloquium 2008, Fribourg, Fribourg, Switzerland, 25 Apr 2008 M. Frey, A. Esposito, A. Schenk Simulation of Intravalley Acoustic Phonon Scattering in Silicon Nanowires, ESSDERC 2008, Edinburgh, UK, 15 Sep Sep 2020 M. Luisier, A. Schenk, W. Fichtner, T.B. Boykin, G. Klimeck A Parallel Sparse Linear Solver for Nearest-neighbor Tight-binding Problems, 14th Int. Conf. on Parallel and Distributed Computing, Las Palmas de Gran Canaria, Spain, Aug 2008 S. Monaghan, P.K. Hurley, K. Cherkaoui, M.A. Negara, A. Schenk Determination of Physical Parameters for HfO2/SiOx/TiN MOSFET Gate Stacks by Electrical Characterization and Reverse Modeling, 9th Conf. on Ultimate Integration on Silicon (ULIS), Udine, Italy, Mar 2008 B. Sahli Computational Science and Engineering in Nanoelectronics (Invited Paper), CSCS User Day 2008, Lucerne, Switzerland, 12 Sep 2008 B. Sahli, K. Vollenweider, N. Zographos, C. Zechner Ab Initio Calculations of Phosphorus and Arsenic Clustering Parameters for the Improvement of Process Simulation Models, E-MRS Spring Meeting 2008, Strasbourg, France, May 2008 B. Sahli, K. Vollenweider, N. Zographos, C. Zechner, K. Suzuki Phosphorus Diffusion and Activation in Silicon: Process Simulation Based on ab Initio Calculations, MRS Spring Meeting 2008, San Francisco, California, USA, Mar 2008 A. Schenk, M. Luisier Three-dimensional Quantum Simulation of Silicon Nanowires, IEEE Silicon Nanoelectronics Workshop (SNW), Honolulu, HI, USA, Jun 2008 A. Schenk, M. Luisier 2D Simulation of Gate Currents in MOSFETs: Comparison between S-Device and the Quantum Mechanical Simulator GreenSolver, Int. Conf. on Simulation of Semiconductor Processes and Devices (SISPAD), Hakone, Japan, 9-11 Sep 2008 A. Schenk, M. Luisier, M. Frey, A. Esposito Simulation of Quantum Effects in Nanoscale Devices, 3rd SINANO Summer School, Bertinoro, Italy, 1-5 Sep 2008 Computational Optoelectronics P. Arbenz, U. Weber, R. Veprek, B. Witzigmann A Jacobi-Davidson Algorithm for Large Eigenvalue Problems from Opto-Electronics, Recent Advances in Numerical Methods for Eigenvalue Problems (RANMEP2008), Hsinchu, Taiwan, 4-8 Jan 2008 A. Bäcker, S. Odermatt, R. Santschi, F. Römer, B. Witzigmann, P. Royo, V. Iakovlev, A. Caliman, A. Mereuta, A. Syrbu, E. Kapon Transverse Optical Mode Analysis of Long-wavelength VCSELs in High Single-Mode Power Operation, 8th International Conference on Numerical Simulation of Optoelectronic Devices (NUSOD), Nottingham, UK, 1-4 Sep 2008 H. Meier, B. Witzigmann Investigation of Bandwidth Limitations in Separate Absorption, Charge and Multiplication (SACM) Avalanche Photodiodes (APD), CLEO 08, San Jose, USA, 4-9 May

142 F. Römer, B. Witzigmann Spectral and Spatial Emission Properties of Photonic Crystal Cavities, Photonics West, San Jose, CA, USA, Jan 2008 R.G. Veprek, S. Steiger, B. Witzigmann Ellipticity and Spurious Solutions in k.p Calculations of III-Nitride Nanostructures, 8th International Conference on Numerical Simulation of Optoelectronic Devices, Nottingham, UK, 1-5 Sep 2008 R.G. Veprek, S. Steiger, B. Witzigmann GaN based Nanocolumns: Impact of Strain Engineering on the Electro-Optical Performance, International Workshop on Nitride semiconductors IWN 2008, Montreux, Switzerland, 6-10 Oct 2008 B. Witzigmann, F. Römer Physics and Simulation of Photonic Crystal Purcell Light Emitters, SPIE Photonics West Conference, Physics and Simulation of Optoelectronic Devices, Invited Talk, San Jose, CA, USA, Jan 2008 Physical Characterization G. Banckaert, M. Mermet-Guyennet, A. Castellazzi A Study of Pressed Contact Technology on IGBT Devices between -40 degc and +200 degc, 5th International Conference on Integrated Power Electronics Systems, Nuerenberg, Germany, Mar 2008 A. Castellazzi, E. Batista, M. Ciappa, J.M. Dienot, M. Mermet-Guyennet, W. Fichtner Full Electro-Thermal Model of a 6.5kV Field-Stop IGBT Module, Poster Presentation at the 39th IEEE Power Electronics Specialists Conference, Rhodes, Greece, Jun 2008 A. Castellazzi, M. Ciappa Multi-Level Electro-Thermal Modeling for Circuit Simulation of Packaged Power Devices, 11th IEEE Workshop on Control and Modeling for Power Electronics (COMPEL), Zurich, Switzerland, Aug 2008 A. Castellazzi, M. Ciappa Novel Simulation Approach for Transient Analysis and Reliable Thermal Management of Power Devices, 19th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF), Maastricht, The Netherlands, 29 Sep - 2 Oct 2008 A. Castellazzi, M. Ciappa, M. Mermet-Guyennet, W. Fichtner VHDL-AMS Simulation of Integrated Power Systems: a Unified Solution for Multi-Domain Multi-Level Abstraction Analysis, 5th International Conference on Integrated Power Electronics Systems, Nuernberg, Germany, Mar 2008 M. Ciappa Lifetime Modeling and Prediction of Power Devices (Invited Paper), International Conference on Integration of Power Electronic Systems (CIPS), Nuremberg, Germany, Mar 2008 M. Ciappa Extraction of Accurate Thermal Compact Models for Fast Electro-Thermal Simulation of Power Modules (Invited Paper), International Workshop on Built-in Reliability into Power Electronic Systems, Toulouse, France, Jun 2008 M. Ciappa Lifetime Modeling and Prediction of Power Devices (Invited Paper), International Workshop on Built-in Reliability into Power Electronic Systems, Toulouse, France, Jun 2008 M. Ciappa Reconstruction of Scanning Electron Microscopy Images by Monte Carlo Simulation to Improve the Accuracy of Critical Dimension Measurement in Advanced CMOS Devices (Invited Paper), International Workshop on Remote Scanning Electron Microscopy, Pula, Italy, Oct 2008 L. Dalessandro, N. Karrer, M. Ciappa, A. Castellazzi, W. Fichtner Online and Offline Isolated Current Monitoring of Parallel Switched High-Voltage Multi-Chip IGBT Modules, Poster Presentation at the 39th IEEE Power Electronics Specialists Conference (PESC 2008), Rhodes, Greece, Jun 2008 M. Mermet-Guyennet, A. Castellazzi, P. Lasserre, J. Saiz 3D Integration of Power Semiconductor Devices based on Surface Bump Technology, 5th International Conference on Integrated Power Electronics Systems, Nuernberg, Germany, Mar 2008 L. Vignaux, J. Saiz, A. Castellazzi, P. Ladoux VHDL-AMS Traction Drive Model Including a 3D Description of Thermal Effects., the 19th International Symposium on Power Electronics, Electrical Drives, Automation and Motion (SPEEDAM 2008), Ischia, Italy, Jun 2008 Bio-Electromagnetics and Electromagnetic Compatibility B.B. Arnetz, L. Hillert, T. Akerstedt, A. Lowden, N. Kuster, S. Ebert, C. Boutry, S. Moffat, M. Berg, C. Wiholm Effects from 884 MHz Mobile Phone Radiofrequency on Brain Electrophysiology, Sleep, Cognition, and Well-being, XIX General Assembly of the International Union of Radio Science (URSIGA), Chicago, IL, USA, 7-16 Aug

143 S. Benkler, N. Chavannes, N. Kuster Real-world Low Frequency Simulations of Full Body Interactions, 30th Annual Meeting of the Bioelectromagnetics Society (BEMS 2008), San Diego, CA, USA, 7-13 Jun 2008 S. Benkler, N. Chavannes, N. Kuster Highly Detailed Low Frequency Full Body Electromagnetic Field Simulations in 3-D, XIX General Assembly of the International Union of Radio Science (URSIGA), Chicago, IL, USA, 7-16 Aug 2008 S. Benkler, E. Neufeld, N. Chavannes, N. Kuster Efficient 3-D Low Frequency Electromagnetic Simulations of Detailed Body Models as Basis for RF Ablation Simulations, Proceedings of the 1st ESHO Educational School on Clinical Hyperthermia and the 10th International Congress on Hyperthermic Oncology, Munich, Germany, 7-12 Apr 2008 G. Bit-Babik, A. Faraone, C. Penney, T. Wittig, A. Prokop, A. Christ, J. Shen, J. Chen Standardization of Computational Techniques for Compliance Evaluation of the Human Exposure in Automotive Environments: Bystander and Passenger RF Exposure from Mobile Radios with Vehicle-mount Antennas, 2nd International Conference on Bioinformatics and Biomedical Engineering (icbbe), Shanghai, China, May 2008 E. Cabot, M. Capstick, S. Kuehn, A. Christ, N. Kuster Accurate Assessment of the MRI Benchmark for Implanted Leads, 30th Annual Meeting of the Bioelectromagnetics Society (BEMS 2008), San Diego, CA, USA, 7-13 Jun 2008 E. Cabot, A. Christ, N. Kuster Whole Body and Local SAR in Anatomical Phantoms Exposed to RF Fields from Birdcage Coils, XIX General Assembly of the International Union of Radio Science (URSIGA), Chicago, IL, USA, 7-16 Aug 2008 M. Capstick, N. Kuster, S. Kühn, V. Berdinas-Torres, J. Ladbury, G. Koepke, D. McCormick, J. Gauger, R. Melnick A Radio Frequency Reverberation Chamber Exposure System for Rodents, XIX General Assembly of the International Union of Radio Science (URSIGA), Chicago, IL, USA, 7-16 Aug 2008 M. Capstick, N. Kuster, S. Kühn, V. Berdinas-Torres, J. Ladbury, G. Koepke, D. McCormick, J. Gauger, R. Melnick A Radio Frequency Radiation Reverberation Chamber Exposure System for Rodents, Cranfield University Multi-Strand Conference, Bedfordshire, UK, 6-9 May 2008 N. Chavannes, P. Futter, S. Schild SEMCAD X Computational (R)evolution, 2008 IEEE International Symposium on Antennas and Propagation (APS/URSI), San Diego, CA, USA, 9 Jul 2008 E. Cherubini, N. Chavannes, N. Kuster Realistic Skeleton Based Deformation of High-resolution Anatomical Human Models for Electromagnetic Simulation, 30th Annual Meeting of the Bioelectromagnetics Society (BEMS 2008), San Diego, CA, USA, 7-13 Jun 2008 E. Cherubini, N. Chavannes, N. Kuster Realistic Skeleton Based Deformation of High-resolution Anatomical Human Models for Electromagnetic Simulations, XIX General Assembly of the International Union of Radio Science (URSIGA), Chicago, IL, USA, 7-16 Aug 2008 A. Christ, M.C. Gosselin, M. Murbach, S. Ryf, M. Christopoulou, E. Neufeld, C. Gabriel, A. Peyman, N. Kuster Age Dependent Changes in SAR and Temperature Distribution Induced in the User s Head by Cellular Phones, 30th Annual Meeting of the Bioelectromagnetics Society (BEMS), San Diego, CA, USA, 7-13 Jun 2008 A. Christ, G. Schmid, M. Bouterfas, R. Überbacher, M. Zefferer, E. Neufeld, N. Kuster Development of Anatomical CAD Models of Children for the Assessment of EM Field Exposure, 30th Annual Meeting of the Bioelectromagnetics Society (BEMS), San Diego, CA, USA, 7-13 Jun 2008 M. Christen, O. Schenk, P. Messmer, E. Neufeld, H. Burkhart Accelerating Stencil-based Computations by Increased Temporal Locality on Modern Multi- and Many-core Architectures, First International Workshop on New Frontiers in High-performance and Hardware-aware Computing (HipHaC 08) held in conjunction with the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41), Lake Como, Italy, 8 Nov 2008 M. Christopoulou, M. Murbach, A. Christ, P. Crespo-Valero, M. Zefferer, S. Kuehn, P. Achermann, N. Kuster Exposure Systems for Testing Hypotheses of Site and Mechanism of Interaction in the Human Brain, 30th Annual Meeting of the Bioelectromagnetics Society (BEMS), San Diego, CA, USA, 7-13 Jun 2008 P. Crespo-Valero, N. Chavannes, N. Kuster Efficient and Versatile Implementation of Different Spatial-averaging Schemes for SAR, 30th Annual Meeting of the Bioelectromagnetics Society (BEMS), San Diego, CA, USA, 7-13 Jun 2008 P. Crespo-Valero, N. Chavannes, N. Kuster Efficient Implementation of Cubical, Spherical and Contiguous Schemes for SAR Averaging, XIX General Assembly of the International Union of Radio Science (URSIGA), Chicago, IL, USA, 7-16 Aug 2008 P. Crespo-Valero, N. Chavannes, N. Kuster Efficient Implementation of SAR Averaging Techniques in Computational Dosimetry for Highly Detailed Human Models, XIX General Assembly of the International Union of Radio Science (URSIGA), Chicago, IL, USA, 7-16 Aug 2008 T. Gohil, K. Muralidhar, D. Szczerba Simulation of Oscillatory Flow in an Aortic Bifurcation, Fluid Mechanics and Fluid Power Conference 2008, Bangalore, India, Dec

144 M.C. Gosselin, A. Christ, M. Murbach, S. Ryf, S. Kühn, M. Christopoulou, E. Neufeld, C. Gabriel, A. Peyman, N. Kuster Influences of Age Dependent Tissue Parameters and Anatomical Structures on SAR and Temperature Increase in the Heads of Cellular Phone Users, XIX General Assembly of the International Union of Radio Science (URSIGA), Chicago, IL, USA, 7-16 Aug 2008 L. Hillert, A. Torbjörn, A. Lowden, M. Anderson, H. Svensson, C. Wiholm, N. Kuster, B.B. Arnetz Factors Affecting Radiofrequency Power Output of Mobile Phones, 30th Annual Meeting of the Bioelectromagnetics Society, San Diego, CA, USA, 7-13 Jun 2008 S. Kühn, M.C. Gosselin, A. Christ, M. Zefferer, E. Cherubini, N. Kuster Experimental Evaluation of the SAR Induced in a Head Phantom of a Three Year Old Child, 30th Annual Meeting of the Bioelectromagnetics Society (BEMS), San Diego, CA, USA, 7-13 Jun 2008 S. Kühn, N. Kuster Exposure Variability as a Function of Technology, NRP57 - Dosimetry Meets Epidemiology Workshop, Zurich, Zurich, Switzerland, 11 Jan 2008 M. Kelsh, A.R. Sheppard, M. Shum, L. Erdreich, E. Lau, N. Kuster, M. McNeely Factors Affecting Radiofrequency Power Output of Mobile Phones, 30th Annual Meeting of the Bioelectromagnetics Society (BEMS 2008), San Diego, CA, USA, 7-13 Jun 2008 S. Kuehn, W. Jennings, M.C. Gosselin, A. Christ, N. Kuster Inconsistency of Reference Values and Spatial Averaging of IEEE/ICNIRP Guidelines with Basic Restrictions, 30th Annual Meeting of the Bioelectromagnetics Society (BEMS 2008), San Diego, CA, USA, 7-13 Jun 2008 N. Kuster Health Aspects of the Proliferation of Wireless Communications in a Deregulated Arena, XXIX General Assembly of the International Union of Radio Science (URSIGA), Chicago, IL, USA, 7-16 Aug 2008 N. Kuster Latest Progress and Future Needs for Experimental and Numerical Em Field Analysis, Design and Optimization (Invited Paper), KIEES 12th Workshop on Health Effects on EMF and Bioelectromagnetic Environment, Seoul, South Korea, 1 Sep 2008 N. Kuster Does Dosimetry Support the Possibility of Non-thermal Effects? (Invited Paper), 30th Annual Meeting of the Bioelectromagnetics Society (BEMS), San Diego, CA, USA, 7-13 Jun 2008 N. Kuster Physical Aspects of Non-ionizing Radiation Related to Potential Biological Effects, Health Risks from NIR due to Mobile Telephony, Toronto, Canada, 5 May 2008 N. Kuster, S. Kühn, A. Christ Challenges from the Perspective of Dosimetry, NRP57 - Dosimetry Meets Epidemiology Workshop, Zurich, Zurich, Switzerland, 11 Jan 2008 N. Kuster, M. Murbach, M. Christopoulou, S. Kühn, A. Christ Experimental Outcome of Human Provocation Studies Depend on the Design Specifics of the Exposure Setup, XIX General Assembly of the International Union of Radio Science (URSIGA), Chicago, IL, USA, 7-16 Aug 2008 N. Kuster, E. Neufeld Easy-to-use, Real-time & Reliable Hyperthermia Treatment Planning: Expectations & Reality, 1st ESHO Educational School on Clinical Hyperthermia and the 10th International Congress on Hyperthermic Oncology, Munich, Germany, 7-12 Apr 2008 N. Kuster, F.J. Nuñez, S. Benkler, N. Chavannes Latest Advances in Hybrid FDTD Approaches (Invited Paper), VI Iberian Meeting on Computational Electromagnetism (EIEC ), Chiclana de la Frontera, Cadiz, Spain, 1 Sep 2008 C.H. Li, E. Ofli, N. Chavannes, E. Cherubini, H.U. Gerber, N. Kuster Effects of Hand Phantom and Different Use Patterns on Mobile Phone Antenna Radiation Performance, IEEE International Symposium on Antennas and Propagation, San Diego, California, USA, 5-12 Jul 2008 R. McGregor, D. Szczerba, M. von Siebenthal, K. Muralidhar, G. Székely Exploring the Use of Proper Orthogonal Decomposition for Enhancing Blood Flow Images via Computational Fluid Dynamics, Medical Image Computing and Computer-Assisted Intervention - MICCAI 2008, New York, NY, USA, 6-10 Sep 2008 E. Neufeld, N. Chavannes, M. Paulides, G. van Rhoon, N. Kuster Fast (re)-optimization for Hyperthermia: Bringing Treatment Planning Into the Treatment Room, 1st ESHO Educational School on Clinical Hyperthermia and the 10th International Congress on Hyperthermic Oncology, Munich, Germany, 7-12 Apr 2008 E. Neufeld, N. Chavannes, M.M. Paulides, G. van Rhoon, N. Kuster Latest Breakthroughs in Treatment Planning Tools for Hyperthermia (Invited Paper), Annual Meeting of the Bioelectromagnetics Society Winter Workshop (BEMS), Washington, DC, USA, 8 Feb

145 E. Neufeld, N. Chavannes, M.M. Paulides, G. van Rhoon, N. Kuster Fast SAR and Temperature Field (re-)optimization for Hyperthermia: Bringing Treatment Planning Into the Treatment Room, 30th Annual Meeting of the Bioelectromagnetics Society (BEMS), San Diego, CA, USA, 7-13 Jun 2008 E. Neufeld, T. Samaras, N. Chavannes, G. Szekely, N. Kuster From Vessels to Wires and 1-D Boundaries: A Technique for Simulating the Thermal Impact of Thin Structures, 1st ESHO Educational School on Clinical Hyperthermia and the 10th International Congress on Hyperthermic Oncology, Munich, Bavaria, Germany, 7-12 Apr 2008 E. Neufeld, T. Samaras, N. Chavannes, G. Szekely, N. Kuster From Vessels to Wires and 1D Boundaries: A Technique for Simulating the Thermal Impact of Thin Structures, 30th Annual Meeting of the Bioelectromagnetics Society (BEMS), San Diego, CA, USA, 7-13 Jun 2008 F.J. Nunez, P. Futter, W. Jennings, N. Chavannes, N. Kuster Solving EMI by Using SPICE-FDTD CO-SIMULATION Engine for Active Integrated Circuits, IEEE International Symposium on Antennas and Propagation (APS), San Diego, CA, USA, 5-11 Jul 2008 F.J. Nunez, W. Jennings, P. Futter, N. Chavannes, N. Kuster Dispersive Material Model Optimization for FDTD Applications, IEEE International Symposium on Antennas and Propagation (APS), San Diego, CA, USA, 5-11 Jul 2008 M. Oberle System for Hyperthermia Cure of Neck and Head Tumors (HYCUNEHT), CTI Medtech Event, Bern, Switzerland, 2 Sep 2008 E. Ofli, C.H. Li, F. Nunez, N. Chavannes, G. Castillo, N. Kuster Genetic Algorithm Optimization of Mobile Phone Antenna Performance under Real Usage Conditions, IEEE International Symposium on Antennas and Propagation, San Diego, California, USA, 5-12 Jul 2008 M.M. Paulides, J.F. Bakker, E. Neufeld, P.P. Jansen, P.C. Levendag, J. van der Zee, G.C. van Rhoon Application of Hyperthermia in the Head and Neck Using the HYPERcollar, 1st ESHO Educational School on Clinical Hyperthermia and the 10th International Congress on Hyperthermic Oncology, Munich, Germany, 1 Apr 2008 S. Schild, M. Ammann, N. Chavannes, N. Kuster A Fast ADE-FDTD Method for Linear and Nonlinear Dispersion, XVIIth International Workshop on Optical Waveguide Theory and Numerical Modelling, Eindhoven, Netherlands, Jun 2008 S. Schild, M. Ammann, N. Chavannes, N. Kuster A Novel Approach to Model Linear and Nonlinear Dispersion with ADE-FDTD, IEEE Antennas and Propagation Symposium 2008, San Diego, CA, USA, 6-11 Jul 2008 S. Schild, M. Ammann, N. Chavannes, N. Kuster A Novel Approach to Model Linear and Nonlinear Dispersion with ADE-FDTD, IEEE International Symposium on Antennas and Propagation (APS), San Diego, CA, USA, 5-11 Jul 2008 S. Schild, S. Blum, N. Chavannes, N. Kuster Integration of Nonlinear Magnetic Materials in FDTD, IEEE International Symposium on Antennas and Propagation (APS), San Diego, CA, USA, 5-11 Jul 2008 D. Szczerba, B. Lloyd, M. Bajka, G. Székely A Multiphysics Model of Myoma Growth, Computational Science (ICCS 2008), Krakow, Poland, Jun 2008 D. Szczerba, R. McGregor, K. Muralidhar, G. Székely Mechanism and Localization of Wall Failure During Abdominal Aortic Aneurysm Formation, 4th International Symposium on Biomedical Simulation, London, Great Britain, 7-8 Jul 2008 G.C. van Rhoon, M. De Bruijne, N. Kuster, E. Neufeld, J. Van der Zee Latest Breakthroughs in Treatment Planning Tools for Hyperthermia (Invited Paper), BEMS 2008 Winter Workshop, Washington, DC, USA, 8 Feb 2008 G. van Rhoon, M. Paulides, J. Bakker, N. Kuster, E. Neufeld, C. van der Zee, P. Levendag Hyperthermia Treatment Planning Targets Heating to the Tumor, 27th annual congress of the European Society for Therapeutic Radiology and Oncology (ESTRO), Goeteborg, Sweden, Sep 2008 Microelectronics Design Center H. Kaeslin, N. Felber Why do Electrical Engineering Students Love VLSI Design? (Invited talk), 7th European Workshop on Microelectronics Education (EWME 2008), Budapest, Hungary, May

146 Equipment for Electronic Test and Physical Characterization Verification Systems & Logic Analyzers Digital IC Test System HP83000 F MHz max test frequency, 10 ps edge resolution, 128 bidirectional test channels, 10 K test vector cache, 1 M test vectors, 4 device power supplies. Manufacturer: Hewlett-Packard/Verigy Digital IC Test System HP83000 F330t 330 MHz max test frequency, 6 timing edges & 2 data per period per pin, 256 bidirectional test channels, 4 M test vectors, 4 device power supplies. Manufacturer: Hewlett-Packard/Verigy Hewlett-Packard Tektronix Tektronix Spectrum & Network Analyzers HP16702A, Logic Analysis System, IEEE Tektronix TLA715, Logic Analyzer Tektronix TLS216, 16-Channel Logic Scope, 500MHz 2GS/s, IEEE Signal Analyzer R&S FSQ 26 Frequency range: 20 Hz to 26.5 GHz, 28 MHz demod. BW, 16 Msample IQ memory, TOI +25 dbm typ., P1dB +13 dbm typ., 84 db ACLR/3GPP with noise correction. Manufacturer: Rohde & Schwarz Microwave Vector Network Analyzer HP8720D Frequency range: 50 MHz to 20 GHz, dynamic range up to 105 db, fast-sweeping synthesized source, integrated solidstate switching S-parameter test set. Manufacturer: Hewlett-Packard/Agilent Audio Precision Rhode & Schwarz Rhode & Schwarz Rhode & Schwarz Agilent Hewlett-Packard Hewlett-Packard Hewlett-Packard Scopes Audio Precision System S1, Audio Analyzer R&S FSIQ3, Signal Analyzer, 20Hz - 3.5GHz R&S FSP, Spectrum Analyzer, 9Hz - 7GHz R&S FSEB30, Spectrum Analyzer, 20Hz - 7GHz Agilent 8591E, RF Spectrum Analyzer, 9kHz - 1.8GHz HP89441A, Vector Signal Analyzer, DC-2650MHz HP8751A, Network Analyzer, 5Hz - 500MHz, with HP87511A S-Parameter Set HP8753E, Network Analyzer, 30kHz - 6GHz WaveMaster 808Zi SDA Oscilloscope Bandwidth: 8 GHz, sample rate: 40 GS/s, vertical resolution 8-Bit (11 bit averaging), 4 channels, sensitivity 2mV, Manufacturer: LeCroy Infiniium Series Oscilloscope Bandwidth: 6 (7) GHz, sample rate: 20 GS/s, differential and single-ended, vertical resolution 8-Bit (12 bit averaging), trigger jitter 1.0 ps rms. Manufacturer: Agilent Tektronix TDS6804B, 4-Channel Digital Scope, 8 GHz, 20 GS/s Tektronix TDS784D, 4-Channel Digital Phosphor Scope, 2GHz, 4GS/s Tektronix TDS820, 2-Channel Digitizing Scope, 6GHz Tektronix TDS794D, 4-Channel Digitizing Scope, 2GHz 8GS/s, IEEE Tektronix TDS684A, 4-Channel Digitizing Scope, 1GHz 5GS/s, IEEE Tektronix TDS784, 4-Channel Digitizing Scope, 1GHz 4GS/s, IEEE (2) Function Generators, Signal Sources Vector Signal Generator R&S SMU200A Frequency range: 100 khz to 6 GHz, SSB phase noise typ dbc/hz (f = 1 GHz, 20 khz), ACLR typ. +70 db for 3GPP FDD, I/Q modulator 200 MHz RF BW. Manufacturer: Rohde & Schwarz Vector Signal Generator Agilent E8267C PSG Frequency range: 250 khz to 20 GHz, SSB phase noise -130 dbc/hz (f = 1 GHz, 10 khz), 160 MHz RF modulation bandwidth, internal baseband generator (80 MHz RFBW). Manufacturer: Agilent Hewlett-Packard HP33250A, Function/Arbitrary Waveform Generator, 80MHz Hewlett-Packard HP346A, Noise Source, 10MHz - 18GHz Hewlett-Packard HP346B, Noise Source, 10MHz - 18GHz Marconi Marconi 2042, Low-Noise Signal Generator, 10kHz - 5.4GHz Rhode & Schwarz R&S SML01, RF Signal Generator, 1GHz (3) Rhode & Schwarz R&S SML03, RF Signal Generator, 3.3GHz (3) Rhode & Schwarz R&S SMHU 58, Signal Generator, 100kHz GHz Rhode & Schwarz R&S SMIQ6 RF Vector Signal Generator, 300kHz - 6.4GHz Rhode & Schwarz R&S AMIQ, 2 Channel Arbitrary Waveform Generator, 100MS/s Stanford Research Stanford Research DS360, Low-Noise and -Distortion Function Generator, 200kHz Hewlett-Packard HP80000, 10 Channel Pattern Generator 1 G Bit/s 144

147 Meters Phase Noise Measurement Solution HP5501B Frequency range: 50 khz to 26.5 GHz, offset frequency range: 0.01 Hz to 100 MHz, system noise response: 180 dbc/hz typ. (>10 khz offset). Manufacturer: Hewlett-Packard/Agilent Hewlett-Packard Hewlett-Packard Rhode & Schwarz UDT Power Supplies HP8970B, Noise Figure Meter, 2GHz HP4284A, LCR Meter, 20Hz-1MHz, IEEE R&S NRV D, RF Power Meter UDT S380, 2-Channel Optometer, IEEE Heinzinger Heinzinger LNC , Power Supply, 3kV/20mA FUG FUG HCN , Power Supply, 12,5kV/50mA, IEEE Kikusui Kikusui PAK20-18A, Power Supply, 20V/18A (2) Kikusui Kikusui PAK6-60A, Power Supply, 6V/60A Active Probes, Amplifiers & Attenuators Agilent Agilent 87405A, Preamplifier 22dB, 10MHz - 3GHz Agilent Agilent E2697A, Preamplifier Probe, 7GHz (2) Agilent 1134A InfiniiMax 7 GHz Probe System (2) Agilent E2697A High Impedance Adapter (includes 500 MHz passive probe) (2) Hewlett-Packard HP54701A, Active Probes, DC-2.5GHz, 100kOhm (2) Tektronix P7380 TekConnect 8 GHz Differential Probe Tektronix P7260 TekConnect 6 GHz Single-ended Active Probe (2) Tektronix Tektronix P6015, High-Voltage Probe, 20kV Tektronix Tektronix P6217, FET Probe, DC-4GHz, 100kOhm (2) Tektronix Tektronix AM503, A6302 Current Probe, TM502A Power Rack Tektronix Tektronix AM503A, A6303 Current Probe, TM502A Power Rack Tektronix Tektronix CT1, 5mV/mA Current Transformer (2) Tektronix Tektronix CT2, 1mV/mA Current Transformer (2) Chase Chase CPA 9231 Preamplifier, 9kHz - 1GHz MITEQ MITEQ AMF P RF Amplifier, 100MHz - 8GHz Stanford Research Stanford Research SR560, Low-Noise Preamplifier Stanford Research Stanford Research SR570, Low-Noise Current Preamplifier Rhode & Schwarz R&S, RF Step Attenuator RSH, DC-5.2GHz Physical Characterization Stereoscan 360 Scanning Electron Microscope Tungsten and LaB6 cathode, 70 nm lateral resolution, secondary and backscattered electrons, absorbed current, electron channeling. Accessories: Tracor Northern Series II EDX spectrometer with thin window and Elprog EBIC amplifier. Manufacturer: Cambridge C3230 Emission Microscope S25 detector for the visible range. Time-resolved signal acquisition with 100 ns time resolution. Frequency-resolved signal acquisition by a set of intereference filters. Accessory: Color videoprinter Hitachi VY-300. Manufacturer: Hamamatsu Nanoscope Dimension 3100 Scanning Probe Microscope with Quadrex Extender. Available techniques: contact and tapping mode, lateral force, magnetic force, electric force, scanning capacitance and scanning spreading resistance microscopy. Manufacturer: Digital Instruments FT 1020 Deep-Level Transient Spectroscopy (DLTS) Recorder Capacitance signal 1 MHz at 5 mv with Boonton bridge. Electrical excitation, fast pulse capability down to 10 ns. Liquid nitrogen cryostat. Manufacturer: Cohausz Balzers Balzers SCD 40, Sputter System Froilabo Froilabo A, Thermo System Zivy Mazali A510Q1, Thermo Test Module Cohausz RH2010, Hall Effect Measurement System Schlieter Schlieter 125l, Thermo Chamber Espec SU241, Temperaturprüfschrank, -40 C C Weiss Technik Weiss 305 SB/10Ju40DU, Environmental Testing Chamber Hughes Hughes TVS200, Thermal Video System IIS ESD Transmission Line Tester IIS Key-Tek MiniZap ESD-Simulator and HBM-Network 145

148 Parameter Analyzers Precision Semiconductor Parameter Analyzer 4156C Set and control measurements and stress programs, 0.01 fa display resolution at 10 pa range, 0.2 µv resolution in differential mode, performs quasi-static CV and time-to-breakdown measurements. 2 Systems. Manufacturer: Agilent Hewlett-Packard HP4142B, Modular DC Source/Monitor Tektronix Tektronix Curve Tracer 370 Probers and Utilities Suss Suss PA150, Semi Automatic Prober Suss Suss PSM6, Submicron Prober Temptronic Temptronic Thermo Chuck, 0 C C Temptronic Temptronic TPO4000, Thermo Stream, -60 C C Temptronic Temptronic TPO700A, Thermo Chuck System Alessi Alessi LG2, Green Laser Cutting System Hewlett-Packard HP4085/4084, Switching Matrix/Control Optical Microscopes Nikon Carl Zeiss Carl Zeiss Leica Optical Characterization Lab Nikon Optiphot 66, Stereo Microscope Zeiss Axiophot, Microscope Zeiss Stemi SV8, Stereo Microscope Leica StereoZoom S6E, Stereo Microscope Lightwave Component Analyzer 86030A Fully vectorial S 11, S 12, S 21, and S 22 characterization up to 50GHz, supports E/E, E/O, O/E and O/O measurements, full 2-port calibration, up to 90dB dynamic range. Manufacturer: Agilent Radiometric Goniometer LD8900 Two optical heads covering nm, +-72 field of view, spatial resolution, sensitivity from 100nW to 0.1W, full 3D scan in 10s, supports any laser/led packaging or fixture. Manufacturer: Photon Inc. Agilent Agilent AG 86030A, 50GHz Lightwave Component Analyzer Ando ANDO AQ 6317B, Optical Spectrum Analyzer, 600nm nm Anritsu Anritsu MS9601A, Optical Spectrum Analyzer, 1200nm nm Bruker Vertex 70 FT-IR Spectrometer, nm Coherent Coherent 251, Spectrum Controller & Analyzer (2) Hewlett-Packard HP54754A, 2-Channel Differential TDR Module for HP54750A Agilent Agilent 4156C, Precision Semiconductor Parameter Analyzer Hewlett-Packard HP 8110A, Programmable Current Pulse Generator, 10V 1Hz - 150MHz Hewlett-Packard HP54750A Digitizing Oscilloscope with TDR Module HP54754A Hewlett-Packard HP8563E, Spectrum Analyzer, 27GHz ILX Lightwave ILX LDC-3722, Laser Diode Controller, 50mA ILX Lightwave ILX LDC-3742, Laser Diode Controller, 3000mA ILX Lightwave ILX LDC-3900, Modular Laser Diode Controller, 3000mA ILX Lightwave ILX Lightwave LDX 3412, 200mA Precision Laser Current Source Laser Precision AM-3500, Optical Power Meter Newport Newport 1835-C, Optical Power Meter, 100fW-300W Cascade Cascade 9652-URF, Wafer Probestation Thorlabs Thorlabs Intun TL1300-B, Tunable Laser Source, 1278nm nm Keithley Keithley 2601, Precision Current/Voltage Source 3A, 40V Koheras Koheras SuperK RED, Supercontinuum Source, 600nm nm Advantest Advantest Q8341, Optical Spectrum Analyzer, 350nm nm 146

149 EDA and TCAD Software EDA Software Design tools for the development of Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs), and Printed Circuit Boards (PCBs) for education and research. Integrated EDA Design Flow Circuit Entry Emacs-VHDL Mode: VHDL coding (D,F) Cadence Virtuoso Schematic Editor: Transistor-level and Verilog, VHDL, C entry (A) Altium Designer - Schematic: Schematic editor (P) Simulation Mentor Graphics Modelsim: Mixed-language (VHDL, Verilog, SystemVerilog, SystemC,...) simulation (D,F) Cadence NC-Sim: Mixed-language (VHDL, Verilog, SystemVerilog, SystemC,...) simulation (D,F) Synopsys Saber: Mixed-technology system simulation (A,D,F,P) Matlab: Algorithm-level behavioral simulation (A,D,F,P) Synopsys Design Compiler: RTL synthesis (D) Cadence BuildGates: RTL synthesis (D) Synplicity Synplify Pro: RTL synthesis (F) Synthesis Cadence SoC Encounter: Place and route, GDSII export (D) Cadence Virtuoso Layout Editor: Custom layout drawing, chip finishing (A,D) Xilinx ISE Foundation: Map, place and route, program device (F) Altium Designer - PCB: PCB placement and routing, manufacturing files (P) Backend Design Verification and Test Generation Mentor Graphics Calibre: Design-rule check, layout versus schematic, parasitic extraction (A,D) Cadence Assura: Design-rule check, layout versus schematic, parasitic extraction (A) Synopsys TetraMax: Automatic test pattern generation (D) 147 Abbreviations A: Analog ASIC D: Digital ASIC F: Field Programmable Gate Array (FPGA) P: Printed Circuit Board (PCB)

150 TCAD Software Technology CAD (TCAD) for technology and device development in nanoelectronics and optoelectronics. Commercial tools of Synopsys, Inc. used in research and education. Integrated TCAD Flow Framework Sentaurus Workbench workbench for technology and device development simulation projects to automate large-scale simulation, parameterization of simulations yield optimization and failure analysis sensitivity analysis and design-of-experiments advanced 2D and 3D visualization Library Calibration Library database of SIMS doping profiles to calibrate process model parameters analysis and optimization of process technology Structure Editor Sentaurus Structure Editor 2D and 3D device structure editor meshing engines Process Simulation Sentaurus Process 1D, 2D and 3D process simulator optimizing silicon and compound semiconductor process technologies Sentaurus Lithography E-beam Lithography Optical Lithography EUV Lithography Device Simulation Sentaurus Device advanced multidimensional device simulator electrical, thermal, and optical characteristics of silicon-based and compound semiconductor devices 148

151 Computer Equipment Computers are most relevant tools in teaching and research at IIS. Examples are design of integrated circuits, simulation of circuits, devices and technologies for nanoelectronics, optoelectronics and microsystems, development of application software, and information transfer. Besides optimal reliability and uncompromising performance, homogeneity of the computing environment and user friendliness are also important. To meet these goals, the computing environment uses the operating system Unix (Linux, Solaris, Mac OS X), networking with NFS V3 and V4 and CIFS (samba), the X-Window System, and the programming languages C++, and Fortran 90/95. Besides the Unix machines in the scientific and technical area, Macintosh computers are widely applied for administration and presentation tasks. A Windows 2003 (x64) terminal server for mainly office applications is also provided. Several Windows PCs are installed for controlling measurement equipment, for lab classes, and for other special applications. Since the teaching and research activities span many areas, computer systems of various vendors (file servers and linux PCs, mostly from Sun Microsytems) are utilized. They range from file servers to standard workstations, compute servers, and workstations with specialized dedicated hardware. The file systems of all computers are assembled via NFS into what appears to the user as a single file system. The networking of IIS computers and external computers is based on switched Gigabit Ethernet which is maintained by the network group of ETH. Important applications in the technical area are EDA (Modelsim, Synopsys, Cadence, Protel, Mentor Graphics), TCAD (Synopsys), as well as publishing and office applications like MS Office and Adobe Creative Suite on Apple Mac computers. Load and number of active processes of an AMD Opteron server (8 Dual Core CPUs, 128 GB memory) used for physicsbased simulations. ( Load = number of processes in running queue) Memory usage of an AMD Opteron server (8 CPU cores, 128 GB memory): total physical memory allocation of all processes. Representative figures of performance of compute servers at the Integrated Systems Laboratory: Relative floating-point performance of one CPU and memory size (Gigabytes) based on a VASP (Vienna Ab Initio Simulation Package) benchmark. The number of machines per architecture is represented by multiple symbols. 149