e-tutorial Semester I UNIT III and IV

Transcription

1 e-tutorial B. Sc. Electronics Semester-I (Choice Based Credit System) Semester I ELECTRONICS-DSC 1A: NETWORK ANALYSIS AND ANALOG ELECTRONICS UNIT III and IV Sections covered: Bipolar Junction Transistor Amplifiers Cascaded Amplifiers Feedback in Amplifiers Sinusoidal Oscillators Unipolar Devices Note: The following reference/text books were used/referred while preparing this e-tutorial: Electronic Devices and Circuit Theory by Robert L. Boylestad and Louis Nashelsky, Pearson. Electronic Devices and Circuits, David A. Bell, 5th Edition 2015, Oxford University Press. Allen Mottershead, Electronic Devices and Circuits, Goodyear Publishing Corporation. Prepared by: Dr. M. Rafiq Beigh Assistant Professor (Electronics) GDC Sumbal Sonawari J&K.

2 Semester I (Electronics DSC 1A) Section III - Bipolar Junction Transistor Bipolar Transistor Basics Simple diodes are made up from two pieces of semiconductor material, either silicon or germanium to form a simple PN-junction and we also learnt about their properties and characteristics. If we now join together two individual signal diodes back-to-back, this will give us two PN-junctions connected together in series that share a common P or N terminal. The fusion of these two diodes produces a three layer, two junction, three terminal device forming the basis of a Bipolar Junction Transistor, or BJT for short. Transistors are three terminal active devices made from different semiconductor materials that can act as either an insulator or a conductor by the application of a small signal voltage. The transistor's ability to change between these two states enables it to have two basic functions: "switching" (digital electronics) or "amplification" (analogue electronics). Then bipolar transistors have the ability to operate within three different regions: 1. Active Region - the transistor operates as an amplifier and Ic = β.ib 2. Saturation - 3. Cut-off - the transistor is "fully-off" operating as a switch and Ic = 0 the transistor is "fully-on" operating as a switch and Ic = I(saturation) Figure 3.1 Typical Bipolar Transistor The word Transistor is an acronym, and is a combination of the words Transfer Varistor used to describe their mode of operation way back in their early days of development. There are two basic types of bipolar transistor construction, PNP and NPN, which basically describes the physical arrangement of the P-type and N-type semiconductor materials from which they are made. The Bipolar Transistor basic construction consists of two PN-junctions producing three connecting terminals with each terminal being given a name to identify it from the other two. These three terminals are known and labeled as the Emitter (E), the Base (B) and the Collector (C) respectively. Bipolar Transistors are current regulating devices that control the amount of current flowing through them in proportion to the amount of biasing voltage applied to their base terminal acting like a current-controlled switch. The principle of operation of the two transistor types PNP and NPN, is exactly the same, the only difference being in their biasing and the polarity of the power supply for each type. Transistor Construction The transistor is a three-layer semiconductor device consisting of either two n- and one p-type layers of material or two p- and one n-type layers of material. The former is called an npn transistor, while the latter is called a pnp transistor. Both are shown in Fig. 3.2 with the proper 1

3 dc biasing. We will find in next section that the dc biasing is necessary to establish the proper region of operation for ac amplification. The emitter layer is heavily doped, the base lightly doped, and the collector only lightly doped. The outer layers have widths much greater than the sandwiched p- or n-type material. For the transistors shown in Fig. 3.2 the ratio of the total width to that of the center layer is 0.150/0.001 = 150:1. The doping of the sandwiched layer is also considerably less than that of the outer layers (typically, 10:1 or less). This lower doping level decreases the conductivity (increases the resistance) of this material by limiting the number of free carriers. For the biasing shown in Fig. 3.2 the terminals have been indicated by the capital letters E for emitter, C for collector, and B for base. An appreciation for this choice of notation will develop when we discuss the basic operation of the transistor. The abbreviation BJT, from bipolar junction transistor, is often applied to this three- terminal device. The term bipolar reflects the fact that holes and electrons participate in the injection process into the oppositely polarized material. If only one carrier is employed (electron or hole), it is considered a unipolar device. The Schottky diode is such a device. Figure 3.2 Types of transistors (a) pnp; (b) npn. Transistor Operation The basic operation of the transistor will now be described using the pnp transistor of Fig. 3.2a. The operation of the npn transistor is exactly the same if the roles played by the electron and hole are interchanged. In Fig. 3.3 the pnp transistor has been redrawn without the base-tocollector bias. Note the similarities between this situation and that of the forward-biased diode. The depletion region has been reduced in width due to the applied bias, resulting in a heavy flow of majority carriers from the p- to the n-type material. Figure 3.3 Forward-biased junction of a pnp transistor Let us now remove the base-to-emitter bias of the pnp transistor of Fig. 3.2a as shown in Fig. 2

4 3.4. Consider the similarities between this situation and that of the reverse-biased diode. Recall that the flow of majority carriers is zero, resulting in only a minority-carrier flow, as indicated in Fig In summary, therefore: One p-n junction of a transistor is reverse biased, while the other is forward biased. In Fig. 3.5 both biasing potentials have been applied to a pnp transistor, with the resulting majority- and minority-carrier flow indicated. Note in Fig. 3.5 the widths of the depletion regions, indicating clearly which junction is forward-biased and which is reverse-biased. As indicated in Fig. 3.5, a large number of majority carriers will diffuse across the forward-biased p-n junction into the n-type material. The question then is whether these carriers will contribute directly to the base current IB or pass directly into the p-type material. Since the sandwiched ntype material is very thin and has a low conductivity, a very small number of these carriers will take this path of high resistance to the base terminal. The magnitude of the base current is typically on the order of micro amperes as compared to milli amperes for the emitter and collector currents. The larger number of these majority carriers will diffuse across the reversebiased junction into the p-type material connected to the collector terminal as indicated in Fig The reason for the relative ease with which the majority carriers can cross the reversebiased junction is easily understood if we consider that for the reverse-biased diode the injected majority carriers will appear as minority carriers in the n-type material. In other words, there has been an injection of minority carriers into the n-type base region material. Combining this with the fact that all the minority carriers in the depletion region will cross the reverse-biased junction of a diode accounts for the flow indicated in Fig Figure 3.4 Reverse-biased junction of a pnp transistor Figure 3.5 M ajority and minority carrier flow of a pnp transistor Applying Kirchhoff s current law to the transistor of Fig. 3.5 as if it were a single node, we obtain IE = IC + IB (3.1) and find that the emitter current is the sum of the collector and base currents. The collector current, however, is comprised of two components the majority and minority carriers as indicated in Fig The minority-current component is called the leakage current and is given the symbol ICO (IC current with emitter terminal Open). The collector current, therefore, is determined in total by Eq. (3.2). (3.2) 3

5 For general-purpose transistors, IC is measured in milli amperes, while ICO is measured in micro amperes or nano amperes. ICO, like IS for a reverse-biased diode, is temperature sensitive and must be examined carefully when applications of wide temperature ranges are considered. It can severely affect the stability of a system at high temperature if not considered properly. Improvements in construction techniques have resulted in significantly lower levels of ICO, to the point where its effect can often be ignored. Common-Base Configuration The notation and symbols used in conjunction with the transistor in the majority of texts are indicated in Fig. 3.6 for the common-base configuration with pnp and npn transistors. The common-base terminology is derived from the fact that the base is common to both the input and output sides of the configuration. In addition, the base is usually the terminal closest to, or at, ground potential. Throughout this text all current directions will refer to conventional (hole) flow rather than electron flow. This choice was based primarily on the fact that the vast amount of literature available at educational and industrial institutions employs conventional flow and the arrows in all electronic symbols have a direction defined by this convention. Recall that the arrow in the diode symbol defined the direction of conduction for conventional current. For the transistor: The arrow in the graphic symbol defines the direction of emitter current (conventional flow) through the device. Figure 3.6 Notation and symbols used with the common-base configuration: (a) pnp transistor; (b) npn transistor. All the current directions appearing in Fig. 3.6 are the actual directions as defined by the choice of conventional flow. Note in each case that IE = IC + IB. Note also that the applied biasing (voltage sources) are such as to establish current in the direction indicated for each branch. That is, compare the direction of IE to the polarity or VEE for each configuration and the direction of IC to the polarity of VCC. To fully describe the behavior of a three-terminal device such as the common- base amplifiers of Fig. 3.6 requires two sets of characteristics one for the driving point or input parameters and the other for the output side. The input set for the common-base amplifier as shown in Fig. 3.7 will relate an input current (IE) to an input voltage (VBE) for various levels of output voltage (VCB). 4

6 Figure 3.7 Input or driving point characteristics for a common-base silicon transistor amplifier The output set will relate an output current (IC) to an output voltage (VCB) for various levels of input current (IE) as shown in Fig The output or collector set of characteristics has three basic regions of interest, as indicated in Fig. 3.8: the active, cutoff, and saturation regions. The active region is the region normally employed for linear (undistorted) amplifiers. In particular: In the active region the collector-base junction is reverse-biased, while the base-emitter junction is forward-biased. Figure 3.8 Output or collector characteristics for a common-base transistor amplifier The active region is defined by the biasing arrangements of Fig At the lower end of the active region the emitter current (IE) is zero, the collector current is simply that due to the reverse saturation current ICO, as indicated in Fig The current ICO is so small (microamperes) in magnitude compared to the vertical scale of IC (milli amperes) that it appears on virtually the same horizontal line as IC = 0. The circuit conditions that exist when IE = 0 for the common-base configuration are shown in Fig The notation most frequently used for ICO on data and specification sheets is, as indicated in Fig. 3.9, ICBO. Because of improved construction techniques, the level of ICBO for general-purpose transistors (especially silicon) in the low- and mid- power ranges is usually so low that its effect can be ignored. However, for higher power units ICBO will still appear in the microampere range. In addition, keep in mind that ICBO, like Is, for the diode (both reverse leakage currents) is temperature sensitive. At higher 5

7 temperatures the effect of ICBO may become an important factor since it increases so rapidly with temperature. Note in Fig. 3.8 that as the emitter current increases above zero, the collector current increases to a magnitude essentially equal to that of the emitter current as determined by the basic transistor-current relations. Note also the almost negligible effect of VCB on the collector current for the active region. The curves clearly indicate that a first approximation to the relationship between IE and IC in the active region is given by IC IE (3.3) As inferred by its name, the cutoff region is defined as that region where the collector current is 0A, as revealed on Fig In addition: In the cutoff region the collector-base and base-emitter junctions of a transistor are both reverse-biased. Figure 3.9 Reverse saturation current. The saturation region is defined as that region of the characteristics to the left of VCB = 0V. The horizontal scale in this region was expanded to clearly show the dramatic change in characteristics in this region. Note the exponential increase in collector current as the voltage VCB increases towards 0V. In the saturation region the collector-base and base-emitter junctions are forward-biased. The input characteristics of Fig. 3.7 reveal that for fixed values of collector voltage (VCB), as the base-to-emitter voltage increases, the emitter current increases in a manner that closely resembles the diode characteristics. In fact, increasing levels of VCB have such a small effect on the characteristics that as a first approximation the change due to changes in VCB can be ignored and the characteristics drawn as shown in Fig. 3.10a. If we then apply the piecewiselinear approach, the characteristics of Fig. 3.10b will result. Taking it a step further and ignoring the slope of the curve and therefore the resistance associated with the forward-biased junction will result in the characteristics of Fig. 3.10c. For the analysis to follow in this text the equivalent model of Fig. 3.10c will be employed for all dc analysis of transistor networks. That is, once a transistor is in the on state, the base-to-emitter voltage will be assumed to be the following: VBE = 0.7 V (3.4) In other words, the effect of variations due to VCB and the slope of the input characteristics will be ignored as we strive to analyze transistor networks in a manner that will provide a good approximation to the actual response without getting too involved with parameter variations of less importance. 6

8 Figure 3.10 Developing the equivalent model to be employed for the base-to-emitter region of an amplifier in the dc mode. It is important to fully appreciate the statement made by the characteristics of Fig. 3.10c. They specify that with the transistor in the on or active state the voltage from base to emitter will be 0.7 V at any level of emitter current as controlled by the external network. In fact, at the first encounter of any transistor configuration in the dc mode, one can now immediately specify that the voltage from base to emitter is 0.7 V if the device is in the active region a very important conclusion for the dc analysis to follow. Alpha (a) In the dc mode the levels of IC and IE due to the majority carriers are related by a quantity called alpha and defined by the following equation: (3.5) where IC and IE are the levels of current at the point of operation. Even though the characteristics of Fig. 3.8 would suggest that a = 1, for practical devices the level of alpha typically extends from 0.90 to 0.998, with most approaching the high end of the range. Since alpha is defined solely for the majority carriers, Eq. (3.2) becomes (3.6) For the characteristics of Fig. 3.8 when IE = 0 ma, IC is therefore equal to ICBO, but as mentioned earlier, the level of ICBO is usually so small that it is virtually undetectable on the graph of Fig In other words, when IE = 0 ma on Fig. 3.8, IC also appears to be 0 ma for the range of VCB values. For ac situations where the point of operation moves on the characteristic curve, an ac alpha is defined by: (3.7) 7

9 The ac alpha is formally called the common-base, short-circuit, amplification factor, for reasons that will be more obvious when we examine transistor equivalent circuits. For the moment, recognize that Eq. (3.7) specifies that a relatively small change in collector current is divided by the corresponding change in IE with the collector-to-base voltage held constant. For most situations the magnitudes of aac and adc are quite close, permitting the use of the magnitude of one for the other. Common-Emitter Configuration The most frequently encountered transistor configuration appears in Fig for the pnp and npn transistors. It is called the common-emitter configuration since the emitter is common or reference to both the input and output terminals (in this case common to both the base and collector terminals). Two sets of characteristics are again necessary to describe fully the behavior of the common-emitter configuration: one for the input or base-emitter circuit and one for the output or collector-emitter circuit. Both are shown in Fig The emitter, collector and base currents are shown in their actual conventional current direction. Even though the transistor configuration has changed, the current relations developed earlier for the common-base configuration are still applicable. That is, IE = IC + IB and IC = aie. For the common-emitter configuration the output characteristics are a plot of the output current (IC) versus output voltage (VCE) for a range of values of input current (IB). The input characteristics are a plot of the input current (IB) versus the input voltage (VBE) for a range of values of output voltage (VCE). Figure 3.11 Notation and symbols used with the common-emitter configuration: (a) npn transistor; (b) pnp transistor. 8

10 Figure 3.12 Characteristics of a silicon transistor in the common-emitter configuration: (a) collector characteristics; (b) base characteristics. Note that on the characteristics of Fig the magnitude of IB is in micro amperes, compared to milli amperes of IC. Consider also that the curves of IB are not as horizontal as those obtained for IE in the common-base configuration, indicating that the collector-to-emitter voltage will influence the magnitude of the collector current. The active region for the common-emitter configuration is that portion of the upper-right quadrant that has the greatest linearity, that is, that region in which the curves for IB are nearly straight and equally spaced. In Fig. 3.12a this region exists to the right of the vertical dashed line at VCE(Sat) and above the curve for IB equal to zero. The region to the left of VCE(Sat) is called the saturation region. In the active region of a common-emitter amplifier the collector-base junction is reverse-biased, while the base-emitter junction is forward-biased. You will recall that these were the same conditions that existed in the active region of the common-base configuration. The active region of the common-emitter configuration can be employed for voltage, current, or power amplification. The cutoff region for the common-emitter configuration is not as well defined as for the common-base configuration. Note on the collector characteristics of Fig that IC is not equal to zero when IB is zero. For the common-base configuration, when the input current IE was equal to zero, the collector current was equal only to the reverse saturation current ICO, so that the curve IE = 0 and the voltage axis were, for all practical purposes, one. The reason for this difference in collector characteristics can be derived through the proper manipulation of Eqs. (3.3) and (3.6). That is, Eq. (3.6): IC = aie + ICBO Substitution gives Eq. (3.3): IC = a(ic + IB) + ICBO Rearranging Yields: (3.8) 9

11 If we consider the case discussed above, where IB = 0 A, and substitute a typical value of a such as 0.996, the resulting collector current is the fo llo w in g : If ICBO were 1 µa, the resulting collector current with IB = 0 A would be 250(1 µa) = 0.25 ma, as reflected in the characteristics of Fig For future reference, the collector current defined by the condition IB = 0 µa will be assigned the notation indicated by Eq. (3.9). (3.9) Figure 3.13 Circuit conditions related to ICEO In Fig the conditions surrounding this newly defined current are demonstrated with its assigned reference direction. For linear (least distortion) amplification purposes, cutoff for the common- emitter configuration will be defined by IC = ICEO. In other words, the region below IB = 0 µa is to be avoided if an undistorted output signal is required. When employed as a switch in the logic circuitry of a computer, a transistor will have two points of operation of interest: one in the cutoff and one in the saturation region. The cutoff condition should ideally be IC = 0 ma for the chosen VCE voltage. Since ICEO is typically low in magnitude for silicon materials, cutoff will exist for switching purposes when IB = 0 µa or IC = ICEO for silicon transistors only. For germanium transistors, however, cutoff for switching purposes will be defined as those conditions that exist when IC = ICBO. This condition can normally be obtained for germanium transistors by reverse-biasing the base-to-emitter junction a few tenths of a volt. Recall for the common-base configuration that the input set of characteristics was approximated by a straight-line equivalent that resulted in VBE = 0.7 V for any level of IE greater than 0 ma. For the common-emitter configuration the same approach can be taken. The result supports our earlier conclusion that for a transistor in the on or active region the base-toemitter voltage is 0.7 V. In this case the voltage is fixed for any level of base current. Beta (β) In the dc mode the levels of IC and IB are related by a quantity called beta and defined by the following equation: (3.10) where IC and IB are determined at a particular operating point on the characteristics. For practical devices the level of β typically ranges from about 50 to over 400, with most in the midrange. As for a, β certainly reveals the relative magnitude of one current to the other. For a 10

12 device with a β of 200, the collector current is 200 times the magnitude of the base current. On specification sheets βdc is usually included as hfe with the h derived from an ac hybrid equivalent circuit. The subscripts FE are derived from forward-current amplification and common-emitter configuration, respectively. For ac situations an ac beta has been defined as follows: (3.11) The formal name for βac is common-emitter, forward-current, amplification factor. Since the collector current is usually the output current for a common-emitter configuration and the base current the input current, the term amplification is included in the nomenclature above. Equation (3.11) is similar in format to the equation for aac. The procedure for obtaining aac from the characteristic curves was not described because of the difficulty of actually measuring changes of IC and IE on the characteristics. Equation (3.11), however, is one that can be described with some clarity, and in fact, the result can be used to find aac using an equation to be derived shortly. On specification sheets βac is normally referred to as hfe. Note that the only difference between the notation used for the dc beta, specifically, βdc = hfe, is the type of lettering for each subscript quantity. The lowercase letter h continues to refer to the hybrid equivalent and the fe to the forward current gain in the common-emitter configuration. Relationship between α and β: A relationship can be developed between β and a using the basic relationships introduced thus far. Using β = IC/IB we have IB = IC/ β, and from a = IC/IE we have IE = IC/a. Substituting into IE = IC + IB We have And dividing both sides of the equation by Ic will result in or so that (3.12a) or (3.12b) 11

13 Transistor Amplifying Action Now that the relationship between IC and IE has been established, the basic amplifying action of the transistor can be introduced on a surface level using the network of Fig The dc biasing does not appear in the figure since our interest will be limited to the ac response. For the common-base configuration the ac input resistance determined by the characteristics of Fig. 3.7 is quite small and typically varies from 10 to 100 Ω. The output resistance as determined by the curves of Fig. 3.8 is quite high (the more horizontal the curves the higher the resistance) and typically varies from 50 KΩ to 1 MΩ (100 KΩ for the transistor of Fig. 3.14). The difference in resistance is due to the forward-biased junction at the input (base to emitter) and the reverse-biased junction at the output (base-to-collector). Using a common value of 20Ω for the input resistance, we find that Figure 3.14 Basic voltage amplification action of the common-base configuration The Voltage amplification is Typical values of voltage amplification for the common-base configuration vary from 50 to 300. The current amplification (IC/IE ) is always less than 1 for the common-base configuration. This latter characteristic should be obvious since IC = a IE and a is always less than 1. The basic amplifying action was produced by transferring a current I from a low- to a highresistance circuit. The combination of the two terms in italics results in the label transistor; that is, transfer + resistor transistor 12

14 Q point or Quiescent or Operating point of BJT Q-point is an acronym for quiescent point. Q-point is the operating point of the transistor (ICQ,VCEQ) at which it is biased. The concept of Q-point is used when transistor act as an amplifying device and hence is operated in active region of input output characteristics. To operate the BJT at a point it is necessary to provide voltages and currents through external sources. Importance of Q point in transistor Normally whatever signals we want to amplify will be of the order of millivolts or less. If we directly input these signals to the amplifier they will not get amplified as transistor needs voltages greater than cut in voltages for it to be in active region. Only in active region of operation transistor acts as an amplifier. So we can establish appropriate DC voltages and currents through BJT by external sources so that BJT operates in active region and superimpose the AC signals to be amplified. The DC voltage and current are so chosen that the transistor remains in active region for entire AC signal excursion. All the input AC signal variations happen around Q-point. Q-point is generally taken to be the intersection point of load line with the output characteristics of the transistor. There can be infinite number of intersection points but Q-point is selected in such a way that irrespective of AC input signal swing the transistor remain in active region. DC load line The dc load line is the locus of IC and VCE at which BJT remains in active region i.e. it represents all the possible combinations of IC and VCE for a given amplifier. Procedure to draw DC load line To draw DC load line of a transistor we need to find the saturation current and cutoff voltage. The saturation current is the maximum possible current through the transistor and occurs at the point where the voltage across the collector is minimum. The cutoff voltage is the maximum possible voltage across the collector and occurs at zero collector current. A common emitter amplifier is shown in the figure below. The biasing and blocking capacitors acts as open circuit for DC signals hence can be represented by open circuit terminals. The DC equivalent of amplifier is shown in the figure below. 13

15 DC equivalent of Voltage divider bias circuit of BJT From the DC equivalent circuit, by applying Kirchhoff s voltage law in collector loop: VCE = Vcc Rc Ic (Eqn 3.13) The two points on the line are found as follows: Cutoff point: To find the cutoff point equate the collector current to zero (actually in cutoff the collector current is ICO which will be of micro amperes order and hence can be assumed to be zero). In Eqn 3.13 equating Ic to zero the cutoff point is (Vcc, 0). Saturation point: To find the saturation point equate the collector voltage to zero (actually in saturation the collector voltage will be around 0.2 Volts which is small and hence can be assumed to be zero). In Eqn 3.13 equating VCE to zero the cutoff point is (0, Vcc/Rc). (Vcc, 0) is cut off point where transistor enters into cut off region from active region and (0, Vcc/Rc) is saturation point where the transistor enters saturation region. DC load line AC load line DC load line analysis gives the variation of collector currents and voltage for static situation of Zero AC voltage. The ac load line tells us the maximum possible output voltage swing for a given common-emitter amplifier i.e. the ac load line will tell us the maximum possible peakto-peak output voltage VCE(cut off) for a given amplifier. 14

16 For AC input signal frequencies the biasing capacitors are chosen such that they acts as short circuits and as open circuits for DC voltages. Hence the AC signal equivalent circuit is shown in the figure below along with the AC load line. AC equivalent circuit of CE amplifier AC load line From the AC equivalent circuit we will get: VCE = (Rc RL) Ic The AC output VCE can have at most VCEQ (since normally the quiescent point is chosen in such a way that the maximum input signal excursion is symmetrical on both negative and positive half cycles i.e. Vmax = +VCEQ and Vmin = -VCEQ so that the transistor stays in active region for entire input signal excursion), hence the maximum current for that corresponding VCEQ is VCEQ / (Rc RL). Also output collector current can be at most Icq hence the maximum voltage for that corresponding ICQ is ICQ(Rc RL). Hence by adding quiescent currents the end points of AC load line are Ic(sat) = ICQ+ VCEQ/(Rc RL) and VCE(off) = VCEQ+ ICQ (Rc RL) = ICQ+ VCEQ/rc and VCE(off) = VCEQ+ ICQ rc Why stabilization of Operating point is needed? In practice the operating point varies due to the drift in temperature etc. As temperature increases Ico, β, VBE gets affected. The reverse saturation current almost doubles for every 10 degree rise in collector junction temperature. The base to emitter voltage decreases by 2.5 milli Volts for every one degree rise in temperature. Hence the operating point should be stabilized against the variations in temperature so that it remains stable. To achieve this proper biasing circuits are employed. 15

17 Semester I (Electronics DSC 1A) Section IV- Amplifiers Introduction The study or design of a transistor amplifier requires a knowledge of both the dc and ac response of the system. Too often it is assumed that the transistor is a magical device that can raise the level of the applied ac input without the assistance of an external energy source. In actuality, the improved output ac power level is the result of a transfer of energy from the applied dc supplies. The analysis or design of any electronic amplifier therefore has two components: the dc portion and the ac portion. Fortunately, the superposition theorem is applicable and the investigation of the dc conditions can be totally separated from the ac response. However, one must keep in mind that during the design or synthesis stage the choice of parameters for the required dc levels will affect the ac response, and vice-versa. The dc level of operation of a transistor is controlled by a number of factors, including the range of possible operating points on the device characteristics. Once the desired dc current and voltage levels have been defined, a network must be constructed that will establish the desired operating point. Although a number of networks are analysed in this section, there is an underlying similarity between the analysis of each configuration due to the recurring use of the following important basic relationships for a transistor: (4.1) (4.2) (4.3) In most instances the base current IB is the first quantity to be determined. Once IB is known, the relationships of Eqs. (4.1) through (4.3) can be applied to find the remaining quantities of interest. The similarities in analysis will be immediately obvious as we progress through the section. The equations for IB are so similar for a number of configurations that one equation can be derived from another simply by dropping or adding a term or two. Operating Point The term biasing appearing in this text is an all-inclusive term for the application of dc voltages to establish a fixed level of current and voltage. For transistor amplifiers the resulting dc current and voltage establish an operating point on the characteristics that define the region that will be employed for amplification of the applied signal. Since the operating point is a fixed point on the characteristics, it is also called the quiescent point (abbreviated Q-point). By definition, quiescent means quiet, still, inactive. Figure 4.1 shows a general output device characteristic with four operating points indicated. The biasing circuit can be designed to set the device operation at any of these points or others within the active region. The maximum ratings are indicated on the characteristics of Fig. 4.1 by a horizontal line for the maximum collector current ICmax and a vertical line at the maximum collector-to-emitter voltage VCEmax. The maximum power constraint is defined by the curve PCmax in the same figure. At the lower end of the scales are the cutoff region, defined by IB 0 µa and the saturation region, 16

18 defined by VCE VCESat. Figure 4.1 Various operating points within the limits of operation of a transistor The BJT device could be biased to operate outside these maximum limits, but the result of such operation would be either a considerable shortening of the lifetime of the device or destruction of the device. Confining ourselves to the active region, one can select many different operating areas or points. The chosen Q-point often depends on the intended use of the circuit. Still, we can consider some differences among the various points shown in Fig. 4.1 to present some basic ideas about the operating point and, thereby, the bias circuit. If no bias were used, the device would initially be completely off, resulting in a Q-point at A namely, zero current through the device (and zero voltage across it). Since it is necessary to bias a device so that it can respond to the entire range of an input signal, point A would not be suitable. For point B, if a signal is applied to the circuit, the device will vary in current and voltage from operating point, allowing the device to react to (and possibly amplify) both the positive and negative excursions of the input signal. If the input signal is properly chosen, the voltage and current of the device will vary but not enough to drive the device into cutoff or saturation. Point C would allow some positive and negative variation of the output signal, but the peak- to-peak value would be limited by the proximity of VCE = 0V/IC = 0 ma. Operating at point C also raises some concern about the nonlinearities introduced by the fact that the spacing between IB curves is rapidly changing in this region. In general, it is preferable to operate where the gain of the device is fairly constant (or linear) to en- sure that the amplification over the entire swing of input signal is the same. Point B is a region of more linear spacing and therefore more linear operation, as shown in Fig Point D sets the device operating point near the maximum voltage and power level. The output voltage swing in the positive direction is thus limited if the maximum voltage is not to be exceeded. Point B therefore seems the best operating point in terms of linear gain and largest possible voltage and current swing. This is usually the desired condition for small-signal amplifiers but not the case necessarily for power amplifiers. In this discussion, we will be concentrating primarily on biasing the transistor for small-signal amplification operation. One other very important biasing factor must be considered. Having selected and biased the BJT at a desired operating point, the effect of temperature must also be taken into account. 17

19 Temperature causes the device parameters such as the transistor current gain (βac) and the transistor leakage current (ICEO) to change. Higher temperatures result in increased leakage currents in the device, thereby changing the operating condition set by the biasing network. The result is that the network design must also provide a degree of temperature stability so that temperature changes result in minimum changes in the operating point. This maintenance of the operating point can be specified by a stability factor, S, which indicates the degree of change in operating point due to a temperature variation. A highly stable circuit is desirable, and the stability of a few basic bias circuits will be compared. For the BJT to be biased in its linear or active operating region the following must be true: 1. The base emitter junction must be forward-biased (p-region voltage more positive), with a resulting forward-bias voltage of about 0.6 to 0.7 V. 2. The base collector junction must be reverse-biased (n-region more positive), with the reverse-bias voltage being any value within the maximum limits of the device. [Note that for forward bias the voltage across the p-n junction is p-positive, while for reverse bias it is opposite (reverse) with n-positive. This emphasis on the initial letter should provide a means of helping memorize the necessary voltage polarity.] Operation in the cutoff, saturation, and linear regions of the BJT characteristic are provided as follows: 1. Linear-region operation: Base emitter junction forward biased Base collector junction reverse biased 2. Cutoff-region operation: Base emitter junction reverse biased 3. Saturation-region operation: Base emitter junction forward biased Base collector junction forward biased Fixed-Bias Circuit The fixed-bias circuit of Fig. 4.2 provides a relatively straightforward and simple introduction to transistor dc bias analysis. Even though the network employs an npn transistor, the equations and calculations apply equally well to a pnp transistor configuration merely by changing all current directions and voltage polarities. The cur- rent directions of Fig. 4.2 are the actual current directions, and the voltages are de- fined by the standard double-subscript notation. For the dc analysis the network can be isolated from the indicated ac levels by replacing the capacitors with an open- circuit equivalent. In addition, the dc supply VCC can be separated into two supplies (for analysis purposes only) as shown in Fig. 4.3 to permit a separation of input and output circuits. It also reduces the linkage between the two to the base current IB. The separation is certainly valid, as we note in Fig. 4.3 that VCC is connected directly to RB and RC just as in Fig

20 Figure 4.3 dc equivalent of Fig. 4.2 Figure 4.2 Fixed-bias circuit Forward Bias of Base Emitter Consider first the base emitter circuit loop of Fig Writing Kirchhoff s voltage equation in the clockwise direction for the loop, we obtain +V CC - I B R B - V BE = 0 Figure 4.4 Base emitter loop. Note the polarity of the voltage drop across RB as established by the indicated direction of IB. Solving the equation for the current IB will result in the following: (4.4) Equation (4.4) is certainly not a difficult one to remember if one simply keeps in mind that the base current is the current through RB and by Ohm s law that current is the voltage across RB divided by the resistance RB. The voltage across RB is the applied voltage VCC at one end less the drop across the base-to-emitter junction (VBE). In addition, since the supply voltage VCC and the base emitter voltage VBE are constants, the selection of a base resistor, RB, sets the level of base current for the operating point. 19

21 Collector Emitter Loop The collector emitter section of the network appears in Fig. 4.5 with the indicated direction of current IC and the resulting polarity across RC. The magnitude of the col- lector current is related directly to IB through (4.5) It is interesting to note that since the base current is controlled by the level of RB and IC is related to IB by a constant β, the magnitude of IC is not a function of the resistance RC. Change RC to any level and it will not affect the level of IB or IC as long as we remain in the active region of the device. However, as we shall see, the level of RC will determine the magnitude of VCE, which is an important parameter. Figure 4.5 Collector emitter loop Applying Kirchhoff s voltage law in the clockwise direction around the indicated closed loop of Fig. 4.5 will result in the following: VCE + ICRC - VCC = 0 and V CE = V CC - I CR C (4.6) which states in words that the voltage across the collector emitter region of a transistor in the fixed-bias configuration is the supply voltage less the drop across RC. As a brief review of single- and double-subscript notation recall that V CE = V C - V E where VCE is the voltage from collector to emitter and VC and VE are the voltages from collector and emitter to ground respectively. But in this case, since VE = 0V, we have VCE = VC In addition, since VBE = VB - VE 20

22 and VE = 0 V, then VBE = VB Figure 4.6 Measuring VCE and VC Voltage-Divider Bias In the previous bias configurations the bias current ICQ and voltage VCEQ were a function of the current gain (β) of the transistor. However, since β is temperature sensitive, especially for silicon transistors, and the actual value of beta is usually not well defined, it would be desirable to develop a bias circuit that is less dependent, or in fact, independent of the transistor beta. The voltage-divider bias configuration of Fig. 4.7 is such a network. If analyzed on an exact basis the sensitivity to changes in beta is quite small. If the circuit parameters are properly chosen, the resulting levels of ICQ and VCEQ can be almost totally independent of beta. Recall from previous discussions that a Q-point is defined by a fixed level of ICQ and VCEQ as shown in Fig The levels of IBQ will change with the change in beta, but the operating point on the characteristics defined by ICQ and VCEQ can remain fixed if the proper circuit parameters are employed. Figure 4.7 Voltage-divider bias configuration Figure 4.8 Defining the Q-point for the voltage- divider bias configuration As noted above, there are two methods that can be applied to analyze the voltage- divider configuration. The reason for the choice of names for this configuration will become obvious in the analysis to follow. The first to be demonstrated is the exact method that can be applied to any voltage-divider configuration. The second is referred to as the approximate method and can be applied only if specific conditions are satisfied. The approximate approach permits a 21

23 more direct analysis with a savings in time and energy. All in all, the approximate approach can be applied to the majority of situations and therefore should be examined with the same interest as the exact method. Exact Analysis The input side of the network of Fig. 4.7 can be redrawn as shown in Fig. 4.9 for the dc analysis. The Thevenin s equivalent network for the network to the left of the base terminal can then be found in the following manner: B R1 R1 VCC R2 R2 R Figure 4.9 Redrawing the input side of the network of Fig. 4.7 RTh: RTh Figure 4.10 Determining RTh The voltage source is replaced by a short-circuit equivalent as shown in Fig R Th = R 1 ll R 2 (4.7) ETh: The voltage source VCC is returned to the network and the open-circuit Thevenin s voltage of Fig determined as follows: Figure 4.11 Determining Eth Figure 4.12 Inserting the Thevenin equivalent circuit Applying the voltage-divider rule: (4.8) The Thevenin s network is then redrawn as shown in Fig. 4.12, and IBQ can be determined by first applying Kirchhoff s voltage law in the clockwise direction for the loop indicated: Substituting IE = (β + 1)IB and solving for IB yields (4.9) 22

24 Although Eq. (4.9) initially appears different from those developed earlier, note that the numerator is again a difference of two voltage levels and the denominator is the base resistance plus the emitter resistor reflected by (β + 1). Once IB is known, the remaining quantities of the network can be found in the same manner as developed for the emitter-bias configuration. That is, (4.10) The remaining equations for VE, VC, and configuration. VB are also the same as obtained for the emitter-bias Transistor Thermal Runaway: We know that in a transistor, power is dissipated in the collector and hence it is made physically larger than the emitter and base region. As the power is dissipated, there is a chance for the collector base junction temperature to be raised. As the temperature at collector base junction increases, the reverse leakage current ICO increases. This is because ICO arises due to the flow of minority carriers which are thermally generated across reverse biased collector-base junction (reverse biased pn junction). As the temperature increases, thermal generation increases, ICO increases. IC = αie + ICO So, as ICO increases, IC increases. Power dissipated = I2 R So, as collector current increases, power dissipated increases which in turn increases the collector base junction temperature. So the process is cumulative leading eventually to the destruction of the transistor. Again, the solution is a bias scheme with some form of negative feedback to stabilize the bias point. Thermal runaway can also be prevented by using a heat sink. Bias Stabilization The stability of a system is a measure of the sensitivity of a network to variations in its parameters. In any amplifier employing a transistor the collector current IC is sensitive to each of the following parameters: β: increases with increase in temperature VBE : decreases about 7.5 mv per degree Celsius ( C) increase in temperature ICO (reverse saturation current): doubles in value for every 10 C increase in temperature Any or all of these factors can cause the bias point to drift from the designed point of operation. Table 4.1 reveals how the level of ICO and VBE changed with increase in temperature for a particular transistor. At room temperature (about 25 C) ICO = 0.1 na, while at 100 C (boiling point of water) ICO is about 200 times larger at 20 na. For the same temperature variation, β increased from 50 to 80 and VBE dropped from 0.65 to 0.48 V. Recall that IB is quite sensitive to the level of VBE, especially for levels beyond the threshold value. 23

25 T ( C) ICO (na) β VBE(V) X X The effect of changes in leakage current (ICO) and current gain (β) on the dc bias point is demonstrated by the common-emitter collector characteristics of Fig. 4.13a and b. Figure 4.13 shows how the transistor collector characteristics change from a temperature of 25 C to a temperature of 100 C. Note that the significant increase in leakage current not only causes the curves to rise but also an increase in beta, as revealed by the larger spacing between curves. An operating point may be specified by drawing the circuit dc load line on the graph of the collector characteristic and noting the intersection of the load line and the dc base current set by the input circuit. An arbitrary point is marked in Fig. 4.13a at IB = 30 µa. Since the fixedbias circuit provides a base current whose value de- pends approximately on the supply voltage and base resistor, neither of which is affected by temperature or the change in leakage current or beta, the same base current magnitude will exist at high temperatures as indicated on the graph of Fig. 4.13b. As the figure shows, this will result in the dc bias point s shifting to a higher collector current and a lower collector emitter voltage operating point. In the extreme, the transistor could be driven into saturation. In any case, the new operating point may not be at all satisfactory, and considerable distortion may result because of the bias-point shift. A better bias circuit is one that will stabilize or maintain the dc bias initially set, so that the amplifier can be used in a changing-temperature environment. Figure 4.13 Shift in dc bias point (Q-point) due to change in temperature: (a) 25 C; (b) 100 C 24

26 Stability Factors, S(ICO), S(VBE), and S(β) A stability factor, S, is defined for each of the parameters affecting bias stability as listed below: (4.11) (4.12) (4.13) In each case, the delta symbol (Δ) signifies change in that quantity. The numerator of each equation is the change in collector current as established by the change in the quantity in the denominator. For a particular configuration, if a change in ICO fails to produce a significant change in IC, the stability factor defined by S(ICO) = Δ IC / Δ ICO will be quite small. In other words. Networks that are quite stable and relatively insensitive to temperature variations have low stability factors. In some ways it would seem more appropriate to consider the quantities defined by Eqs. ( ) to be sensitivity factors because: The higher the stability factor, the more sensitive the network to variations in that parameter. The study of stability factors requires the knowledge of differential calculus. Our purpose here, however, is to review the results of the mathematical analysis and to form an overall assessment of the stability factors for a few of the most popular bias configurations. Transistor Hybrid Model: Introduction The primary function of a "model" is to predict the behaviour of a device in a particular operating region. At dc the bipolar junction transistor (BJT) and some of its biasing techniques have already been described, see these articles: BJT Biasing Transistor as a Switch The behaviour of the BJT in the sinusoidal ac domain is quite different from its dc domain. At dc the BJT usually works at in either saturation or cut off regions. In the ac domain the transistor works in the linear region and effects of capacitance between terminals, input impedance, output conductance, etc. all have to be accounted for. The small signal ac response can be described by two common models: the hybrid model and re model. The models are equivalent circuits (or combination of circuit elements) that allow methods of circuit analysis to predict performance. 25

27 Transistor Hybrid Model To demonstrate the Hybrid transistor model an ac equivalent circuit must be produced. The left hand diagram below is a single common emitter stage for analysis. Figure 4.14 Single Common Emitter Stage and its Equivalent circuit At ac the reactance of coupling capacitors C1 and C2 is so low that they are virtual short circuits, as does the bypass capacitor C3. The power supply (which will have filter capacitors) is also a short circuit as far as ac signals are concerned. The equivalent circuit is shown above on the right hand diagram. The input signal generator is shown as Vs and the generators source impedance as Rs. As RB1 and RB2 are now in parallel the input impedance will be RB1 RB2. The collector resistor RC also appears from collector to emitter (as emitter is bypassed). See below: The blue rectangle now represents the small signal ac equivalent circuit and can now start work on the hybrid equivalent circuit. The hybrid model has four h-parameters. The "h" stands for hybrid because the parameters are a mix of impedance, admittance and dimensionless units. In common emitter configuration the parameters are: hie - input impedance (Ω) 26

28 hre - reverse voltage ratio (dimensionless) hfe - forward current transfer ratio (dimensionless) hoe - output admittance (Siemen) Note that lower case suffixes indicate small signal values and the last suffix indicates the mode so hie is input impedance in common emitter, hfb would be forward current transfer ration in common base mode, etc. The hybrid model for the BJT in common emitter mode is shown below: The hybrid model is suitable for small signals at mid band and describes the action of the transistor. Two equations can be derived from the diagram, one for input voltage vbe and one for the output ic: vbe = hie ib + hre vce ic = hfe ib + hoe vce If ib is held constant (ib=0) then hre and hoe can be solved: hre = vbe / vce ib = 0 hoe = ic / vce ib = 0 Also if vce is held constant (vce=0) then hie and hfe can be solved: hie = vbe / ib vce = 0 hfe = ic / ib vce = 0 These are the four basic parameters for a BJT in common emitter. Typical values are hre = 1x10-4, hoe typical value 20uS, hie typically 1k to 20k and hfe can be The H- parameters can often be found on the transistor datasheets. The table below lists the four h-parameters for the BJT in common base and common collector (emitter follower) mode. H-parameters are not constant and vary with temperature, collector current and collector emitter voltage. For this reason when designing a circuit the hybrid parameters should be measured under the same conditions as the actual circuit. Below are graphs of the variation of h-parameters with temperature and collector current. 27

29 Table 4.2: h-parameters of Bipolar Junction Transistor Common Base Common Emitter Common Collector Definitions Input Impedance with Output Short Circuit Reverse Voltage Ratio Input Open Circuit Forward Current Gain Output Short Circuit Output Admittance Input Open Circuit Figure. Variation of h-parameters with Collector Current Figure. Variation of h-parameters with Temperature 28

30 Output Characteristic Curves The graph below, shows the output characteristic curves for a 2N3904 transistor in common emitter mode. The output curves are quite useful as they show the change in collector current for a range of collector emitter voltages. Figure. Output Characteristics for 2N3904 In addition, because the base currents are also known, then two small signal parameters, hfe and hoe can be determined straight from the graph. The almost flat portion of the curves, shows that the transistor behaves as a constant current generator. However, in saturation the steepness of the curves (between 0 and 0.4 Vce) show a sharp drop in hfe. This is an important fact to consider, if using the transistor as a switch. Typical h-parameter Values h-parameters are not constant and vary with both temperature and collector current. Typical values for 1mA collector currents are: hie = 1000 Ω hre = 3 x 10-4 hoe = 3 x 10-6S hfe = 250 Examples 1. CE Stage with RE Bypassed The h-parameter model will be applied to a single common emitter (CE) stage with the emitter resistor (RE) bypassed. The model will be used to build equations for voltage gain, current gain, input and output impedance. The circuit is shown below: 29

31 The small signal parameter hrevce is often too small to be considered so the input resistance is just hie. Often the output resistance hoe is often large compared with the collector resistor RC and its effects can be ignored. The h-parameter equivalent model is now simplified and drawn below: Input Impedance Zi The input impedance is the parallel combination of bias resistors RB1 and RB2. As the power supply is considered short circuit at small signal levels then RB1 and RB2 are in parallel. RBB will represent the parallel combination: RBB = RB1 RB2 = RB1 RB2 /( RB1 + RB2) As RBB is in parallel with hie then: Zi = RBB hie Output Impedance Zo As hfeib is an ideal current generator with infinite output impedance, then output impedance looking into the circuit is: Zo = RC Voltage Gain Av Note the ( ) sign in the equation, this indicates phase inversion of the output waveform. 30

32 Vo = -Io RC = -hfe Ib RC as Ib = Vi / hie then Current Gain Ai The current gain is the ratio Io / Ii. At the input the current is split between the parallel branch RBB and hie. So looking at the equivalent h-parameter model again (shown below): The current divider rule can be used for Ib: 31

33 2. CE Stage with RE Un-bypassed The h-parameter model of a common emitter stage with the emitter resistor un-bypassed is now shown. The model will be used to build equations for voltage gain, current gain, input and output impedance. The circuit is shown below: As in the previous example, RB1 and RB2 are in parallel, the bias resistors are replaced by resistance RBB, but as RE is now un-bypassed this resistor appears in series with the emitter terminal. The hybrid small signal model is shown below, once again effects of small signal parameters hrevce and hoe have been omitted. Input Impedance Zi The input impedance Zi is the bias resistors RBB in parallel with the impedance of the base, Zb. Zb = hie + (1 + hfe) RE Since hfe is normally much larger than 1, the equation can be reduced to: Zb = hie + hfe RE Zi = RBB (hie + hfe RE) 32

34 Output Impedance Zo With Vi set to zero, then Ib = 0 and hfeib can be replaced by an open circuit. The output impedance is: Zo = RC Voltage Gain Av Note the sign in the equation, this indicates phase inversion of the output waveform. As Zb = hie + hfe RE often the product hfere is much larger than hie, so Zb can reduced to the approximation: Current Gain Ai The current gain is the ratio Io / Ii. At the input the current is split between the parallel branch RBB and Zb. So looking at the equivalent hparameter model again (shown below): 33

35 The current divider rule can be used for Ib: Example CE Stage The hybrid parameters must be known to use the hybrid model, either from the datasheet or measured. In the above circuit, Zi, Zo, Av, and Ai will now be calculated. Note that this CE stage uses a single bias resistor RB1 which is the value RBB. Input Impedance Zi Zb = hie + (1 + hfe) RE = 0.56k + ( ) 1.2k = k Zi = RB Zb Zi = 270k k = 94.66k 34

36 Output Impedance Zo Zo 5.6k Voltage Gain Av Current Gain Ai Summary: The hybrid model is limited to a particular set of operating conditions for accuracy. If the device is operated at a different collector current, temperature or Vce level from the manufacturer s datasheet then the h parameters will have to be measured for these new conditions. The hybrid model has parameters for output impedance and reverse voltage ratio which can be important in some circuits. Amplifier Types An amplifier receives a signal from some pickup transducer or other input source and provides a larger version of the signal to some output device or to another amplifier stage. An input transducer signal is generally small (a few millivolts from a cassette or CD input, or a few microvolts from an antenna) and needs to be amplified sufficiently to operate an output device (speaker or other power-handling device). In small-signal amplifiers, the main factors are usually amplification linearity and magnitude of gain. Since signal voltage and current are small in a small-signal amplifier, the amount of power-handling capacity and power efficiency are of little concern. A volt- age amplifier provides voltage amplification primarily to increase the voltage of the input signal. Large-signal or power amplifiers, on the other hand, primarily provide sufficient power to an output load to drive a speaker or other power device, typically a few watts to tens of watts. In the present section, we concentrate on those amplifier circuits used to handle large-voltage signals at moderate to high current levels. The main features of a 35

37 large-signal amplifier are the circuit s power efficiency, the maximum amount of power that the circuit is capable of handling, and the impedance matching to the output device. One method used to categorize amplifiers is by class. Basically, amplifier classes represent the amount the output signal varies over one cycle of operation for a full cycle of input signal. A brief description of amplifier classes is provided next. Class A: The output signal varies for a full 360 of the cycle. Figure (a) below shows that this requires the Q-point to be biased at a level so that at least half the signal swing of the output may vary up and down without going to a high-enough voltage to be limited by the supply voltage level or too low to approach the lower supply level, or 0 V in this description. Figure Amplifier operating classes Class B: A class B circuit provides an output signal varying over one-half the input signal cycle, or for 180 of signal, as shown in Fig. (b). The dc bias point for class B is therefore at 0 V, with the output then varying from this bias point for a half- cycle. Obviously, the output is not a faithful reproduction of the input if only one half-cycle is present. Two class B operations one to provide output on the positive- output half-cycle and another to provide operation on the negative-output half-cycle are necessary. The combined half-cycles then provide an output for a full 360 of operation. This type of connection is referred to as pushpull operation. Note that class B operation by itself creates a very distorted output signal since reproduction of the input takes place for only 180 of the output signal swing. Class AB: An amplifier may be biased at a dc level above the zero base current level of class B and above one-half the supply voltage level of class A; this bias condition is class AB. Class AB operation still requires a push-pull connection to achieve a full output cycle, but the dc bias level is usually closer to the zero base current level for better power efficiency, as described shortly. For class AB operation, the output signal swing occurs between 180 and 360 and is neither class A nor class B operation. Class C: The output of a class C amplifier is biased for operation at less than 180 of the cycle and will operate only with a tuned (resonant) circuit, which provides a full cycle of operation for the tuned or resonant frequency. This operating class is therefore used in special areas of tuned circuits, such as radio or communications. Class D: This operating class is a form of amplifier operation using pulse (digital) signals, which are on for a short interval and off for a longer interval. Using digital techniques makes it possible to obtain a signal that varies over the full cycle (using sample-and-hold circuitry) to recreate the output from many pieces of input signal. The major advantage of class D operation 36

38 is that the amplifier is on (using power) only for short intervals and the overall efficiency can practically be very high. Amplifier Efficiency The power efficiency of an amplifier, defined as the ratio of power output to power input, improves (gets higher) going from class A to class D. In general terms, we see that a class A amplifier, with dc bias at one-half the supply voltage level, uses a good amount of power to maintain bias, even with no input signal applied. This results in very poor efficiency, especially with small input signals, when very little ac power is delivered to the load. In fact, the maximum efficiency of a class A circuit, occurring for the largest output voltage and current swing, is only 25% with a direct or series- fed load connection and 50% with a transformer connection to the load. Class B operation, with no dc bias power for no input signal, can be shown to provide a maxi- mum efficiency that reaches 78.5%. Class D operation can achieve power efficiency over 90% and provides the most efficient operation of all the operating classes. Since class AB falls between class A and class B in bias, it also falls between their efficiency ratings between 25% (or 50%) and 78.5%. Table 4.3 summarizes the operation of the various amplifier classes. This table provides a relative comparison of the output cycle operation and power efficiency for the various class types. In class B operation, a push-pull connection is obtained using either a transformer coupling or by using complementary (or quasicomplementary) operation with npn and pnp transistors to provide operation on opposite polarity cycles. While transformer operation can provide opposite cycle signals, the transformer itself is quite large in many applications. A transformer-less circuit using complementary transistors provides the same operation in a much smaller package. TABLE 4.3 Comparison of Amplifier Classes Class A AB B C* D Less than 180 Pulse operation Operating cycle to Power efficiency 25% to 50% Between 25% 78.5% (50%) and 78.5% Typically over 90% *Class C is usually not used for delivering large amounts of power, thus the efficiency is not given here 37

39 Semester I (Electronics DSC 1A) Section V Cascade Amplifiers Cascade Amplifier Cascade amplifier is any two port network constructed from a series of amplifiers, where each amplifier sends its output to the input of the next amplifier. Voltage gain of a single stage amplifier is not sufficient for many applications, so we need to cascade many single stages called multistage amplifiers. The individual gain of each amplifier is multiplied by each other. For e.g. if β1, β2, β3 are the gains of individuals amplifiers then β=β1xβ2xβ3. Two stage R-C Coupled Amplifier A two stage R-C coupled amplifier is shown in figure: When an ac signal is applied to the base of the first transistor, it is amplified and appears across its collector load RC. Now the amplified signal developed across RC is given to the base of the next transistor through a coupling capacitor CC.The second stage again amplifies this signal and the more amplified signal appears across the second stage collector resistance. In this way the cascaded stages amplify the signal and the overall gain is considerably increased. However, the total gain is less than the product of the gains of individual stages. It is because, when a second stage follows the first stage, the effective load resistance of first stage is reduced due to the shunting effect of the input resistance of second stage. This reduces the gain of the stage which is loaded by the next stage. Frequency Response of R-C Coupled Amplifier We make the following assumptions: 1) R1, R2 i.e. bias resistors are large so that they do not affect the AC operation of the circuit. 2) Reactance of emitter bypass is small (negligible). 3) The transistors are identical so that hie and hfe of each is same and does not vary with frequency. 38

40 4) hre and output admittance of transistors are negligibly small (hre & hoe). The figure below shows the frequency response of a typical RC coupled amplifier. You can notice from the above fig. that the voltage gain drops off at low (< 50 Hz) and high (> 20 KHz) frequencies. However, it is uniform over the mid-frequency range i.e. 50 Hz to 20 KHz. This behavior of the amplifier can be explained as follows: 1) At mid frequencies i.e. between 50 Hz to 20 KHz, the voltage gain of the amplifier is constant. The effect of coupling capacitor in this frequency range is such that the voltage gain remains uniform. As the frequency increases in this range, reactance of CC decreases which in result increases the gain. However, at the same time lower reactance means higher loading effect of first stage to the next one and hence gain decreases. Thus, these two factor almost cancel each other, resulting in a uniform gain at this mid frequency. Vo = -hfe Ib ZL Vi = hie Ib (i) (ii) Since ZL= RL hie = hie RL/(hie+RL ) Voltage gain Avm = Vo/Vi =-hfe Ib ZL/hie Ib 39

41 Avm = -hfe Ib hie RL/hie Ib (hie+rl) Avm = -hfe RL/(hie+RL ) So at mid frequency gain is independent of frequency. Gain at Low Frequencies: At low frequencies i.e. below 50Hz the reactance of coupling capacitor (1/wC) is quiet high and can't be neglected and hence a small part of signal will pass from 1 stage to the next. 40

42 Gain at high frequencies: So Avh < Avm 41

43 Semester I (Electronics DSC 1A) Section VI Feedback in Amplifiers Concept of Feedback The process of sending part of the output signal of an is called feedback. There are two types of feedback in called regenerative feedback and negative feedback difference between these two types is Whether the FB input signal. amplifier back to the input of the amplifier amplifiers. They are positive feedback, also also called degenerative feedback. The signal is in phase or out of phase with the Basic Feedback Amplifier Positive Feedback Positive feedback occurs when the feedback signal is in phase with the input signal. A block diagram of an amplifier with positive feedback is shown in figure. Notice that the feedback signal is in phase with the input signal. This means that the feedback signal will add to or "regenerate" the input signal. The result is a larger amplitude output signal than would occur without the feedback. Positive feedback is useful for producing oscillations. For an amplifier with positive feedback, the gain is given by the expression below: The large open loop gain of an op-amp makes it inevitable that the condition A0 B = 1 will be reached and the gain expression becomes infinite. 42

44 Practically speaking, the gain which applies at low signal amplitudes will be reduced until the output amplitude reaches some constant value. However, that limiting value will be independent of input, allowing the circuit to produce a designed output. Negative Feedback Negative feedback is accomplished by adding part of the output signal out of phase with the input signal. The methods of providing negative feedback are similar to those methods used to provide positive feedback. The phase relationship of the feedback signal and the input signal is the only difference. Negative Feedback Equations: 43

45 Advantages of Negative Feedback Amplifier 1. GAIN STABILITY The negative feedback amplifier increases the Gain Stability i.e. the gain will be stable over external or internal variations. 2. NOISE REDUCTION It is impossible to construct an Amplifier without NOISE. By using Negative Feedback amplifier we can reduce the Noise. 3. REDUCTION IN NONLINEAR DISTORTION By the increase in Number of Amplifier stages, Nonlinear Distortion also increases gradually. 4. BANDWIDTH CAN BE INCREASED Negative Feedback Amplifier Decreases the Voltage Gain, the reduction in voltage gain results improved Frequency Band Width. 5. INCREASE IN INPUT IMPEDENCE The amplifier with Negative feedback Increases the Input impedance. Thus we can avoid loading of signal source. 6. DECREASE IN OUTPUT IMPEDENCE The amplifier with Negative feedback reduces the output Impedance. 44

46 Semester I (Electronics DSC 1A) Section VII Sinusoidal Oscillators Sinusoidal Oscillator (Introduction) An electronic oscillator is an electronic circuit that produces a periodic, oscillating electronic signal, often a sine wave or a square wave. Oscillators convert direct current (DC) from a power supply to an alternating current (AC) signal. They are widely used in many electronic devices. The most common form of linear oscillator is an electronic amplifier such as a transistor or Op-amp connected in a feedback loop with its output fed back into its input through a frequency selective electronic filter to provide positive feedback. When the power supply to the amplifier is first switched on, electronic noise in the circuit provides a non-zero signal to get oscillations started. The noise travels around the loop and is amplified and filtered until very quickly it converges on a sine wave at a single frequency. Feedback oscillator circuits can be classified according to the type of frequency selective filter they use in the feedback loop. It consists of amplifier A whose output Vo is fed back into its output through a feedback network. To find the loop gain the feedback loop is considered broken at some point and the output Vo for a give input V is given as Av=Vo/Vi=(Vf/Vi) (Vo/Vf) = βa Barkhausen Criterion for sustained oscillations It is a mathematical condition to determine when a linear electronic circuit will oscillate or it states that the circuit will sustain steady state oscillation only at frequencies for which the loop gain is unity i.e. Aβ=-1. This represents the condition for oscillation. It means that: (i) (ii) The feedback factor or loop gain Aβ = 1 The net phase shift around the loop is 0o (or an integral multiple of 360o ). In other words feedback should be positive. Colpitts Oscillator The Colpitts circuit, like other LC oscillators, consists of a gain device (such as a bipolar junction transistor, field effect transistor, operational amplifier, or vacuum tube) with its output connected to its input in a feedback loop containing a parallel LC circuit (tuned circuit) which functions as a band pass filter to set the frequency of oscillation. A Colpitts oscillator is the electrical dual of a Hartley oscillator, where the feedback signal is taken from an "inductive" voltage divider 45

47 consisting of two coils in series (or a tapped coil). Fig. 1 shows the common-base Colpitts circuit. L and the series combination of C1 and C2 form the parallel resonant tank circuit which determines the frequency of the oscillator. The voltage across C2 is applied to the base-emitter junction of the transistor, as feedback to create oscillations. Fig. 2 shows the common-collector version. Here the voltage across C1 provides feedback. The frequency of oscillation is approximately the resonant frequency of the LC circuit, which is the series combination of the two capacitors in parallel with the inductor. Figure 1: Simple common base Colpitts oscillator Figure 2: Simple common collector Colpitts oscillator (with simplified Biasing) The actual frequency of oscillation will be slightly lower due to junction capacitances and resistive loading of the transistor. As with any oscillator, the amplification of the active component should be marginally larger than the attenuation of the capacitive voltage divider, to obtain stable operation. Thus, a Colpitts oscillator used as a variable frequency oscillator (VFO) performs best when a variable inductance is used for tuning, as opposed to tuning one of the two capacitors. If tuning by variable capacitor is needed, it should be done via a third capacitor connected in parallel to the inductor (or in series as in the Clapp oscillator). 46

48 Figure 3: Colpitts Oscillator The frequency of oscillations for a Colpitts oscillator is determined by the resonant frequency of the LC tank circuit and is given as: where CT is the capacitance of C1 and C2 connected in series and is given as: The configuration of the transistor amplifier in Figure 3 is of a Common Emitter Amplifier with the output signal 180o out of phase with regards to the input signal. The additional 180o phase shift require for oscillation is achieved by the fact that the two capacitors are connected together in series but in parallel with the inductive coil resulting in overall phase shift of the circuit being zero or 360o. The amount of feedback depends on the values of C1 and C2. We can see that the voltage across C1 is the same as the oscillator s output voltage, Vout and that the voltage across C2 is the oscillators feedback voltage. Then the voltage across C1 will be much greater than that across C2. Therefore, by changing the values of capacitors, C1 and C2 we can adjust the amount of feedback voltage returned to the tank circuit. However, large amounts of feedback may cause the output sine wave to become distorted, while small amounts of feedback may not allow the circuit to oscillate. Then the amount of feedback developed by the Colpitts oscillator is based on the capacitance ratio of C1 and C2 and is what governs the the excitation of the oscillator. This ratio is called the feedback fraction and is given simply as: Feedback fraction= C1 /C2 47

49 Phase shift Oscillator In the circuit diagram resistor R1 and the resistor R (close to the base of Q1 in the diagram) gives a voltage divider bias to the transistor Q1. Resistor Rc limits the collector current while Re is meant for thermal stability. Ce is the emitter by-pass capacitor and Cout is the output DC decoupling capacitor. By using more than three RC phase shift stages (like 4 x 45 ) the frequency stability of the oscillator can be further improved. The frequency of the transistor RC phase shift oscillator can be expressed by the equation: Where F is the frequency, R is the resistance, C is the capacitance and N is the number of RC phase shift stages. The RC phase shift oscillator can be made variable by making the resistors or capacitors variable. The common approach is to leave the resistors untouched the three capacitors are replaced by a triple gang variable capacitor. Frequency of oscillation 48

50 RC Phase Angle 49

51 Semester I (Electronics DSC 1A) Section VIII- Unipolar Devices Field Effect Transistor Introduction The field-effect transistor (FET) is a three-terminal device used for a variety of applications that match, to a large extent, those of the BJT transistor. Although there are important differences between the two types of devices, there are also many similarities. The primary difference between the two types of transistors is the fact that the BJT transistor is a currentcontrolled device as depicted in Fig. 8.1a, while the JFET transistor is a voltage-controlled device as shown in Fig. 8.1b. In other words, the current IC in Fig. 8.1a is a direct function of the level of IB. For the FET the current I will be a function of the voltage VGS applied to the input circuit as shown in Fig. 8.1b. In each case the current of the output circuit is being controlled by a parameter of the input circuit in one case a current level and in the other an applied voltage. Figure 8.1 (a) Current-controlled and (b) voltage-controlled amplifiers Just as there are npn and pnp bipolar transistors, there are n-channel and p-channel field-effect transistors. However, it is important to keep in mind that the BJT transistor is a bipolar device the prefix bi- revealing that the conduction level is a function of two charge carriers, electrons and holes. The FET is a unipolar device depending solely on either electron (n-channel) or hole (p-channel) conduction. The term field-effect in the chosen name deserves some explanation. We are all familiar with the ability of a permanent magnet to draw metal filings to the magnet without the need for actual contact. The magnetic field of the permanent magnet has enveloped the filings and attracted them to the magnet through an effort on the part of the magnetic flux lines to be as short as possible. For the FET an electric field is established by the charges present that will control the conduction path of the output circuit without the need for direct contact between the controlling and controlled quantities. There is a natural tendency when introducing a second device with a range of applications similar to one already introduced to compare some of the general characteristics of one versus the other. One of the most important characteristics of the FET is its high input impedance. At a level of 1 to several hundred mega ohms it far exceeds the typical input resistance levels of the BJT transistor configurations - a very important characteristic in the design of linear ac amplifier systems. On the other hand, the BJT transistor has a much higher sensitivity to changes in the applied signal. In other words, the variation in output current is typically a great deal more for BJTs than FETs for the same change in applied voltage. For this reason, typical ac voltage gains for BJT amplifiers are a great deal more than for FETs. In general, FETs are 50

52 more temperature stable than BJTs, and FETs are usually smaller in construction than BJTs, making them particularly useful in integrated-circuit (IC) chips. The construction characteristics of some FETs, however, can make them more sensitive to handling than BJTs. There are three types of FETs: the junction field-effect transistor (JFET), the metal-oxidesemiconductor field-effect transistor (MOSFET) and the metal-semiconductor field-effect transistor (MESFET). The MOSFET category is further broken down into depletion and enhancement types, which are both described. The MOSFET transistor has become one of the most important devices used in the design and construction of integrated circuits for digital computers. Its thermal stability and other general characteristics make it extremely popular in computer circuit design. However, as a discrete element in a typical top-hat container, it must be handled with care. Construction and Characteristics of JFETs As indicated earlier, the JFET is a three-terminal device with one terminal capable of controlling the current between the other two. In our discussion of the BJT transistor the npn transistor was employed through the major part of the analysis and design sections, with a section devoted to the impact of using a pnp transistor. For the JFET transistor the n-channel device will appear as the prominent device, with paragraphs and sections devoted to the impact of using a p-channel JFET. The basic construction of the n-channel JFET is shown in Fig Note that the major part of the structure is the n-type material that forms the channel between the embedded layers of ptype material. The top of the n-type channel is connected through an ohmic contact to a terminal referred to as the drain (D), while the lower end of the same material is connected through an ohmic contact to a terminal referred to as the source (S). The two p-type materials are connected together and to the gate (G) terminal. In essence, therefore, the drain and source are connected to the ends of the n-type channel and the gate to the two layers of p-type material. In the absence of any applied potentials the JFET has two p-n junctions under no-bias conditions. The result is a depletion region at each junction as shown in Fig. 8.2 that resembles the same region of a diode under no-bias conditions. Recall also that a depletion region is that region void of free carriers and therefore unable to support conduction through the region. Figure 8.2 Junction field-effect transistor (JFET) Figure 8.3 Analogy for the JFET control mechanism 51

53 Analogies are rarely perfect and at times can be misleading, but the water analogy of Fig. 8.3 does provide a sense for the JFET control at the gate terminal and the appropriateness of the terminology applied to the terminals of the device. The source of water pressure can be likened to the applied voltage from drain to source that will establish a flow of water (electrons) from the spigot (source). The gate, through an applied signal (potential), controls the flow of water (charge) to the drain. The drain and source terminals are at opposite ends of the n-channel as introduced in Fig. 8.2 because the terminology is defined for electron flow. VGS = 0 V, VDS Some Positive Value In Fig. 8.4, a positive voltage VDS has been applied across the channel and the gate has been connected directly to the source to establish the condition VGS = 0 V. The result is a gate and source terminal at the same potential and a depletion region in the low end of each pmaterial similar to the distribution of the no-bias conditions of Fig The instant the voltage VDD (= VDS) is applied, the electrons will be drawn to the drain terminal, establishing the conventional current ID with the defined direction of Fig The path of charge flow clearly reveals that the drain and source currents are equivalent (ID = IS). Under the conditions appearing in Fig. 8.4, the flow of charge is relatively uninhibited and limited solely by the resistance of the n-channel between drain and source. ID + n-channel Depletion e i e p + VDS n e e VGS = 0 V IS Figure 8.4 JFET in the VGS = 0 V and VDS > 0 V It is important to note that the depletion region is wider near the top of both p- type materials. The reason for the change in width of the region is best described through the help of Fig Assuming a uniform resistance in the n-channel, the resistance of the channel can be broken down to the divisions appearing in Fig The current ID will establish the voltage levels through the channel as indicated on the same figure. The result is that the upper region of the p-type material will be reverse- biased by about 1.5 V, with the lower region only reverse-biased by 0.5 V. Recall from the discussion of the diode operation that the greater the applied reverse bias, the wider the depletion region hence the distribution of the depletion region as shown in Fig The fact that the p-n junction is reverse-biased for the length of the channel results in a gate current of zero amperes as shown in the same figure. The fact that IG = 0A is an important characteristic of the JFET. 52

54 Figure 8.5 Varying reverse-bias potentials across the p-n junction of an n-channel JFET As the voltage VDS is increased from 0 to a few volts, the current will increase as determined by Ohm s law and the plot of ID versus VDS will appear as shown in Fig.8.6. The relative straightness of the plot reveals that for the region of low values of VDS, the resistance is essentially constant. As VDS increases and approaches a level referred to as VP in Fig. 8.6, the depletion regions of Fig. 8.4 will widen, causing a noticeable reduction in the channel width. The reduced path of conduction causes the resistance to increase and the curve in the graph of Fig. 8.6 to occur. The more horizontal the curve, the higher the resistance, suggesting that the resistance is approaching infinite ohms in the horizontal region. If VDS is increased to a level where it appears that the two depletion regions would touch as shown in Fig. 8.7, a condition referred to as pinch-off will result. The level of VDS that establishes this condition is referred to as the pinch-off voltage and is denoted by VP as shown in Fig In actuality, the term pinch-off is a misnomer in that it suggests the current ID is pinched off and drops to 0 A. As shown in Fig. 8.6, however, this is hardly the case - ID maintains a saturation level defined as IDSS in Fig In reality a very small channel still exists, with a current of very high density. The fact that ID does not drop off at pinch-off and maintains the saturation level indicated in Fig. 8.6 is verified by the following fact: The absence of a drain current would remove the possibility of different potential levels through the n-channel material to establish the varying levels of reverse bias along the p-n junction. The result would be a loss of the depletion region distribution that caused pinch-off in the first place. Figure 8.6 ID versus VDS for VGS = 0 V Figure 8.7 Pinch-off (VGS = 0 V, VDS = VP) 53

55 As VDS is increased beyond VP, the region of close encounter between the two depletion regions will increase in length along the channel, but the level of ID remains essentially the same. In essence, therefore, once VDS > VP the JFET has the characteristics of a current source. As shown in Fig. 8.8, the current is fixed at ID = IDSS, but the voltage VDS (for levels > VP) is determined by the applied load. Figure 8.8 Current source equivalent for VGS = 0V, VDS > VP The choice of notation IDSS is derived from the fact that it is the Drain-to-Source current with a Short-circuit connection from gate to source. As we continue to investigate the characteristics of the device we will find that: IDSS is the maximum drain current for a JFET and is defined by the conditions VGS = 0 V and VDS > VP. Note in Fig. 8.6 that VGS = 0V for the entire length of the curve. The next few paragraphs will describe how the characteristics of Fig. 8.6 are affected by changes in the level of VGS. VGS < 0V The voltage from gate to source, denoted VGS, is the controlling voltage of the JFET. Just as various curves for IC versus VCE were established for different levels of IB for the BJT transistor, curves of ID versus VDS for various levels of VGS can be developed for the JFET. For the n-channel device the controlling voltage VGS is made more and more negative from its VGS = 0 V level. In other words, the gate terminal will be set at lower and lower potential levels as compared to the source. In Fig. 8.9 a negative voltage of -1V has been applied between the gate and source terminals for a low level of VDS. The effect of the applied negative-bias VGS is to establish depletion regions similar to those obtained with VGS = 0 V but at lower levels of VDS. Therefore, the result of applying a negative bias to the gate is to reach the saturation level at a lower level of VDS as shown in Fig for VGS = -1V. The resulting saturation level for ID has been reduced and in fact will continue to decrease as VGS is made more and more negative. Note also on Fig how the pinch- off voltage continues to drop in a parabolic manner as VGS becomes more and more negative. Eventually, VGS when VGS = -VP will be sufficiently negative to establish a saturation level that is essentially 0 ma, and for all practical purposes the device has been turned off. In summary: The level of VGS that results in ID = 0 ma is defined by VGS = VP, with VP being a negative voltage for n-channel devices and a positive voltage for p-channel JFETs. On most specification sheets the pinch-off voltage is specified as VGS(off) rather than VP. The region to the right of the pinch-off locus of Fig is the region typically employed in linear amplifiers (amplifiers with minimum distortion of the applied signal) and is commonly referred to as the constant-current, saturation, or linear amplification region. 54

56 Figure 8.9 Application of a negative voltage to the gate of a JFET Figure 8.10 n-channel JFET char ac teristic s with IDSS = 8 ma and VP = -4 V Voltage-Controlled Resistor The region to the left of the pinch-off locus of Fig is referred to as the ohmic or voltagecontrolled resistance region. In this region the JFET can actually be employed as a variable resistor (possibly for an automatic gain control system) whose resistance is controlled by the applied gate-to-source voltage. Note in Fig that the slope of each curve and therefore the resistance of the device between drain and source for VDS < VP is a function of the applied voltage VGS. As VGS becomes more and more negative, the slope of each curve becomes more and more horizontal, corresponding with an increasing resistance level. The following equation will pro- vide a good first approximation to the resistance level in terms of the applied voltage VGS. (8.1) 55

57 where ro is the resistance with VGS = 0 V and rd the resistance at a particular level of VGS. For an n-channel JFET with ro equal to 10 kω (VGS = 0 V, VP = -6 V), Eq. (8.1) will result in 40 kω at VGS = -3 V. p-channel Devices The p-channel JFET is constructed in exactly the same manner as the n-channel device of Fig. 8.2, but with a reversal of the p- and n-type materials as shown in Fig Figure 8.11 p-channel JFET The defined current directions are reversed, as are the actual polarities for the volt- ages VGS and VDS. For the p-channel device, the channel will be constricted by in- creasing positive voltages from gate to source and the double-subscript notation for VDS will result in negative voltages for VDS on the characteristics of Fig. 8.12, which has an IDSS of 6 ma and a pinch-off voltage of VGS = +6 V. Do not let the minus signs for VDS confuse you. They simply indicate that the source is at a higher potential than the drain. Figure 8.12 p-channel JFET characteristics with IDSS = 6 ma and VP = +6 V 56