Part ILectures Bipolar Junction Transistors(BJTs) and Circuits

Transcription

1 University of missan Electronic II, Second year Part ILectures Bipolar Junction Transistors(BJTs) and Circuits Assistant Lecture: 1

2 Bipolar Junction Transistors (BJTs) Bipolar Junction Transistors Basic Construction: The transistor is a three-layer semiconductor device consisting of either two n- and one p-type layers of material or two p- and one n-type layers of material. The former is called an npn transistor, while the latter is called a pnp transistor. Both (with symbols) are shown in Fig The middle region of each transistor type is called the base (B) of the transistor. Of the remaining two regions, one is called emitter (E) and the other is called the collector (C) of the transistor. For each transistor type, a junction is created at each of the two boundaries where the material changes from one type to the other. Therefore, there are two junctions: emitter-base (E-B) junction and collector-base (C-B) junction. The outer layers of the transistor are heavily doped semiconductor materials having widths much greater than those of the sandwiched p- or n-type material. The doping of the sandwiched layer is also considerably less than that of the outer layers (typically 10:1 or less). This lower doping level decreases the conductivity (increases the resistance) of this material by limiting the number of "free" carriers. (Emitter) E n p n C (Collector) E p n p C E-B junction E B (Base) C-B junction C E B C B Fig. 1-1 B The dc biasing is necessary to establish the proper region of operation for ac amplification or switching purposes. Table 8-1 shows the transistor operation regions and the purpose with respect to the biasing of the E-B and C-B junctions. Table 8-1 Operation region Purpose Junctions biasing E-B junction bias C-B junction bias 1 Active region Amplification Forward-biased Reverse-biased 2 Cutoff region Switching Reverse-biased Reverse-biased 3 Saturation region Forward-biased Forward-biased The abbreviation BJT, from bipolar junction transistor, is often applied to this three-terminal device. The term bipolar reflects the fact that holes and electrons participate in the injection process into the oppositely polarized material. If only one carrier is employed (electron or hole), it is considered a unipolar device. Such a device is the field-effect transistor (FET). 2

3 University of Misszn Bipolar Junction Transistors Active Region Operation: The basic operation of the transistor will now be described using the pnp transistor of Fig The operation of the npn transistor is exactly the same if the roles played by the electron and hole are interchanged. When the E-B junction is forward-biased, a large number of majority carriers will diffuse across the forward-biased p-n junction into the n-type material (base). Since the base is very thin and has a low conductivity (lightly doping), a very small number of these carriers will take this path of high resistance to the base terminal. The larger number of these majority carriers will diffuse across the reverse-biased C-B junction into the p-type material (collector). The reason for the relative ease with which the majority carriers can cross the reverse-biased C-B junction is easily understood if we consider that for the reverse-biased diode the injected majority carriers will appear as minority carriers in the n-type base region material. Combining this with the fact that all the minority carriers in the depletion region will cross the reverse-biased junction of a diode accounts for the flow indicated in Fig Fig. 1-2 Applying Kirchhoff's current law to the transistor of Fig. 1-2, we obtain I E IC I B [1.1] The collector current, however, is comprised of two components: the majority and minority carriers as indicated in Fig The minority-current component is called the leakage current and is given the symbol ICO (IC current with emitter terminal Open). The collector current, therefore, is determined in total by Eq. [1.2]. I C = IC majority + ICO minority [1.2] 3

4 Bipolar Junction Transistors Common-Base (CB) Configuration: The common-base configuration with npn and pnp transistors are indicated in Fig The common-base terminology is derived from the fact that the base is common to both input and output sides of the configuration. In addition, the base is usually terminal closest to, or at, the ground potential. I E E C IC I E E C IC VEE VBE B I B VCB VCC VEE VEB B I B VBC VCC Fig. 1-3 In the dc mode the levels of IC and IE due to the majority carriers are related by a quantity called alpha (αdc) and defined by the following equation: dc IC I E [1.3] Where IC and IE are the levels of current at the point of operation and αdc 1, or for practical devices: αdc Since alpha is defined solely for the majority carriers and from Fig. 1-4, Eq. [1.2] becomes IC I E ICBO [1.4] The input (emitter) characteristics for a CB configuration are a plot of the emitter (input) current (IE) versus the base-to-emitter (input) voltage (VBE) for a rage of values of the collectorto-base (output) voltage (VCB) as shown in Fig Since, the exact shape of this IE-VBE carve will depend on the reverse-biasing output voltage, VCB. The reason for this dependency is that the grater the value of VCB, the more readily minority carriers in the base are swept through the C-B junction. The increase in emitter-to-collector current resulting from an increase in VCB means the emitter current will be greater for a given value of base-to-emitter voltage (VBE). Fig. 1-4 Fig

5 Bipolar Junction Transistors The output (collector) characteristics for CB configuration will be a plot of the collector (output) current (IC) versus collector-to-base (output) voltage (VCB) for a range of values of emitter (input) current (IE) as shown in Fig The collector characteristics have three basic region of interest, as indicated in Fig. 1-6, the active, cutoff, and saturation regions. Active region: VCB > 0 and IC I E. Cutoff region: IE = 0 and IC ICBO. Saturation region: Fig. 1-6 VCB < 0 and IC(sat.) I E(sat.). For ac situations where the point of operation moves on the characteristic carve, an ac alpha (αac) is defined by ac IC I E VCB const. [1.5] The ac alpha is formally called the common-base, short-circuit, amplification factor, and for most situations the magnitudes of αac and αdc are quite close, permitting the use of the magnitude of one for other. Fig. 1-7 shows how the common-base output characteristics appear when the effects of breakdown are included. Note the sudden upward swing of each curve at a large value of VCB. The collector-to-base breakdown voltage when IE = 0 (emitter open) is designed BVCBO. Fig. 1-7 Transistor Amplification Action: The basic voltage-amplifying action of the CB configuration can now be described using the circuit of Fig The dc biasing does not appear in the figure since our interest will be limited to the ac response. For the CB configuration, the input resistance between the emitter and the base of a transistor will typically vary from 10 to 100 Ω, while the output resistance may vary from 100 kω to 1 MΩ. The difference in resistance is due to the forward-biased junction at the input (base to emitter) and the reverse-biased junction at the output (base to collector). Using effective values and a common value of 20 Ω for the input resistance, we find that 5

6 Bipolar Junction Transistors Ii / Ri 200mV / 20Ω 10mA. If we assume for the moment that αac = 1 (Ic = Ie), I L Ii 10mA and VL I L R (10mA)(5kΩ) 50V. The voltage amplification is Fig. 1-8 Av VL / 50V / 200mV 250. Typical values of voltage amplification for the common-base configuration vary from 50 to 300. The current amplification (IC/IE) is always less than 1 for the CB configuration. This latter characteristic should be obvious since IC = αie and α is always less than 1. The basic amplifying action was produced by transferring a current I from a low-to a high-resistance circuit. The combination of the two terms in italics results in the label transistor; that is, transfer + resistor transistor. Common-Emitter (CE) Configuration: The common-emitter configuration with npn and pnp transistors are indicated in Fig The external voltage source VBB is used to forward bias the E-B junction and the external voltage source VCC is used to reverse bias C-B junction. The magnitude of VCC must be greater than VBB to ensure the C-B junction remains reverse biased, since, as can be seen in the Fig. 1-9, VCB VCC VBB. IC IC C C VBB I B VCB B VBE E VCE I E VCC VBB I B B VBC VEB E VEC I E VCC Fig. 1-9 From Eqs. [1.1] and [1.4], we obtain IC (IC I B ) ICBO Rearranging yields IC I B I CBO 1 1 From Fig. 1-10, Eq. [1.6] becomes [1.6] ICEO ICBO 1- IB 0 [1.7] Fig

7 Bipolar Junction Transistors In the dc mode the levels of IC and IB are related by a quantity called beta (βdc) and defined by the following equation: βdc IC I B [1.8] Where IC and IB are the levels of current at the point of operation. For practical devices the levels of βdc typically ranges from about 50 to over 500, with most in the mid range. On specification sheets βdc is usually included as hfe with h derived from an ac hybrid equivalent circuit. For ac situation an ac beta (βac) has been defined as follows: β ac IC I B VCE const. [1.9] The formal name for βac is common-emitter, forward-current, amplification factor and on specification sheets βac is usually included as hfe. A relationship can be developed between β and α using the basic relationships introduced thus far. Using β IC / I B we have I B IC / β, and from IC / I E we have I E IC /. Substituting into I E IC I B we have IC / IC IC / β and dividing both sides of the equation by IC will result in 1/ 1 1/ β or β β (β 1) so that Β β 1 or β 1 [1.10] In addition, recall that ICEO ICBO /(1 ) but using an equivalence of 1/(1 ) β 1 derived from the above, we find that ICEO (β 1)ICBO or ICEO βicbo [1.11] Beta is particularly important parameter because it provides a direct link between current levels of the input and output circuits for CE configuration. That is, IC βi B ICEO βi B [1.12] and since I E IC I B βi B I B we have I E (β 1)I B [1.13] 7

8 Bipolar Junction Transistors The input (base) characteristics for the CE configuration are a plot of the base (input) current (IB) versus the base-to-emitter (input) voltage (VBE) for a range of values of collector-to-emitter (output) voltage (VCE) as shown in Fig Note that IB increases as VCE decreases, for a fixed value of VBE. A large value of VCE results in a large reverse bias of the C-B junction, which widens the depletion region and makes the base smaller. When the base is smaller, there are fewer recombinations of injected minority carriers and there is a corresponding reduction in base current (IB). Fig Fig The output (collector) characteristics for CE configuration are a plot of the collector (output) current (IC) versus collector-to-emitter (output) voltage (VCE) for a range of values of base (input) current (IB) as shown in Fig The collector characteristics have three basic region of interest, as indicated in Fig. 1-12, the active, cutoff, and saturation regions. Active region: IB > 0 and IC βi B. Cutoff region: IB = 0 and IC ICEO. Saturation region: VCE 0 and I B(sat.) IC(sat.) / β. Common-Collector (CC) Configuration: The third and final transistor configuration is the common-collector configuration, shown in Fig with npn and pnp transistors. The CC configuration is used primarily for impedance-matching purposes since it has a high input impedance and low output impedance, opposite to that which is true of the common-base and common-emitter configurations. From a design viewpoint, there is no need for a set of common-collector characteristics to choose the circuit parameters. The circuit can be designed using the common-emitter characteristics. For all practical purposes, the output characteristics of the CC configuration are the same as for the CE configuration. For the CC configuration the output characteristics are a plot of emitter (output) current (IE) versus collector-to-emitter (output) voltage (VCE), for a range of values of base (input) 8

9 Bipolar Junction Transistors current (IB). The output current, therefore, is the same for both the common-emitter and common-collector characteristics. There is an almost unnoticeable change in the vertical scale of IC of the common-emitter characteristics if IC is replaced by IE for the common-collector characteristics (since 1, I E IC ). I E I E VBB I B B VBE VCB C E VCE IC VCC VBB I B B VEB VBC C E VEC IC VCC Fig Transistor Casing and Terminal Identification: Whenever possible, the transistor casing will have some marking to indicate which leads are connected to the emitter, collector, or base of a transistor. A few of the methods commonly used are indicated in Fig Exercises: Fig Given an αdc of 0.998, determine IC if IE = 4 ma. 2. Determine αdc if IE = 2.8 ma and IB = 20 µa. 3. Find IE if IB = 40 µa and αdc is Given that αdc = 0.987, determine the corresponding value of β. 5. Given βdc = 120, determine the corresponding value of α. 6. Given that βdc = 180 and IC = 2.0 ma, find IE and IB. 7. A transistor has ICBO = 48 na and α = i. Find β and ICEO. ii. Find its (exact) collector current (IC) when IB = 30 μa. iii. Find the approximate collector current, neglecting leakage current. 9

10 DC Biasing Circits of BJTs DC Biasing Circuits of BJTs Basic Concepts: The analysis or design of a transistor amplifier requires a knowledge of both the dc and ac response of the system. Too often it is assumed that the transistor is a magical device that can raise the level of the applied ac input without the assistance of an external energy source. In actuality, the improved output ac power level is the result of a transfer of energy from the applied dc supplies. The analysis or design of any electronic amplifier therefore has two components: the dc portion and the ac portion. Fortunately, the superposition theorem is applicable and the investigation of the dc conditions can be totally separated from the ac response. However, one must keep in mind that during the design or synthesis stage the choice of parameters for the required dc levels will affect the ac response, and vice versa. The term biasing appearing in the title of this lecture is an all-inclusive term for the application of dc voltages to establish a fixed level of current and voltage. For transistor amplifiers the resulting dc current and voltage establish an operating point on the characteristics that define the region that will be employed for amplification of the applied signal. Since the operating point is a fixed point on the characteristics, it is also called the quiescent point (abbreviated Q-point). By definition, quiescent means quiet, still, inactive. Fig. 2-1 shows a general output device characteristic with four operating points indicated. The biasing circuit can be designed to set the device operation at any of these points or others within the active region. The maximum ratings are indicated on the characteristics of Fig. 2-1 by a horizontal line for the maximum collector current ICmax and a vertical line at the maximum collector-to-emitter voltage VCEmax. The maximum power constraint is defined by the curve PCmax in the same figure. At the lower end of the scales are the cutoff region, defined by IB 0 μa, and the saturation region, defined by VCE VCE(sat). Fig

11 DC Biasing Circits of BJTs Standard Biasing Circuits: 1. Fixed-Bias Circuit: Fig. 2-2a shows a fixed-bias circuit. Analysis: - For the input (base-emitter circuit) loop as shown in Fig. 2-2b: VCC I B RB VBE 0 I B V VBE CC RB [2.1a] - For the output (collector-emitter circuit) (a) loop as shown in Fig. 2-2c: IC βi B VCE IC RC VCC 0 VCE VCC IC RC [2.1b] - For the transistor terminal voltages: VE 0V VB VCC I B RB VBE [2.1c] VC VCC I C RC VCE (b) Load-Line Analysis: From Eq. [2.1b] and Fig. 2-3: Fig. 2-2 At cutoff region: V CE V CC IC 0 [2.2a] At saturation region: V IC CC R C VCE 0 [2.2b] I CQ (c) Design: For an optimum design: 1 VCEQ VCC 2 1 V ICQ IC (sat) CC 2 2RC [2-3] Fig. 2-3 V CEQ 11

12 DC Biasing Circits of BJTs 2. Emitter-Stabilized Bias Circuit: Fig. 2-4a shows an emitter-stabilized bias circuit. Analysis: For the input (base-emitter circuit) loop as shown in Fig. 2-4b: VCC I B RB VBE I E RE 0 I E (β 1)I B VCC VBE I B [2.4a] RB (β 1)RE For the output (collector-emitter circuit) loop as shown in Fig. 2-4c: I E RE VCE IC RC VCC 0 I E IC VCE VCC IC (RC RE ) [2.4b] For the transistor terminal voltages: (a) VE I E RE VB VCC I B RB VE VBE [2.4c] VC VCC IC RC VE VCE (b) Load-Line Analysis: From Eq. [2.4b] and Fig. 2-5: Fig. 2-4 At cutoff region: V CE V CC [2.5a] IC 0 At saturation region: (c) IC VCC R C R E VCE 0 [2.5b] Design: For an optimum design: 1 VCEQ VCC 2 ICQ VE 1 VCC IC (sat) 2 2(RC RE ) 1 10 VCC ICQ [2-6] Fig. 2-5 VCEQ 12

13 DC Biasing Circits of BJTs 3. Voltage-Divider Bias Circuit: Fig. 2-6a shows a voltage-divider bias circuit. Analyses: For the input (base-emitter circuit) loop: Exact Analysis: From Fig. 2-6b: [2.7a] RTh R1 R2 From Fig. 2-6c: E th= V R2= R2VCC R1 R2 From Fig. 2-6d: ETh I B RTh VBE I E RE 0 I E (β 1)I B [2.7b] (a) I B ETh VBE RTh (β 1)RE [2.7c] IC I B Approximate Analysis: (b) (c) From Fig. 2-6e: If Ri R2 => I 2 I B. Since I B 0 => I1 I 2. Thus R1 in series with R2. That is, VB [2.8a] (d) I R2VCC R1 R2 Since Ri (β 1)RE βre the condition that will define whether the approximation approach can be applied will be the following: βre 10R2 and VE VB VBE V IC E E RE [2.8b] [2.8c] For the output (collector-emitter circuit) loop: Fig. 2-6 VCE VCC IC (RC RE ) [2.9] (e) 13

14 DC Biasing Circits of BJTs Load-Line Analysis: The similarities with the output circuit of the emitter-biased configuration result in the same intersections for the load line of the voltage-divider configuration. The load line will therefore have the same appearance as that of Fig The level of IB is of course determined by a different equation for the voltage-divider bias and the emitter-bias configuration. Design: For an optimum design: 1 VCEQ VCC 2 1 Ic(sat) = VCC 2 2(RC RE ) VE = 1/10 Vcc R 2 10 β R E [2.10] Example 2-1: Determine the dc bias voltage VCE and the current IC for the voltage-divider configuration of Fig. 2-6a with the following parameters: VCC = +22 V, β = 140, R1 = 39 kω, R2 = 3.9 kω, RC = 10 kω, and RE = 1.5 kω. Solution: Exact: RTh R1 R2 39k 3.9k 3.55Ω ETh I B R2VCC (3.9k )(22) 2V R1 R2 39k 3.9k ETh VBE RTh (β 1)RE µA 3.55k (141)(1.5k) I CQ β I B (140)(6.05µ) 0.85mA VCEQ VCC IC (RC RE ) 22 (0.85m)(10k 1.5k ) 12.23V Approximate: Testing: β RE 10R2 (140)(1.5k) 10(3.9k ) 210kΩ 39kΩ(satisfied) R2VCC (3.9k )(22) VB 2V R1 R2 39k 3.9k VE VB VBE V VE ICQ I 1.3 E 0.867mA RE 1.5k VCEQ VCC IC (RC RE ) 22 (0.867m)(10k 1.5k ) 12.03V 14

15 DC Biasing Circits of BJTs 4. Voltage-Feedback Bias Circuit: Fig. 2-7a shows a voltage-feedback bias circuit. Analysis: For the input (base-emitter circuit) loop as shown in Fig. 2-7b: VCC IC Ic' RC I B RB VBE I E RE 0 Ic' IC IC I B I EIC β I B VCC β I B RC I B RB VBE β I B RE 0 VCC VBE I B RB β (RC RE ) For the output (collector-emitter circuit) loop as shown in Fig. 2-7c: I E RE VCE IC' RC VCC 0 IC' I E IC VCE VCC IC (RC RE ) [2.11a] [2.11b] (a) Load-Line Analysis: Continuing with the approximation Ic' IC IC will result in the same load line defined for the voltage-divider and emitter-biased configurations. The levels of IBQ will be defined by the chosen base configuration. Design:For an optimum design: 1 VCEQ 2 VCC ICQ VE 1 IC (sat) VCC I c(sat) = 2 2(RC RE ) [2-12] 1 10 VCC RB β (RC RE ) (b) (c) Fig

16 DC Biasing Circits of BJTs Other Biasing Circuits: Example 2-2: (Negative Supply) Determine VC and VB for the circuit of Fig Solution: I B RB VBE VEE 0 (KVL) V - V I B EE BE 0 9 V = 83µA RB 100k IC β I B (45)(83µ ) 3.735mA VC I C RC (3.735m)(1.2k ) 4.48V VB I B RB (83µ )(100k ) 8.3V Fig. 2-8 Example 2-3: (Two Supplies) Determine VC and VB for the circuit of Fig. 2-9a. Solution: From Fig. 2-9b: RTh R1 R2 8.2k 2.2k 1.73kΩ I V CC VEE mA R1 R2 8.2k 2.2k ETh IR2 VEE (3.85m)(2.2k) V From Fig. 2-9c: ETh I B RTh VBE I E RE VEE 0 (KVL) I E (β 1)I B I B V EE E Th V BE RTh (β 1)RE k (121)(1.8k) 35.39µA IC β I B (120)(35.39µ ) 4.25mA VC VCC IC RC 20 (4.25m)(2.7k ) 8.53V VB ETh I B RTh (11.53) (35.39µ )(1.73k ) 11.59V (a) (b) (c) Fig

17 DC Biasing Circits of BJTs Example 2-4: (Common-Base) Determine VCB and IB for the common-base configuration of Fig Solution: Applying KVL to the input circuit: VEE I E RE VBE 0 V - VBE I E EE 2.75mA RE 1.2k Applying KVL to the output circuit: VCB I C RC VCC 0 VCB VCC IC RC with IC I E VCB 10 (2.75m)(2.4k ) 3.4V Fig IC 2.75m I B 45.8µA β 60 Example 2-5: (Common-Collector) Determine IE and VCE for the common-collector (emitter-follower) configuration of Fig Solution: Applying KVL to the input circuit: I B RB VBE I E RE VEE 0 I E (β 1)I B VEE VBE I B RB (β 1)RE µA 240k (91)(2k) I E (β 1)I B (91)(45.73µ) 4.16mA Applying KVL to the output circuit: VEE I E RE VCE 0 VCE VEE I E RE 20 (4.16m)(2k ) 11.68V Fig

18 DC Biasing Circits of BJTs Example 2-6: (PNP Transistor) Determine VCE for the voltage-divider bias configuration of Fig Solution: Testing: β RE 10R2 (120)(1.1k) 10(10k ) 132kΩ 100kΩ(satisfied ) R2VCC (10k )(18) VB 3.16V 47k 10k R1 R2 VE VB VBE 3.16 (0.7) 2.46V VE 2.46 IC I E 2.24mA RE 1.1k I E RE VCE IC RC VCC 0 (KVL) VCE VCC IC (RC RE ) 18 (2.24m)(2.4k 1.1k ) 10.16V Fig Exercises: 1. For the fixed-biased configuration of Fig. 2-2a with the following parameters: VCC = +12 V, β = 50, RB = 240 kω, and RC = 2.2 kω, determine: IBQ, ICQ, VCEQ, VB, VC, and VBC. 2. Given the device characteristics of Fig. 2-13a, determine VCC, RB, and RC for the fixed-bias configuration of Fig. 2-13b. (a) (b) Fig

19 DC Biasing Circits of BJTs 3. For the emitter bias circuit of Fig. 2-4a with the following parameters: VCC = +20 V, β = 50, RB = 430 kω, RC = 2 kω, and RE = 1 kω, determine: IB, IC, VCE, VC, VE, VB and VBC. 4. Design an emitter-stabilized circuit (Fig. 2-4a) at ICQ = 2 ma. Use VCC = +20 V and an npn transistor with β = Determine the dc bias voltage VCE and the current IC for the voltage-divider configuration of Fig. 2-6a with the following parameters: VCC = +18 V, β = 50, R1 = 82 kω, R2 = 22 kω, RC = 5.6 kω, and RE = 1.2 kω. 6. Design a beta-independent (voltage-divider) circuit to operate at VCEQ = 8 V and ICQ = 10 ma. Use a supply of VCC = +20 V and an npn transistor with β = Determine the quiescent levels of ICQ and VCEQ for the voltage-feedback circuit of Fig. 2-7a with the following parameters: VCC = +10 V, β = 90, RB = 250 kω, RC = 4.7 kω, and RE = 1.2 kω. 8. Prove that RB β (RC RE ) is the required condition for an optimum design of the voltage-feedback circuit. 9. Prove mathematically that ICQ for the voltage-feedback bias circuit is approximately independent of the value of beta. 10. Fig shows a three-stage circuit with a VCC supply of +20 V. GND stands for ground. If all transistors have a β of 100, what are the IC and VCE of each stage? 20V vi 10µF 10µF 2kΩ 3kΩ 10µF 50kΩ 10µF vo 100kΩ 0.56kΩ 8kΩ 3kΩ 0.68kΩ Fig GND 19

20 Second Year, Electronics I I, Bias Stabilization Bias Stabilization Basic Definitions: The stability of system is a measure of sensitivity of a circuit to variations in its parameters. In any amplifier employing a transistor the collector current IC is sensitive to each of the following parameters: ICO (reverse saturation current): doubles in value for every 10 o C increase in temperature. VBE (base-to-emitter voltage): decrease about 7.5 mv per 1 o C increase in temperature. β (forward current gain): increase with increase in temperature. Any or all of these factors can cause the bias point to drift from the design point of operation. Stability Factors, S(ICO), S(VBE), and S(β): A stability factor, S, is defined for each of the parameters affecting bias stability as listed below: S (ICO ) IC ICO IC ICO VBE, β const. [3.1a] S (VBE ) IC VBE IC VBE ICO, β const. [3.1b] S (β ) IC β IC β ICO,VBE const. [3.1c] Generally, networks that are quite stable and relatively insensitive to temperature variations have low stability factors. In some ways it would seem more appropriate to consider the quantities defined by Eqs. [3.1a - 3.1c] to be sensitivity factors because: the higher the stability factor, the more sensitive the network to variations in that parameter. The total effect on the collector current can be determined using the following equation: IC S (ICO )ICO S (VBE )VBE S (β ) β [3.2] 20

21 Bias Stabilization Derivation of Stability Factors for Standard Bias Circuits: For the voltage-divider bias circuit, the exact analysis (using Thevenin theorem) for the input (base-emitter) loop will result in: and and or ETh I B RTh VBE I E RE 0, I E IC I B => IC RE I B (RE RTh ) VBE ETh, I C β I B (β 1)I CO, IC β +1 ICO => I B β β IC [ (β 1)RE RTh ( β 1)(RE RTh ) ]- IICO β [ β VBE ETh [3.3] The partial derivation of the Eq. [3.3] with respect to ICO will result: I C I CO (β 1)RE RTh β (β 1)(RE RTh ) β 0 S (ICO ) (β 1)(RE RTh ) (β 1)RE RTh [3.4a] Also, the partial derivation of the Eq. [3.3] with respect to VBE will result: I C VBE (β 1)RE RTh β 1 0 S (VBE ) β (β 1)RE RTh [3.4b] The mathematical development of the last stability factor S(β) is more complex than encountered for S(ICO) and S(VBE). Thus, S(β) is suggested by the following equation: S (β ) (IC 1 / β 1 )(RE Th ) R (β 2 1)RE RTh [3.4c] 21

22 Second Year, Electronics I I, Bias Stabilization For the emitter-stabilized bias circuit, the stability factors are the same as these obtained above for the voltage-divider bias circuit except that RTh will replaced by RB. These are: S (ICO ) S (VBE ) (β 1)(RE RB ) (β 1)RE RB β (β 1)RE RB [3.5a] [3.5b] S (β ) (I C 1 / β 1 )(RE R B ) (β 2 1)RE RB [3.5c] resul: For the fixed-bias circuit, if we plug in RE = 0 the following equation will S (ICO ) β 1 [3.6a] S (VBE ) β RB [3.6b] S (β) IC 1 β 1 [3.6c] Finally, for the case of the voltage-feedback bias circuit, the following equation will result: (β 1)(RC RE RB ) S (ICO ) (β 1)(RC RE ) RB β S (VBE ) (β 1)(RC RE ) RB [3.7a] [3.7b] S ( ) (I C 1 / β 1 )(RC R E R B ) (β 2 1)(RC RE ) RB [3.7c] 22

23 Bias Stabilization Example 3-1: 1. Design a voltage-divider bias circuit using a VCC supply of +18 V, and an npn silicon transistor with β of 80. Choose RC = 5RE, and set IC at 1 ma and the stability factor S(ICO) at For the circuit designed in part (1), determine the change in IC if a change in operating conditions results in ICO increasing from 0.2 to 10 μa, VBE drops from 0.7 to 0.5 V, and β increases 25%. 3. Calculate the change in IC from 25 o to 75 o C for the same circuit designed in part (1), if ICO = 0.2 μa and VBE = 0.7 V. Solution: Part 1: VCC 18V VCE VCC / 2 18 / 2 9V. RC 7.5kΩ VCE VCC IC (RC RE ), RC 5RE => R1 36kΩ C o 9 18 (1m)(5R E R E ) => R E 1.5kΩ. Ci RC 5(1.5k ) 7.5kΩ. vi β 80 I E IC 1mA, VE I E RE (1m)(1.5k) 1.5V. VB VE VBE V. R2 5kΩ RE 1.5kΩ R2VCC R2 VB 2.2 VB => [10.8a] R1 R2 R1 R2 VCC 18 ( β 1)(RE RTh ) S (ICO ) (β 1)RE RTh => Fig. 3-1 (81)(1.5k RTh ) 3.8 (81)(1.5k) RTh => RTh 4.4kΩ. R1R2 R2 RTh 4.4k RTh => R1 R2 R1 R 2 R 1 R 1 [3.8b] vo From Eqs. [3.8a] and [3.8b]: 4.4k 2.2 => R1 36kΩ. 18 R1 From Eq. [3.8a]: R => R2 5kΩ. 36k R2 18 Fig. 3-1 shows the final circuit. 23

24 Bias Stabilization Part 2: S (ICO ) 3.8, ICO 10µ 0.2µ 9.8µA β S (VBE ) 0.635mS, (β+1) R E +R Th (81)(1.5k)+(4.4k) VBE V. β 2 β 1 (1 25 /100) 1.25 β (80) 100, (Ic1/ β1)(r E +R TH ) (1m/80)(1.5k)+4.4k S (β ) 0.473µA, ( β2+1) R E +R TH (101)(1.5k) 4.4k β IC S (ICO )ICO S (VBE )VBE S (β ) β (3.8)(9.8µ ) (0.635m)(0.2) (0.473µ )(20) 0.174mA. Part 3: Since ICO, doubles in value for every 10 o C increase in temperature. T Thus = 5, Ico(75 o C)=2N.Ico(25o C)=(25)(0.2µ)=6.4µA ICO 6.4µ 0.2µ 6.2µA. Since VBE, decreases about 7.5 mv per 1 o C increase in temperature. Thus T o C, VBE (25 o C) 0.7V => VBE (75 o C) (7.5m) 0.325V. IC S (ICO )ICO S (VBE )VBE (3.8)(6.2µ ) (0.635m)(0.375) 0.262mA. Exercises: 1. Derive a mathematical expression to determine the stability factor S (VCC ) I C VCC for the emitter-stabilized bias circuit. 2. Discuss and compare (by equations) between the relative levels of stability for the following biasing circuits: i. the fixed-bias circuit, ii. the emitter-stabilized bias circuit, iii. the voltage-divider bias circuit, and iv. the voltage-feedback circuit. 24

25 BJT Switching Circuits BJT Switching Circuits Basic Concepts: The application of transistors is not limited solely to the amplification of signals. Through proper design it can be used as a switch for computer and control applications. The circuit of Fig. 4-1a can be employed as an inverter in computer logic circuitry. Note that the output voltage VC is opposite to that applied to the base or input terminal. In addition, note the absence of a dc supply connected to the base circuit. The only dc source is connected to the collector or output side and for computer applications is typically equal to the magnitude of the "high" side of the applied signal-in this case 5V. VCC 5V RC 5V RB 0V (a) VBE VCE VC 5V 0V Fig. 4-1 (b) Proper design for the inversion process requires that the operating point switch from cutoff to saturation along the load line depicted in Fig. 4-1b. For our purposes we will assume that IC ICEO 0 ma when I B 0 μa (an excellent approximation in light of improving construction techniques), as shown in Fig. 4-1b. In addition, we will assume that V CE V CE (sat ) 0 V rather than the typical 0.1 to 0.3 V level. When = 5 V, the transistor will be "on" and the design must ensure that the circuit is heavily saturated by a level of IB greater than that associated with the IB curve appearing near the saturation level. The base current IB for the circuit of Fig. 4-1a is determined by I B V i V BE [4.1] RB The saturation level for collector current IC(sat) for the same circuit is defined by V IC(sat) CC [4.2] RC The level of IB in the active region just before saturation results can be approximated by the following equation: IC (sat ) I B(max) [4.3] For the saturation level we must therefore ensure that the following is satisfied: I B I B(max) [4.4] 25

26 BJT Switching Circuits Example 4-1: Verify that the circuit shown in Fig. 4-2 behaves like an inverter when the input switches between 0 V and +10 V. Assume that the transistor is silicon and that β = 50. Solution: It is only necessary to verify that the transistor is saturated when = +10 V. V V I B i BE 42.3µA. 22k0 RB I C (sat ) VCC 10 I B(max) 32.3µA. RC (50)(6.2k) Thus, we have I B I B(max), therefore the transistor is Solution: (4)(5k) VCC 20V When 0V, VB 0.8V, hence the 20k 5k RC 1.6kΩ transistor is at cutoff, so that D1 and D2 are on and D2 Vo V o = =-5v V. D1 When 5V -5v,RTh=5kII20k=4kΩ, 5k 4k, Si Ge R1 (4)(5k ) (5)(20k ) V ETh 3.2V, i 20k 5k 20k 5k 5kΩ R2 20kΩ E I B Th 625µA. RTh 4k 4V We assume the V transistor is at saturation, Vo 0V, Fig. 4-3 so that D1 and D2 are off and IC (sat ) 12.5mA, RC 1.6k I B (max) I C (sat) / 12.5mA /. IC (sat) 12.5m I B I B(max) => µ RB 220kΩ saturated, and the circuit is inverter. Fig. 4-2 Example 4-2: VCC 10V RC 6.2kΩ Vo 50 Verify that the circuit shown in Fig. 4-3 is an inverter when the input switches between 0 V and -5 V. What minimum value of β is required? Assume that the transistor is silicon. VCC 20 For the transistor to be in saturation, I B 4V Vo 26

27 BJT Switching Circuits Exercise: 1. Design the transistor inverter of Fig. 4-4 to operate with a saturation current of 8 ma using a transistor with a beta of 100. Use a level of IB equal to 120% of IB(max) and standard resistor values. V CC 5V RC Vo 5 RB t Fig Verify that the circuit shown in Fig. 4-5 is a positive NAND when the input switches between 0 V and +12 V. Neglect source impedance and junction saturation voltages and diode voltages in forward direction. Find the minimum value of β. VCC 12V 12V RC 2.2kΩ VA VB D1 D2 R1 15kΩ R2 15kΩ R3 100kΩ Vo 12V Fig

28 BJT Modeling and AC Equivalent Circuit BJT Modeling and AC Equivalent Circuit Basic Concepts: The key to the transistor small-signal analysis is the use of ac equivalent circuits or models. A model is the combination of circuit elements, properly chosen, that best approximates the actual behavior of a semiconductor device (BJT) under specific operating conditions. Once the ac equivalent circuit has been determined, the graphical symbol of the device can be replaced in the schematic by this circuit and the basic methods of ac circuit analysis (mesh analysis, nodal analysis, and Thevenin's theorem) can be applied to determine the response of the circuit. There are two schools of thought in prominence today regarding the equivalent circuit to be substituted for the transistor: hybrid and re model. In summary, the ac equivalent circuit of the BJT amplifier is obtained by (see Fig. 5-1): 1. Setting all dc sources to zero and replacing them by a short-circuit equivalent. 2. Replacing all capacitors by a short-circuit equivalent. 3. Removing all elements bypassed by the short-circuit equivalents introduced by stapes 1 and Redrawing the circuit in a more convenient and logical form. 5. Use the hybrid or re equivalent circuit of the BJT to complete the equivalent circuit of the amplifier. 6. Finally, the following parameters are determined for the amplifier: a. Input impedance (Zi). b. Output impedance (Zo). c. Voltage gain (Av). d. Current gain (Ai). e. Phase relationship (θ). (a) (b) (c) Fig

29 BJT Modeling and AC Equivalent Circuit The Hybrid (h-parameters) Equivalent Model: For the general hybrid two-port system of Fig. 5-2: h11ii h12vo I o h21ii h22vo [5.1a] [5.1b] Fig. 5-2 where h11 Ii h12 Vo Vo 0 Ii 0 hi (Ω), short-circuit input impedance parameter. hr (unitless), open-circuit reverse transfer voltage ratio parameter. h21 I o Ii Vo 0 h f (unitless), short-circuit forward transfer current ratio parameter. h22 Io Vo Ii 0 ho (S ), open-circuit output admittance parameter. From the BJT hybrid equivalent circuit of Fig. 5-3, Eqs. [5.1a] and [5.1b] becomes: hi Ii hrvo I o h f Ii hovo [5.2a] [5.2b] Fig

30 BJT Modeling and AC Equivalent Circuit Gain and Impedance Computation of the Complete Hybrid Equivalent Circuit: For the circuit of Fig. 5-4, RS Ii hi Io VS Zi hrvo h f ii 1/ ho Zo Vo RL Fig. 5-4 the voltage gain (Av = Vo/); Ii V i h r V o, I o V o, and Io h f I i h o V o => hi RL Av Vo h f RL hi (hi ho h f hr )RL [5.3a] the current gain (Ai = Io/Ii); Io h f Ii 1 ho 1 ho RL h f ii 1 ho RL => Ai Io Ii h f 1 ho RL [5.3b] the input impedance (Zi = /Ii); h V hi r o, and Vo I o R L => I hi h r R L o hi h r R L A i => Ii Ii - Ii Ii - Zi Ii h f hr RL hi 1 ho RL [5.3c] the output impedance (Zo = Vo/Io when VS = 0 V); VS I i (R S h i ) h r V o 0 => Ii hrvo RS hi, and I o h f Ii hovo => I o = h o Vo - o Zo Vo I o h f hr RS hi ho 1 h f hr RS hi Vo => [5.3d] 30

31 BJT Modeling and AC Equivalent Circuit Types of Hybrid Parameters: Since there are three types of BJT configuration (CE, CC, and CB), there are three different ways that the input and output can be defined and therefore three corresponding sets of h-parameters as shown in Table 5-1. If all of the h-parameters values in one configuration are known, then the values corresponding to any other configuration can be determined. The common-emitter values of the h-parameters are the ones most often given. BJT configuration Table 5-1 h-parameters sets 1 Common-Emitter hie, hfe, hre, hoe 2 Common-Collector hic, hfc, hrc, hoc 3 Common-Base hib, hfb, hrb, hob The hybrid equivalent circuits of the CE and CB transistor configuration are shown in Fig. 5-5 (a) and (b) respectively. (a) (b) Fig

32 BJT Modeling and AC Equivalent Circuit Table 5-2 lists typical parameter values in each of the three transistor configurations (CE, CC, and CB) for the broad range of transistors available today. Table 5-2 h-parameters CE CC CB hi 1kΩ 1kΩ 20kΩ hr hf ho 25 μs 25 μs 0.5 μs 1/ho 40 kω 40 kω 2 MΩ Graphical Determination of the CE Hybrid Parameters: The parameters hie and hre are determined from the input or base characteristics, while the parameters hfe and hoe are obtained from the output or collector characteristics as shown in Fig hie vbe ib VCE const. 1.5kΩ hre vbe vce I B const h fe ic ib VCE const. 100 Fig. 5-6 hoe ic vce IB const. 33µS 32

33 BJT Modeling and AC Equivalent Circuit For the transistor whose characteristics have appeared in Fig. 5-6, the resulting hybrid small-signal equivalent circuit is shown in Fig Fig. 5-7 The typical values of h-parameters for CE transistor configuration are shown in Table 5-3. Table 5-3 Approximate CE Hybrid Equivalent Model: hxe parameters Min. Max. Unit Input impedance hie kω Voltage feedback ratio hre Small-signal current gain hfe Output admittance hoe μs Since hre is normally a relatively small quantity, its removal is approximated by hre 0 and hrevce = 0, resulting in a short-circuit equivalent for the feedback element. The resistance determined by 1/hoe is often large enough to be ignored in comparison to a parallel load permitting its replacement by an open-circuit equivalent for the CE model as shown in Fig b For the circuit of Fig. 5-8, e Ib Ic c Io Zi hie h fe Ib Fig. 5-8 Zo Vo e RL Zo ' Zi hie, and Z o. Ai Ic h fe, and Av Vo I o RL I c RL h fe R L Ai Z ' o. Ib Ib hie Ib hie hie Zi 33

34 BJT Modeling and AC Equivalent Circuit The re Equivalent Model: CB Transistor Configuration: From Fig. 5-9, the input impedance at the emitter of CB transistor configuration (dynamic resistance of the forward diode) can de determined by: re 26mV I E [5.4] the output impedance at the collector (dynamic resistance of the reverse diode) is: also; ro Zi re, and Zo Vo Io RL (Ic )RL Ie RL, and I e Zi I ere => Av Vo R RL L R L. re re I c e I, and Ai I o I c I e => Ai. Ii I e (a) (b) (c) (d) (e) Fig

35 BJT Modeling and AC Equivalent Circuit CE Transistor Configuration: From Fig ; I c Ib, I e I c Ib Ib Ib ( 1)Ib Ib, and Vbe I ere Ib re. Vbe Zi re. Ii Ib Z o ro. Vo I o RL I c RL Ib RL, Vo Vo Ib RL R Vbe Ib er re Av L Ai I o Ii I c Ib. Ib Ib (a) (b) (c) (d) (e) (g) Fig

36 BJT Modeling and AC Equivalent Circuit Hybrid Versus re Model: The hybrid versus re model for CE and CB transistor configurations are shown in Figs (a) and (b) respectively. (a) (b) Fig Approximate Conversion Formulas for Hybrid and re Models: The approximate conversion formulas for hybrid and re models for CB and CC configurations are listed in Table 5-4. CB Configuration Table 5-4 CC Configuration hib hie (1 h fe ) re hic hie re hrb hiehoe (1 h fe ) hre hrc 1 hre 1 h fb h fe (1 h fe ) h fc (1 h fe ) hob hoe (1 h fe ) hoc hoe 1/ ro Exercise: Given IE = 1.3 ma, β = 100, and ro = 40 kω, sketch: 1. The CE and CB hybrid equivalent models. 2. The CE and CB re equivalent models. 36

37 BJT Small-Signal Analysis Common-Emitter Configuration: BJT Small-Signal Analysis The voltage divider circuit of Fig. 6-1 includes an emitter resistor (RE) that may or may not be bypassed by an emitter capacitor (CE) in the ac domain. VCC RS Vs Ii C S Zi R1 B Zb R2 C E RC C RE Zo C Io Vo CE RL Zo Zin Fig. 6-1 Bypassed (absence of RE): For the ac equivalent circuit of Fig. 6-2, Ii b Ib Ic c Io RS Vs Zi R Zb re hie e Ib h fe Ib ro 1/ hoe Zo RC Vo RL Zo Zin Fig. 6-2 Using re equivalent model: Input impedance: R R1 R2 Zb re Zi R Zb R re Zin RS Zi RS (R re ) 37

38 BJT Small-Signal Analysis Output impedance: Approximate (neglecting ro); Exact (including ro); Z o RC Z o RC ro ZZ o o RL Z o RL RC ZZ o o RL RC ro Voltage gain: Approximate (neglecting ro); Vo I I c Z Z o Ib (RL RC ) Exact (including ro); Av R L R C r o re Ib Zb re V RL R o C Av V r i o Vo Vo Avs Av Vs Vs Zi Zi RS Current gain: Approximate (neglecting ro); Exact (including ro); Ai I o I o I c I b Ai ro RC R Ii I c Ib Ii [ro (R C R L )](R C R L )(R re ) RC R. RC RL R Zb RC R (RC R L )(R re ) I o I o Ii RS Ais Ai I s Ii I s RS Zi Phase relationship: The negative sign in the resulting equation for Av reveals that a 180o phase shift occurs between the input and output voltage signals. 38

39 BJT Small-Signal Analysis Using hybrid equivalent model: Approximate (neglecting hoe); Zb hie h fe ( R L RC) Av - Ai hie h fe RC R (RC R L )(R hie ) Exact (including hoe); h fe (RL RC 1 / hoe ) Av Ai hie h fe RC R/ hoe [1/ hoe (R C R L )](R C R L )(R hie ) Unbypassed (include of RE): For the approximate ac equivalent circuit ( ro 1/ hoe Ω ) of Fig. 6-3, Ii b Ib Ic c Io RS Vs Zi R Zb re hie e I e Ib h fe Ib Zo RC Vo RL Zo RE Fig. 6-3 Using re equivalent model: Input impedance: Ib re I e RE Ib [re ( 1)RE ] Zb Ib re ( 1)RE (re RE ) RE Zi R Zb R [re ( 1)RE ] R (re RE ) R RE Output impedance: Z o RC Z' Z o o RL Z o RL RC Voltage gain: Vo IcZo Z' o Ib (RL RC ) Ib Zb (re RE ) 39

40 BJT Small-Signal Analysis Av Vo R L R C R L R C re RE RE Current gain: Ai I o I o I c I b I i I c I b Ii RC R RC RL R Zb RC R RC R (RC R L )[R (re R E )] (RC R L )(R RE ) Phase relationship: Vo and are out-of-phase by 180 o. Using hybrid equivalent model: Common-Base Configuration: The common-base configuration of Fig. 6-4 is characterized as having a relatively low input and a high output impedance and a current gain less than 1. The voltage gain, however, can be quite large. Ii CS E C CC I o RS Vs Zi Zb RE VEE B Zo RC VCC Vo RL Zo Fig

41 BJT Small-Signal Analysis Using re equivalent model: For the approximate ac equivalent circuit ( ro Ω) of Fig. 6-5, Input impedance: Zb re Zi RE Output impedance: Zo RC Z' o RL re [low] RC [high] RS Voltage gain: Vo I c Zo Z' o I e (RL RC ) Vs Ii Zi R E e Ie Zb re b Fig. 6-5 Ic Ie c Zo Io RC Vo RL Zo I e / re Av Current gain: (RL RC ) RL re re RC [high] RC RE [less than 1] (RC RL )(RE re ) Phase relationship: Vo and are in-phase. Using hybrid equivalent model: For the approximate ac equivalent circuit (1/ hob Ω) of Fig. 6-6, Zb hib Zi RE hib hfb (R L R C) Av - hib h fb RC RE RS Vs Ai Fig. 6-6 (RC RL )(RE hib ) [hfb: -ve quantity] Ii Zi R E e I e Zb hib b Ic c h fb Ie Zo Io RC Vo RL Zo 41

42 BJT Small-Signal Analysis Common-Collector (Emitter-Follower] Configuration: When the output is taken from the emitter terminal of the transistor, an amplifier circuit is referred to as emitter-follower as shown in Fig The emitter-follower configuration is frequently used for impedance-matching purposes. It presents a high impedance at the input and a low impedance at the output. Also, the output voltage is always slightly less than the input signal with an in-phase relationship between them. VCC Ii CS RB B C RS Vs Zi Zb E RE Zo CC Vo Io RL Zo Fig. 6-7 Using re equivalent model: For the ac equivalent circuit of Fig. 6-8, Ii b Ib Ic c RS Vs Zi RB Zb re hie e I e Io Ib h fe Ib RE Zo Vo RL Input impedance: R RL RE Ib re I e R Ib[re ( 1)R] Zb / Ib re ( 1)R (re R) R [high] Fig. 6-8 Zi RB Zb 42

43 BJT Small-Signal Analysis Output impedance: Vs Ii RS Ib re I e R 0 For the circuit of Fig. 13-9a, RTh R S R B, and ETh where RB >> RS => Ib Vs RB RS RB RTh RS, ETh Vs, and Ii Ib Vs Ib RS Ib re Ib ( 1)R 0 Vs RS re ( 1)R ( 1)Vs I e ( 1)Ib RS re ( 1)R [KVL] Vs RS / R S / h fe RS Vs (a) RB Thevenin re Ie Io hie / h fe Zo RE Vo RL Zo Vs RS / re R (b) Drawing the circuit to "fit" the above last equation will result in the configuration of Fig. 6-9b. Thus Fig. 6-9 Z ' o Z o RE (RS / re ) Z o RL Zo [low] Voltage gain: Vo Av I e R I e (R re ) R R re [less than 1] A vs Current gain: Vo Vs R R Rs / re 43

44 BJT Small-Signal Analysis Using hybrid equivalent model: Zb hie (h fe 1)R h fe R Z o RE (RS hie ) / h fe Av R R hie / h fe R A vs R (Rs hie )/ h fe h fe RE RB Ai (RE RL )(RB h fe R) Example 6-1: For the BJT amplifier circuit of Fig with the following parameters: VBE = 0.7 V, β = hfe 250, and ro = 1/hoe Ω, determine: (a) re, and dc output voltage (VC). (b) hie, Zb, Zi, Zo, and Zo. (c) Av = Vo/, and Ai = Io/Ii. (d) A vs V o /V s, and ac output voltage (Vo). VCC 20V Ii RS 750Ω Vs CS 25mV Zi R1 91kΩ Zb RC 3kΩ C Zo R2 10kΩ RE1 180Ω RE2 820Ω C Io Vo RL CE Zo 12kΩ Fig

45 BJT Small-Signal Analysis Solution: Testing: RE 10R2, RE RE1 RE k 0.82k 1kΩ, 250(1k ) 10(10k ), 250k 100k Satisfied, V. R2 1.98V, I E B BE VB CC 20(10k ) V - V R1 R2 10k 91k RE 1k 26mV 26m re 20.3Ω, IC I E 1.28mA, and I E 1.28m VC VCC IC RC m(3k ) 16.16V. hie re 250(20.3) 5.075kΩ, Zb hie (h fe 1)RE k 251(0.18k ) 50.26kΩ, 1.28mA, R R1 R2 91k 10k 9.01kΩ, Zi R Zb 9.01k 50.26k 7.64kΩ, Z o RC 3kΩ, and Z o RL RC 12k 3k 2.4kΩ. h fe Z o 250(2.4k ) Zi Av 11.94, and Ai Av 11.94( 7. 64k ) Zb 50.26k RL 12k V Zi 11.94( 7. 64k ) Avs Av i Av 10.87, and Vs Zi RS 7.64k 0.75k V o A vs V s 10.87(25m) mV Example 6-2: Design the BJT amplifier circuit shown in Fig to have a voltage gain magnitude of 4, Zi = 3.37 kω, Zo = 3 kω, and Z o = 2kΩ. Assume that the transistor is silicon with 100, hie = 1 kω, ro = 1/hoe Ω, and RE 10R2. V CC 20V R1 RC C C Io RS Vs Ii CS Zi Zb R2 RE Zo Vo RL Zo Fig

46 BJT Small-Signal Analysis Solution: RC Zo 3kΩ, Z o RL RC 2k RL 3k RL 6kΩ. Av Z o 4 2 RE 0.5kΩ. RE RE Example 6-3: Complete the design of the BJT amplifier circuit shown in Fig for a voltage gain of 125, Zo = 2.4 kω, Zo = 2 kω. Assume that 0.985, VBE = 0.7 V, and ro = 1/hob Ω. Calculate A vs, and Vo. VCC 9V RC CC RS CS Zo Vo Zo RL Vs 20Ω 10mV Zi VEE RE 4V Fig

47 BJT Small-Signal Analysis Exercises: 1. For each one of the circuits shown in Fig. 6-13, write a mathematical expression to determine each of the following parameters by using hybrid or re equivalent model. (a) Zb and Zi. (b) Zo and Z o. (c) Ai and Av. V CC V CC R F1 R F 2 R C C C I o R 1 R S V s I i C S Z i V i C F Z b R E Zo V o Z o R L R S V s Ii C S Z i V i Z b R 2 I o Zo V o R L Z o C E R E (a) (b) Fig

48 BJT Small-Signal Analysis 2. For the common-base amplifier of Fig. 6-14, determine the following parameters using the complete hybrid equivalent model and compare the results to these obtained using the approximate model. (a) Zb and Zi. (b) Zo and Z o. (c) Ai and A vs. (d) Ai and A is. Ii CS hie 1.6kΩ hre h fe 110 hoe 20S CC Io RS 1kΩ Vs Zi RE VEE Zb 3kΩ 6V VCC RC Zo 3kΩ 12V V R o L Zo 8.2kΩ Fig Complete the design of the BJT amplifier circuit shown in Fig for a voltage gain magnitude of 205, Zi =1.5k Ω, and Z o = 3.2 kω. Assume that 100, VBE = 0.7 V, RF1/RF2 =1.95, and ro = 1/hoe Ω. Sketch Vo to the same time scale as Vs. VCC 10V RC CC Io RF1 RF 2 Vs RS Ii C S 1kΩ 2Sinwt mv Zi CF Z b Zo Vo RL Zo Fig

49 49