Bi-directional brain. with brain implantable. computer interface. Arm-based SoCs. Joseph Fernando Principal architect, Arm. Arm Tech Symposia 2017

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1 Bi-directional brain computer interface with brain implantable Arm-based SoCs Joseph Fernando Principal architect, Arm Arm Tech Symposia 2017

2 Agenda The Needs Improve quality of life through Electroceuticals The play of Analog Front Ends (AFEs) Neural Signal Recording Neural signal stimulation The play of Mix mode/digital processing Arm Cortex-M4 /AI /ML Call to action 2

3 Our nervous system 3

4 The needs Neuro degenerative Injury 4

5 Addressing the needs Revolutionize the treatment of stroke, spinal cord injury and other neurological conditions by developing the principles of closed-loop, coadaptive, ethically-grounded bi- directional braincomputer interfaces (BBCIs) that enable the body to heal, feel, and move again. 5 5

Signal Stimulation Wireless Telemetry Wireless Power

6 Move over pharmaceuticals, now electroceuticals NeuroSoc Neural Compute Neural Signal Recording Neural Signal Stimulation Wireless Telemetry Wireless Power Rx Wireless Telemetry External Mobile Device Wireless Power Rx 6

7 Challenges 7

8 Neural signal recording

9 Conventional Approaches Harrison JSSC 03 Muller JSSC 15 9

10 Calibration and weighted sum Our recording architecture M U X Shared CM Artifact Suppression Shared Charge Sampling OTA Shared 8-Bit SAR Delta-Encoding loop 64x16b Interleaved Channels DM Artifact Template Shared 8-bit CDAC + 64 Channel x8b Register + 10

Artifact suppression Saturation DM Supression Off DM Supression On x64 Electrode and MUX REP RES CE φmux REP VMID φaz1 φaz2 φtie CIN Vin φaz1 φaz2 (a) To LNA x64 Electrode and MUX REP RES CE φmux REP

11 Artifact suppression Saturation DM Supression Off DM Supression On x64 Electrode and MUX REP RES CE φmux REP VMID φaz1 φaz2 φtie CIN Vin φaz1 φaz2 (a) To LNA x64 Electrode and MUX REP RES CE φmux REP VMID φaz1 φaz2 φtie CIN Vin φaz1 φaz2 To LNA (b) x64 Electrode and MUX REP RES CE φmux REP VMID φaz1 φaz2 φtie CIN Vin φaz1 φaz2 To LNA x64 Electrode and MUX REP RES CE φmux REP VMID φaz1 φaz2 φtie CIN Vin φaz1 φaz2 To LNA x64 Electrode and MUX REP RES CE φmux REP VMID φaz1 φaz2 φtie CIN Vin φaz1 φaz2 To LNA VMID VMID VMID VMID VMID φaz1 φaz1 φaz1 φaz1 φaz1 φaz2 φaz2 φaz2 φaz2 φaz2 φmux φmux φmux φmux φmux φtie φtie φtie φtie φtie 11

12 Crosstalk suppression >90dB crosstalk suppression V0 V1 V2 Without Autozero R R C R V0 V2 V1 Scenario 1 Low High T0 T1 T2 t V1 V2 V0 Scenario 2 Low High T0 T1 T2 t Sample has Memory V0 V1 V2 With Autozero R R C R φaz V0 V2 V1 Scenario 1 V1 V2 V0 Scenario 2 Memoryless Sample 12 T0 T1 T2 t T0 T1 T2 t

13 AGG DAC ADC Delta loop encoding x

14 Comparatives work Work UC Berkeley JSSC 15 [2] Univ. of Michigan JSSC 16 [3] National Chiao Tung Univ. JSSC 14 [4] IMEC ESSCIRC 16 [5] THIS WORK Technology 65nm CMOS 0.18μm CMOS 0.18μm CMOS 0.13μm CMOS 65nm CMOS Supply Voltage 0.5V 0.5V, 1V 1.8V 1.2V, 1.8V 0.5V, 2.5V DM Artifact Suppression None LMS on Input DAC None None CM Artifact Suppression None None None None Template Subtrac-tion on Input DAC Switched-Cap. Offset Correction Multiplexing N/A N/A ADC Shank Interconnect Full Signal Chain # of Ch Ch. Area 0.025mm mm 2 N/A 0.12mm mm 2 Ch. Power 2.3μW 330nW 56.7μW 3μW 2.98μW IRN/NEF 1.2μV rms / μV rms / μV rms / μV rms / μV rms / 2.21 CMRR/PSRR 88dB / 67dB N/A N/A N/A 76dB / 82dB Bandwidth 1Hz - 500Hz 1Hz - 2kHz 0.1Hz - 0.7kHz 0.5Hz 8kHz 1Hz 1kHz 14 Pk-Pk Range 100mV pk-pk N/A N/A N/A 110mV pk-pk Crosstalk -85 db N/A N/A -63dB -92dB ADC Type 15b RO-Based Amplifier Only Full Probe DC coupled to Electrode 10b Range Adapting SAR 10b Delta-Modulated SAR 10b SAR 8b SAR + Delta Encoding (14b)

15 Neural signal stimulation

16 Biphasic current pulses Pulse Width Pulse Amplitude Phase Interval 16

17 Conventional Approach Pulse Width Pulse Amplitude V DD Phase Interval I stim I stim I stim Electrode Reliable high-voltage interfacing circuits with low-voltage devices. Deliver constant current to a widerange of electrode impedances. 17

18 Sink-Regulated H-Bridge Topology HVDD V E,A ( ΔV) +I STIM I STIM E ACTIVE TISSUE I STIM Z E I E,A E RETURN HVDD V E,R (DC) HVDD V E,A (DC) +I STIM I STIM E ACTIVE I E,A TISSUE I STIM Z E E RETURN HVDD V E,R ( ΔV) Only sink regulation and single power rail required Highest intrinsic compliance for a given HVDD, V d,sat STATE-OF-ART [Chen, 14] Single charge-pump boosts HVDD as needed; switches use device stacking for high-voltage tolerance COMPLIANCE = ±(HVDD V d,sat ) ±9V compliance using 3.3V devices 18

19 Sink-Regulated H-Bridge w/ Capacitive-Looking Z E Unreliable Balancing Stimulus Delivery HVDD +I STIM I STIM I E,A HVDD HVDD +I STIM I STIM I E,A HVDD +I STIM I STIM I E,A HVDD V E,A ( ΔV) E ACTIVE Z E E RETURN V E,R V E,A E ACTIVE (DC) (DC) + + TISSUE TISSUE I STIM I STIM + I SHORT Z E E RETURN V E,R ( ΔV) 0V HVDD HVDD + V ON V E,R V E,A To-date, ZE charge storage is not accounted for by high-voltage CMOS H-Bridge stimulators Switch devices may be overstressed Junctions may be forward biased Stimulus current unpredictable 19

20 Proposed front-end solution RELIABLE 2-PHASE BALANCING STIMULUS DELIVERY HVDD +I STIM I STIM I E,A HVDD +I STIM I STIM I E,A HVDD +I STIM I STIM I E,A HVDD V E,A ( ΔV) E ACTIVE + TISSUE I STIM E RETURN V E,R (DC) V E,A (DC) E ACTIVE + TISSUE I STIM E RETURN V E,R ( ΔV) V E,A (DC) E ACTIVE E RETURN + TISSUE I STIM V E,R ( ΔV) Z E V d,sat Z E Z E V E,R = V d,sat COMPLIANCE = ±(HVDD V d,sat ) Deliver balancing current in two phases: 1 st phase Z E discharged by I STIM while E ACTIVE held at low DC voltage Once V E,A = V E,R, 2 nd phase activated HVDD used to supply remaining balancing stimulus 20

21 ΔV ΔV H-Bridge states for biphasic pulse delivery V DVS,A = 0V V DVS,R = 0V V DVS,A = 0V 0V HVA V E,A Z E V E,R 0V HVA + V d,sat +I STIM I STIM +I STIM I STIM I STIM 1 HVA I STIM Z E ΔV V DVS,R + HVA V MAX 2 PCD R in SUPPLY Feedback +I STIM PCD R in TRACK Feedback V DVS,A = 0V 0V Z E V E,R HVA ΔV V DVS,R = V E,R + HVA + 3 0V 0V + V d,sat V CMP +I STIM I STIM V DVS,A = V E,A V DVS,R = 0V +I STIM I STIM V DVS,A V MAX V DVS,R = 0V +I STIM I STIM V DVS,A = 0V V DVS,R = V E,R + CLOSE FOR FORCED DISCHARGE HVA V E,A Z E + 0V HVA PCD A in TRACK Feedback 6 PCD A in SUPPLY Feedback x HVA I STIM Z E + + V d,sat HVA + V d,sat 5 PCD R in TRACK Feedback HVA I STIM + Z E ΔV + V IDAC + HVA V CMP 4 Stim architecture appeared in [6] E. Pepin et al, BioCAS

22 Stimulator comparison table System [X] T. BioCAS 13 [X] JSSC 15 [X] JSSC 14 This Work Stimulus Regulation Biphasic Current (Constant or Arbitrary) Biphasic Constant Current Biphasic Constant Current Biphasic Constant Current Front-End Topology Ground-Return Differential H-Bridge H-Bridge Process 65nm CMOS (TSMC LP) 65nm CMOS (TSMC LP) 0.18μm CMOS (TSMC) 65nm CMOS (TSMC GP) Devices Used / Voltage Compliance 1.2V, 2.5V / 2.4V 1.2V, 2.5V / 6V 1.8V, 3.3V / 9V 1V, 2.5V / 10V to 11V* Electrode Invariant R YES, C YES R?**, C YES R YES, C NO** R YES, C YES Charge-Balancing Technique Digital Calibration Electrode Shorting w/ Off-Chip Series Blocking Cap N.A. Electrode Shorting w/ Off-Chip Series Blocking Cap MAX I STIM / IDAC LSB 50μA / 3μA 450μA*** / 7μA 30μA / 30μA 2mA / 10μA***** Electrode Pads / Stimulators 513 / / 2 2 / 1 2 / 1 Stimulator Active Area mm 2 /stimulator 0.385mm mm 2 /stimulator In-Vivo Evaluation None None * 10V at 2mA stimulus, 11V at 50μA stimulus **Not Demonstrated ***Demonstrated up to 150μA ****Could be 8; language/figures are vague *****50μA minimum 0.6mm 2 2mm 2 Rat (Acute, Closed-Loop seizure Suppression) Rat (Acute, Evoked Motor Response) 22

23 Neural signal processing

24 Neural Signal Processing 32 channels Storage 8channels FIR IIR Hilbert transforms Band-pass filters Spike detection Power spectrum density Level Detectors Neural Signal Recording Channel Selection Rectification & Filtering Feature Extraction Configuration and Record Timer FPGA Control Logic Classifiers Machine Learning 24 Arm Cortex-M4

25 Electroceuticals implants Continued R&D Channel Weights State Arm Cortex-M4 Neural Recording DSP Compute Per cycle configuration and instructions Configuration Brain State Adaptive Control Machine Learning NeuroSOC II Embedded ML Second tapeout Neural-IO. Implement NIO and a nearfinal version of the processor 25 Design initial processing architecture with the right mix of accelerators and FPGA functionality on Arm Cortex-M4 Tapeout Neural-IO. Implement prototype board with NIO and HUB processor

26 Get involved

27 Partnerships BBCI Semiconductors Neuroethics Computational Neuroscience Wireless Apps Medical Devices Patient Therapy Consumer Electronics 27

28 For further information Center for Sensorimotor Neural Engineering

29 Thank You! Danke! Merci! 谢谢! ありがとう! Gracias! Kiitos! 감사합니다 धन यव द 29

30 The Arm trademarks featured in this presentation are registered trademarks or trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. All rights reserved. All other marks featured may be trademarks of their respective owners. 30

Bi-directional brain computer interface with brain implantable Arm-based SoCs Joseph Fernando Principal architect

Bi-directional brain computer interface with brain implantable Arm-based SoCs Joseph Fernando Principal architect Arm Tech Symposia 2017 Agenda The needs Improve quality of life through Electroceuticals