Continuous-Time Systems

Size: px
Start display at page:

Download "Continuous-Time Systems"

Transcription

1 Continuous-Time Systems Continuous time waveforms Analog RF High-freq./speed continuous time Radio design community today: analog ~= RF Bluetooth chip (Cambridge Silicon) Mixed-signal Low-freq. Continuous-time IC design community (opamps) Digital + analog/rf tight interaction Mixed-domain includes non-electronic eg: mech., optical Slide 1

2 Applications beyond ICs Internal combustion engine NEMS switch Photonic interconnect Integrated photonic demux Mechanical Optical Energy Nanodevices Biology MEMS disc resonator Energy sources Intracellular reactions Energy-efficient buildings Biological systems Drug design (CADD) Si-InP bulk-process laser Spin-torque devices Carbon nanotubes Energy grids Slide 2

3 Continuous-Time Analysis Fundamentals Modelling: nonlinear differential equations Solving nonlinear equations numerically Solving linear matrix equations numerically Solving differential equations numerically Linearization Frequency-domain concepts Analysing the effects of variability Linear differential equations: steady states Sensitivities Noise: modelling and analysis Slide 3

4 Analog Effects in Digital Electronics 2-input NAND Timing/Delay Correctness Interference/ Noise Slide 4

5 Noise and Variability Geometrical variability Oxide thicknesses: O(10) atoms White noise (time domain) ubiquitous in devices Mechanism similar to biological reactions (inherently stochastic) Spread of parameters showing correlation Time-varying RTS noise (discrete-continuous) RTS noise (freq. domain) Noise/variability are of crucial importance for both analog and digital Impact of device variability (Intel: Shekhar Borkar) Slide 5

6 Analog Issues in Digital (contd.) analog issues becoming show-stoppers analog problems have proliferated clean boolean abstractions much less relevant to actual implementations contributing to Moore's law slowdown analog/mixed-signal key focus at Intel (show Top's slides) Slide 6

7 Start: High-Level System Concept System design starts from simplifications/abstractions Idealized representations: proof of concept simulation/verification Credits: Karim Chabrak. Slide 7

8 Top-Down Design Refinement Manual (skilled) design process: little/no automated synthesis Transceiver block for UMTS Credits: Karim Chabrak. Reference Phase Detector Lowpass Filter VCO Frequency Divider Slide 8

9 Circuit-Level Design (Analog/MS) choose (or invent) ckt topology design loop: most time-consuming step choose parameters... W, L, res/cap values, placement, supplies, s-1000s of runs typical: DC, model and simulate transient, AC, noise, sensitivity, HB,... check simulated performances against desired eg: gain, distortion/im, CMRR, phase margin (stability), lock range, jitter/snr/ber, delay, read/write access times, yield, performances met? exit loop skilled manual process not met? change parameters, retry specialized optimizers (occasionally) too many tries and no success? try other topologies relax desired specs; retry (change system at higher levels to compensate) simulation time: #1 designer complaint some circuits (eg, PLLs) take so long that designs fab without adequate simulation high numbers of chip failures after fab (3-5 respins) Slide 9

10 Bottom Up Validation Transceiver block for UMTS placement/layout + extraction Reference Phase Detector loop: simulate system, validate operation, redesign Lowpass Filter Frequency Divider VCO loop: simulate + redesign extracted ckt embed in system Credits: Karim Chabrak. Slide 10

11 Abstraction-Based Verification too expensive: impractical Credits: Karim Chabrak. Low level models Credits: Karim Chabrak. Reference Phase Detector Lowpass Filter Frequenc y Divider VCO use simpler higher level model Accurate? Consistent? Slide 11

12 The Gap EE Times The primary problem hindering the change to analog top-down design and bottom-up verification has been the lack of tool support for the design process between system-level specification and transistor-level implementation, as well as between transistor implementation and chip fabrication. These missing tools are commonly referred to as The Gap." - EE Times, 2001 Slide 12

13 EE Times on The Gap : continued At this point, you may wonder why you should bother with behavioral libraries and calibration. Why not just submit the transistor-level design to some smart software and let it come up with a model? Unfortunately, despite some claims to the contrary, practical model synthesis is still a long way off. Attempts at this technology rely on pre-existing templates, which are unlikely to exist for leading-edge or proprietary designs. There's no pushbutton approach to analog modeling, and from all indications, this will remain the case for some time to come. - EE Times, 2001 Slide 13

14 Mixed-Signal/Domain Design Today McCorquodale et al, U of Michigan Design Validation many re-spins: the norm Slide 14

15 Design Validation System Verification Flow: the Future Automated abstraction needed to generate higher-level models McCorquodale et al, U of Michigan Slide 15

16 Goal: Automated Macromodelling Low-level model (detailed, big) Macromodelling Higher-level model (consistent, simpler, smaller) Automate! Computational Algorithms Push button generation (fast) Consistency/ Fidelity Accuracy vs Size tradeoffs Slide 16

Continuous-Time Systems

Continuous-Time Systems Continuous-Time Systems Continuous time waveforms Analog RF High-freq./speed continuous time Radio design community today: analog ~= RF Bluetooth chip (Cambridge Silicon) Mixed-signal Low-freq. Continuous-time

More information

PV-PPV: Parameter Variability Aware, Automatically Extracted, Nonlinear Time-Shifted Oscillator Macromodels

PV-PPV: Parameter Variability Aware, Automatically Extracted, Nonlinear Time-Shifted Oscillator Macromodels PV-PPV: Parameter Variability Aware, Automatically Extracted, Nonlinear Time-Shifted Oscillator Macromodels Zhichun Wang, Xiaolue Lai and Jaijeet Roychowdhury Dept of ECE, University of Minnesota, Twin

More information

Lecture 1, Introduction and Background

Lecture 1, Introduction and Background EE 338L CMOS Analog Integrated Circuit Design Lecture 1, Introduction and Background With the advances of VLSI (very large scale integration) technology, digital signal processing is proliferating and

More information

Hot Topics and Cool Ideas in Scaled CMOS Analog Design

Hot Topics and Cool Ideas in Scaled CMOS Analog Design Engineering Insights 2006 Hot Topics and Cool Ideas in Scaled CMOS Analog Design C. Patrick Yue ECE, UCSB October 27, 2006 Slide 1 Our Research Focus High-speed analog and RF circuits Device modeling,

More information

EECS240 Spring Advanced Analog Integrated Circuits Lecture 1: Introduction. Elad Alon Dept. of EECS

EECS240 Spring Advanced Analog Integrated Circuits Lecture 1: Introduction. Elad Alon Dept. of EECS EECS240 Spring 2009 Advanced Analog Integrated Circuits Lecture 1: Introduction Elad Alon Dept. of EECS Course Focus Focus is on analog design Typically: Specs circuit topology layout Will learn spec-driven

More information

Analysis and Design of Analog Integrated Circuits Lecture 1. Overview of Course, NGspice Demo, Review of Thevenin/Norton Modeling

Analysis and Design of Analog Integrated Circuits Lecture 1. Overview of Course, NGspice Demo, Review of Thevenin/Norton Modeling Analysis and Design of Analog Integrated Circuits Lecture 1 Overview of Course, NGspice Demo, Review of Thevenin/Norton Modeling Michael H. Perrott January 22, 2012 Copyright 2012 by Michael H. Perrott

More information

EE2254 LINEAR INTEGRATED CIRCUITS UNIT-I IC FABRICATION

EE2254 LINEAR INTEGRATED CIRCUITS UNIT-I IC FABRICATION DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING Question bank EE2254 LINEAR INTEGRATED CIRCUITS UNIT-I IC FABRICATION 1. Mention the advantages of integrated circuits. 2. Write down the various processes

More information

Teaching Staff. EECS240 Spring Course Focus. Administrative. Course Goal. Lecture Notes. Elad s office hours

Teaching Staff. EECS240 Spring Course Focus. Administrative. Course Goal. Lecture Notes. Elad s office hours EECS240 Spring 2012 Advanced Analog Integrated Circuits Lecture 1: Introduction Teaching Staff Elad s office hours 519 Cory Hall Tues. and Thurs. 11am-12pm (right after class) GSI: Pierluigi Nuzzo Weekly

More information

Progress Towards Computer-Aided Design For Complex Photonic Integrated Circuits

Progress Towards Computer-Aided Design For Complex Photonic Integrated Circuits Department of Electrical and Computer Engineering Progress Towards Computer-Aided Design For Complex Photonic Integrated Circuits Wei-Ping Huang Department of Electrical and Computer Engineering McMaster

More information

Datorstödd Elektronikkonstruktion

Datorstödd Elektronikkonstruktion Datorstödd Elektronikkonstruktion [Computer Aided Design of Electronics] Zebo Peng, Petru Eles and Gert Jervan Embedded Systems Laboratory IDA, Linköping University http://www.ida.liu.se/~tdts80/~tdts80

More information

Analysis and Design of Autonomous Microwave Circuits

Analysis and Design of Autonomous Microwave Circuits Analysis and Design of Autonomous Microwave Circuits ALMUDENA SUAREZ IEEE PRESS WILEY A JOHN WILEY & SONS, INC., PUBLICATION Contents Preface xiii 1 Oscillator Dynamics 1 1.1 Introduction 1 1.2 Operational

More information

Question Paper Code: 21398

Question Paper Code: 21398 Reg. No. : Question Paper Code: 21398 B.E./B.Tech. DEGREE EXAMINATION, MAY/JUNE 2013 Fourth Semester Electrical and Electronics Engineering EE2254 LINEAR INTEGRATED CIRCUITS AND APPLICATIONS (Regulation

More information

Research in Support of the Die / Package Interface

Research in Support of the Die / Package Interface Research in Support of the Die / Package Interface Introduction As the microelectronics industry continues to scale down CMOS in accordance with Moore s Law and the ITRS roadmap, the minimum feature size

More information

THE BASIC BUILDING BLOCKS OF 1.8 GHZ PLL

THE BASIC BUILDING BLOCKS OF 1.8 GHZ PLL THE BASIC BUILDING BLOCKS OF 1.8 GHZ PLL IN CMOS TECHNOLOGY L. Majer, M. Tomáška,V. Stopjaková, V. Nagy, and P. Malošek Department of Microelectronics, Slovak Technical University, Ilkovičova 3, Bratislava,

More information

INF3430 Clock and Synchronization

INF3430 Clock and Synchronization INF3430 Clock and Synchronization P.P.Chu Using VHDL Chapter 16.1-6 INF 3430 - H12 : Chapter 16.1-6 1 Outline 1. Why synchronous? 2. Clock distribution network and skew 3. Multiple-clock system 4. Meta-stability

More information

Appendix. RF Transient Simulator. Page 1

Appendix. RF Transient Simulator. Page 1 Appendix RF Transient Simulator Page 1 RF Transient/Convolution Simulation This simulator can be used to solve problems associated with circuit simulation, when the signal and waveforms involved are modulated

More information

DAV Institute of Engineering & Technology Department of ECE. Course Outcomes

DAV Institute of Engineering & Technology Department of ECE. Course Outcomes DAV Institute of Engineering & Technology Department of ECE Course Outcomes Upon successful completion of this course, the student will intend to apply the various outcome as:: BTEC-301, Analog Devices

More information

1 2 B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2010 Fourth Semester Electrical and Electronics Engineering EE 2254 LINEAR INTEGRATED CIRCUITS AND APPLICATIONS (Common to Instrumentation and Control

More information

Linear Integrated Circuits and Applications

Linear Integrated Circuits and Applications Dhanalakshmi Srinivasan Engineering College - Perambalur Department of EEE QUESTION BANK Linear Integrated Circuits and Applications UNIT-I ICs FABRICATION 1. Mention the advantages of integrated circuits.

More information

Investigating the Electronic Behavior of Nano-materials From Charge Transport Properties to System Response

Investigating the Electronic Behavior of Nano-materials From Charge Transport Properties to System Response Investigating the Electronic Behavior of Nano-materials From Charge Transport Properties to System Response Amit Verma Assistant Professor Department of Electrical Engineering & Computer Science Texas

More information

Reinventing the Transmit Chain for Next-Generation Multimode Wireless Devices. By: Richard Harlan, Director of Technical Marketing, ParkerVision

Reinventing the Transmit Chain for Next-Generation Multimode Wireless Devices. By: Richard Harlan, Director of Technical Marketing, ParkerVision Reinventing the Transmit Chain for Next-Generation Multimode Wireless Devices By: Richard Harlan, Director of Technical Marketing, ParkerVision Upcoming generations of radio access standards are placing

More information

LUCEDA PHOTONICS DELIVERS A SILICON PHOTONICS IC SOLUTION IN TANNER L-EDIT

LUCEDA PHOTONICS DELIVERS A SILICON PHOTONICS IC SOLUTION IN TANNER L-EDIT LUCEDA PHOTONICS DELIVERS A SILICON PHOTONICS IC SOLUTION IN TANNER L-EDIT WIM BOGAERTS, PIETER DUMON, AND MARTIN FIERS, LUCEDA PHOTONICS JEFF MILLER, MENTOR GRAPHICS A M S D E S I G N & V E R I F I C

More information

Disseny físic. Disseny en Standard Cells. Enric Pastor Rosa M. Badia Ramon Canal DM Tardor DM, Tardor

Disseny físic. Disseny en Standard Cells. Enric Pastor Rosa M. Badia Ramon Canal DM Tardor DM, Tardor Disseny físic Disseny en Standard Cells Enric Pastor Rosa M. Badia Ramon Canal DM Tardor 2005 DM, Tardor 2005 1 Design domains (Gajski) Structural Processor, memory ALU, registers Cell Device, gate Transistor

More information

Relationship Between Signal Integrity and EMC

Relationship Between Signal Integrity and EMC Relationship Between Signal Integrity and EMC Presented by Hasnain Syed Solectron USA, Inc. RTP, North Carolina Email: HasnainSyed@solectron.com 06/05/2007 Hasnain Syed 1 What is Signal Integrity (SI)?

More information

Course Outcome of M.Tech (VLSI Design)

Course Outcome of M.Tech (VLSI Design) Course Outcome of M.Tech (VLSI Design) PVL108: Device Physics and Technology The students are able to: 1. Understand the basic physics of semiconductor devices and the basics theory of PN junction. 2.

More information

Simulation of Radio Frequency Integrated Circuits

Simulation of Radio Frequency Integrated Circuits Simulation o Radio Frequency Integrated Circuits Based on: Computer-Aided Circuit Analysis Tools or RFIC Simulation: Algorithms, Features, and Limitations, IEEE Trans. CAS-II, April 2000. Outline Introduction

More information

Analog-to-Digital Converter Performance Signoff with Analog FastSPICE Transient Noise at Qualcomm

Analog-to-Digital Converter Performance Signoff with Analog FastSPICE Transient Noise at Qualcomm Analog-to-Digital Converter Performance Signoff with Analog FastSPICE Transient Noise at Qualcomm 2009 Berkeley Design Automation, Inc. 2902 Stender Way, Santa Clara, CA USA 95054 www.berkeley-da.com Tel:

More information

Advances in Silicon Technology Enables Replacement of Quartz-Based Oscillators

Advances in Silicon Technology Enables Replacement of Quartz-Based Oscillators Advances in Silicon Technology Enables Replacement of Quartz-Based Oscillators I. Introduction With a market size estimated at more than $650M and more than 1.4B crystal oscillators supplied annually [1],

More information

Integrated Circuit Design for High-Speed Frequency Synthesis

Integrated Circuit Design for High-Speed Frequency Synthesis Integrated Circuit Design for High-Speed Frequency Synthesis John Rogers Calvin Plett Foster Dai ARTECH H O US E BOSTON LONDON artechhouse.com Preface XI CHAPTER 1 Introduction 1 1.1 Introduction to Frequency

More information

UNIT-III POWER ESTIMATION AND ANALYSIS

UNIT-III POWER ESTIMATION AND ANALYSIS UNIT-III POWER ESTIMATION AND ANALYSIS In VLSI design implementation simulation software operating at various levels of design abstraction. In general simulation at a lower-level design abstraction offers

More information

T.J.Moir AUT University Auckland. The Ph ase Lock ed Loop.

T.J.Moir AUT University Auckland. The Ph ase Lock ed Loop. T.J.Moir AUT University Auckland The Ph ase Lock ed Loop. 1.Introduction The Phase-Locked Loop (PLL) is one of the most commonly used integrated circuits (ICs) in use in modern communications systems.

More information

Lecture 7: Components of Phase Locked Loop (PLL)

Lecture 7: Components of Phase Locked Loop (PLL) Lecture 7: Components of Phase Locked Loop (PLL) CSCE 6933/5933 Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides are borrowed from various books, websites, authors pages,

More information

Lecture: Integration of silicon photonics with electronics. Prepared by Jean-Marc FEDELI CEA-LETI

Lecture: Integration of silicon photonics with electronics. Prepared by Jean-Marc FEDELI CEA-LETI Lecture: Integration of silicon photonics with electronics Prepared by Jean-Marc FEDELI CEA-LETI Context The goal is to give optical functionalities to electronics integrated circuit (EIC) The objectives

More information

Phase-Locked Loop Engineering Handbook for Integrated Circuits

Phase-Locked Loop Engineering Handbook for Integrated Circuits Phase-Locked Loop Engineering Handbook for Integrated Circuits Stanley Goldman ARTECH H O U S E BOSTON LONDON artechhouse.com Preface Acknowledgments xiii xxi CHAPTER 1 Cetting Started with PLLs 1 1.1

More information

A Top-Down Microsystems Design Methodology and Associated Challenges

A Top-Down Microsystems Design Methodology and Associated Challenges A Top-Down Microsystems Design Methodology and Associated Challenges Michael S. McCorquodale, Fadi H. Gebara, Keith L. Kraver, Eric D. Marsman, Robert M. Senger, and Richard B. Brown Department of Electrical

More information

Innovative ultra-broadband ubiquitous Wireless communications through terahertz transceivers ibrow

Innovative ultra-broadband ubiquitous Wireless communications through terahertz transceivers ibrow Project Overview Innovative ultra-broadband ubiquitous Wireless communications through terahertz transceivers ibrow Mar-2017 Presentation outline Project key facts Motivation Project objectives Project

More information

Brief Course Description for Electrical Engineering Department study plan

Brief Course Description for Electrical Engineering Department study plan Brief Course Description for Electrical Engineering Department study plan 2011-2015 Fundamentals of engineering (610111) The course is a requirement for electrical engineering students. It introduces the

More information

Amber Path FX SPICE Accurate Statistical Timing for 40nm and Below Traditional Sign-Off Wastes 20% of the Timing Margin at 40nm

Amber Path FX SPICE Accurate Statistical Timing for 40nm and Below Traditional Sign-Off Wastes 20% of the Timing Margin at 40nm Amber Path FX SPICE Accurate Statistical Timing for 40nm and Below Amber Path FX is a trusted analysis solution for designers trying to close on power, performance, yield and area in 40 nanometer processes

More information

Aim. Unit abstract. Learning outcomes. QCF level: 6 Credit value: 15

Aim. Unit abstract. Learning outcomes. QCF level: 6 Credit value: 15 Unit T3: Microelectronics Unit code: A/503/7339 QCF level: 6 Credit value: 15 Aim The aim of this unit is to give learners an understanding of the manufacturing processes for and the purposes and limitations

More information

EE320L Electronics I. Laboratory. Laboratory Exercise #2. Basic Op-Amp Circuits. Angsuman Roy. Department of Electrical and Computer Engineering

EE320L Electronics I. Laboratory. Laboratory Exercise #2. Basic Op-Amp Circuits. Angsuman Roy. Department of Electrical and Computer Engineering EE320L Electronics I Laboratory Laboratory Exercise #2 Basic Op-Amp Circuits By Angsuman Roy Department of Electrical and Computer Engineering University of Nevada, Las Vegas Objective: The purpose of

More information

Automated Oscillator Macromodelling Techniques for Capturing Amplitude Variations and Injection Locking

Automated Oscillator Macromodelling Techniques for Capturing Amplitude Variations and Injection Locking Automated Oscillator Macromodelling Techniques for Capturing Amplitude Variations and Injection Locking Xiaolue Lai, Jaijeet Roychowdhury ECE Dept., University of Minnesota, Minneapolis December 1, 24

More information

f o Fig ECE 6440 Frequency Synthesizers P.E. Allen Frequency Magnitude Spectral impurity Frequency Fig010-03

f o Fig ECE 6440 Frequency Synthesizers P.E. Allen Frequency Magnitude Spectral impurity Frequency Fig010-03 Lecture 010 Introduction to Synthesizers (5/5/03) Page 010-1 LECTURE 010 INTRODUCTION TO FREQUENCY SYNTHESIZERS (References: [1,5,9,10]) What is a Synthesizer? A frequency synthesizer is the means by which

More information

Integrated Photonics using the POET Optical InterposerTM Platform

Integrated Photonics using the POET Optical InterposerTM Platform Integrated Photonics using the POET Optical InterposerTM Platform Dr. Suresh Venkatesan CIOE Conference Shenzhen, China Sept. 5, 2018 POET Technologies Inc. TSXV: PUBLIC POET PTK.V Technologies Inc. PUBLIC

More information

Introduction. Reading: Chapter 1. Courtesy of Dr. Dansereau, Dr. Brown, Dr. Vranesic, Dr. Harris, and Dr. Choi.

Introduction. Reading: Chapter 1. Courtesy of Dr. Dansereau, Dr. Brown, Dr. Vranesic, Dr. Harris, and Dr. Choi. Introduction Reading: Chapter 1 Courtesy of Dr. Dansereau, Dr. Brown, Dr. Vranesic, Dr. Harris, and Dr. Choi http://csce.uark.edu +1 (479) 575-6043 yrpeng@uark.edu Why study logic design? Obvious reasons

More information

A CMOS Analog Front-End Circuit for MEMS Based Temperature Sensor

A CMOS Analog Front-End Circuit for MEMS Based Temperature Sensor Technology Volume 1, Issue 2, October-December, 2013, pp. 01-06, IASTER 2013 www.iaster.com, Online: 2347-6109, Print: 2348-0017 A CMOS Analog Front-End Circuit for MEMS Based Temperature Sensor Bollam

More information

ECE 521. Design Flow. Fall 2016 Simulation. Design Verification. Why Solve Equations on a Computer?

ECE 521. Design Flow. Fall 2016 Simulation. Design Verification. Why Solve Equations on a Computer? Design Flow Comparison with specs Redesign Concept Implementation Design Specifications Circuit Schematic ECE 521 Layout SPICE etc. Physical definition Fall 2016 Physical verification Parasitic Extraction

More information

Phase-Locked Loops. Roland E. Best. Me Graw Hill. Sixth Edition. Design, Simulation, and Applications

Phase-Locked Loops. Roland E. Best. Me Graw Hill. Sixth Edition. Design, Simulation, and Applications Phase-Locked Loops Design, Simulation, and Applications Roland E. Best Sixth Edition Me Graw Hill New York Chicago San Francisco Lisbon London Madrid Mexico City Milan New Delhi San Juan Seoul Singapore

More information

Phase Locked Loops, Report Writing, Layout Tuesday, April 5th, 9:15 11:00

Phase Locked Loops, Report Writing, Layout Tuesday, April 5th, 9:15 11:00 Phase Locked Loops, Report Writing, Layout Tuesday, April 5th, 9:15 11:00 Snorre Aunet (sa@ifi.uio.no) Nanoelectronics group Department of Informatics University of Oslo Last time and today, Tuesday 5th

More information

ECEN 474/704 Lab 8: Two-Stage Miller Operational Amplifier

ECEN 474/704 Lab 8: Two-Stage Miller Operational Amplifier ECEN 474/704 Lab 8: Two-Stage Miller Operational Amplifier Objective Design, simulate and test a two-stage operational amplifier Introduction Operational amplifiers (opamp) are essential components of

More information

CHAPTER 1 INTRODUCTION

CHAPTER 1 INTRODUCTION CHAPTER 1 INTRODUCTION 1.1 Historical Background Recent advances in Very Large Scale Integration (VLSI) technologies have made possible the realization of complete systems on a single chip. Since complete

More information

An Efficient Design of CMOS based Differential LC and VCO for ISM and WI-FI Band of Applications

An Efficient Design of CMOS based Differential LC and VCO for ISM and WI-FI Band of Applications IJSTE - International Journal of Science Technology & Engineering Volume 2 Issue 10 April 2016 ISSN (online): 2349-784X An Efficient Design of CMOS based Differential LC and VCO for ISM and WI-FI Band

More information

SiNANO-NEREID Workshop:

SiNANO-NEREID Workshop: SiNANO-NEREID Workshop: Towards a new NanoElectronics Roadmap for Europe Leuven, September 11 th, 2017 WP3/Task 3.2 Connectivity RF and mmw Design Outline Connectivity, what connectivity? High data rates

More information

Quantum-effect Resonant Tunneling Device Technology for Practical Ultra Low-power High-speed Applications

Quantum-effect Resonant Tunneling Device Technology for Practical Ultra Low-power High-speed Applications Quantum-effect Resonant Tunneling Device Technology for Practical Ultra Low-power High-speed Applications SEMATECH Symposium October 23 rd, 2012 Prof. Kyounghoon Yang High Speed Nanoelectronics Laboratory

More information

FOR THE MOST CHALLENGING TELECOM AND WIRELESS DESIGNS

FOR THE MOST CHALLENGING TELECOM AND WIRELESS DESIGNS Eldo RF High-Performance RF IC Verification Analog/Mixed-Signal Verification D A T A S H E E T Key Benefits Full-chip RF IC verification for wireless applications Seamless integration into Mentor and other

More information

EE C245 ME C218 Introduction to MEMS Design

EE C245 ME C218 Introduction to MEMS Design EE C245 ME C218 Introduction to MEMS Design Fall 2008 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 94720 Lecture 1: Definition

More information

Appendix. Harmonic Balance Simulator. Page 1

Appendix. Harmonic Balance Simulator. Page 1 Appendix Harmonic Balance Simulator Page 1 Harmonic Balance for Large Signal AC and S-parameter Simulation Harmonic Balance is a frequency domain analysis technique for simulating distortion in nonlinear

More information

Ansys Designer RF Training Lecture 3: Nexxim Circuit Analysis for RF

Ansys Designer RF Training Lecture 3: Nexxim Circuit Analysis for RF Ansys Designer RF Solutions for RF/Microwave Component and System Design 7. 0 Release Ansys Designer RF Training Lecture 3: Nexxim Circuit Analysis for RF Designer Overview Ansoft Designer Advanced Design

More information

Computer Aided Design of Electronics

Computer Aided Design of Electronics Computer Aided Design of Electronics [Datorstödd Elektronikkonstruktion] Zebo Peng, Petru Eles, and Nima Aghaee Embedded Systems Laboratory IDA, Linköping University www.ida.liu.se/~tdts01 Electronic Systems

More information

EE C245 ME C218 Introduction to MEMS Design Fall 2007

EE C245 ME C218 Introduction to MEMS Design Fall 2007 EE C245 ME C218 Introduction to MEMS Design Fall 2007 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 94720 Lecture 1: Definition

More information

Ten-Tec Orion Synthesizer - Design Summary. Abstract

Ten-Tec Orion Synthesizer - Design Summary. Abstract Ten-Tec Orion Synthesizer - Design Summary Lee Jones 7/21/04 Abstract Design details of the low phase noise, synthesized, 1 st local oscillator of the Ten-Tec model 565 Orion transceiver are presented.

More information

The New England Radio Discussion Society electronics course (Phase 4, cont d) Introduction to receivers

The New England Radio Discussion Society electronics course (Phase 4, cont d) Introduction to receivers The New England Radio Discussion Society electronics course (Phase 4, cont d) Introduction to receivers AI2Q April 2017 REVIEW: a VFO, phase-locked loop (PLL), or direct digital synthesizer (DDS), can

More information

Fundamentals of RF Design RF Back to Basics 2015

Fundamentals of RF Design RF Back to Basics 2015 Fundamentals of RF Design 2015 Updated January 1, 2015 Keysight EEsof EDA Objectives Review Simulation Types Understand fundamentals on S-Parameter Simulation Additional Linear and Non-Linear Simulators

More information

A Review of Phase Locked Loop Design Using VLSI Technology for Wireless Communication.

A Review of Phase Locked Loop Design Using VLSI Technology for Wireless Communication. A Review of Phase Locked Loop Design Using VLSI Technology for Wireless Communication. PG student, M.E. (VLSI and Embedded system) G.H.Raisoni College of Engineering and Management, A nagar Abstract: The

More information

Design Considerations for 5G mm-wave Receivers. Stefan Andersson, Lars Sundström, and Sven Mattisson

Design Considerations for 5G mm-wave Receivers. Stefan Andersson, Lars Sundström, and Sven Mattisson Design Considerations for 5G mm-wave Receivers Stefan Andersson, Lars Sundström, and Sven Mattisson Outline Introduction to 5G @ mm-waves mm-wave on-chip frequency generation mm-wave analog front-end design

More information

CHAPTER 6 CARBON NANOTUBE AND ITS RF APPLICATION

CHAPTER 6 CARBON NANOTUBE AND ITS RF APPLICATION CHAPTER 6 CARBON NANOTUBE AND ITS RF APPLICATION 6.1 Introduction In this chapter we have made a theoretical study about carbon nanotubes electrical properties and their utility in antenna applications.

More information

Design of Analog CMOS Integrated Circuits

Design of Analog CMOS Integrated Circuits Design of Analog CMOS Integrated Circuits Behzad Razavi Professor of Electrical Engineering University of California, Los Angeles H Boston Burr Ridge, IL Dubuque, IA Madison, WI New York San Francisco

More information

Electronic Circuit Simulation Tools Using Pspice On Ac Analysis

Electronic Circuit Simulation Tools Using Pspice On Ac Analysis Electronic Circuit Simulation Tools Using Pspice On Ac Analysis This Design Idea shows it can handle digital filter simulation too. PSpice has become an industry standard tool for analog circuit simulations.

More information

ELECTRICAL AND ELECTRONIC ENGINEERING COURSES

ELECTRICAL AND ELECTRONIC ENGINEERING COURSES ELECTRICAL AND ELECTRONIC ENGINEERING COURSES PH1012 PHYSICS A [Academic Units: 4.0 ; Pre-requisite: Nil ; Contact Hours: Lec: 39 hr ; Tut: 12 hrs] Vectors. Kinematics. Forces and torques. Newton s laws

More information

Stability and Dynamic Performance of Current-Sharing Control for Paralleled Voltage Regulator Modules

Stability and Dynamic Performance of Current-Sharing Control for Paralleled Voltage Regulator Modules 172 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 17, NO. 2, MARCH 2002 Stability Dynamic Performance of Current-Sharing Control for Paralleled Voltage Regulator Modules Yuri Panov Milan M. Jovanović, Fellow,

More information

MARCH mmw-sprawl photonic integrated circuits for microwave photonics Martijn Heck

MARCH mmw-sprawl photonic integrated circuits for microwave photonics Martijn Heck MARCH 25. 2016 mmw-sprawl photonic integrated circuits for microwave photonics Martijn Heck 1 2 playing field PIC technology The case for photonic integration Pros Cons system performance: speed, sensitivity

More information

A CMOS CURRENT CONTROLLED RING OSCILLATOR WITH WIDE AND LINEAR TUNING RANGE

A CMOS CURRENT CONTROLLED RING OSCILLATOR WITH WIDE AND LINEAR TUNING RANGE A CMOS CURRENT CONTROLLED RING OSCILLATOR WI WIDE AND LINEAR TUNING RANGE Abstract Ekachai Leelarasmee 1 1 Electrical Engineering Department, Chulalongkorn University, Bangkok 10330, Thailand Tel./Fax.

More information

ECEN474: (Analog) VLSI Circuit Design Fall 2011

ECEN474: (Analog) VLSI Circuit Design Fall 2011 ECEN474: (Analog) VLSI Circuit Design Fall 2011 Lecture 1: Introduction Sebastian Hoyos Analog & Mixed-Signal Center Texas A&M University Analog Circuit Sequence 326 2 Why is Analog Important? [Silva]

More information

CMOS VLSI IC Design. A decent understanding of all tasks required to design and fabricate a chip takes years of experience

CMOS VLSI IC Design. A decent understanding of all tasks required to design and fabricate a chip takes years of experience CMOS VLSI IC Design A decent understanding of all tasks required to design and fabricate a chip takes years of experience 1 Commonly used keywords INTEGRATED CIRCUIT (IC) many transistors on one chip VERY

More information

Improved Model Generation of AMS Circuits for Formal Verification

Improved Model Generation of AMS Circuits for Formal Verification Improved Generation of AMS Circuits for Formal Verification Dhanashree Kulkarni, Satish Batchu, Chris Myers University of Utah Abstract Recently, formal verification has had success in rigorously checking

More information

EE105 Fall 2015 Microelectronic Devices and Circuits. Invention of Transistors

EE105 Fall 2015 Microelectronic Devices and Circuits. Invention of Transistors EE105 Fall 2015 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1-1 Invention of Transistors - 1947 Bardeen, Shockley, and Brattain at Bell Labs Invented

More information

PhD PRELIMINARY WRITTEN EXAMINATION READING LIST

PhD PRELIMINARY WRITTEN EXAMINATION READING LIST Updated 10/18/2007 PhD PRELIMINARY WRITTEN EXAMINATION READING LIST COMMUNICATIONS Textbook example: R. Ziemer and W. Tranter, "Principles of Communications", Wiley Typically covered in a course such as

More information

ECE 484 VLSI Digital Circuits Fall Lecture 02: Design Metrics

ECE 484 VLSI Digital Circuits Fall Lecture 02: Design Metrics ECE 484 VLSI Digital Circuits Fall 2016 Lecture 02: Design Metrics Dr. George L. Engel Adapted from slides provided by Mary Jane Irwin (PSU) [Adapted from Rabaey s Digital Integrated Circuits, 2002, J.

More information

M a r c h 7, Contact Hours = per week

M a r c h 7, Contact Hours = per week FE1012 PHYSICS A NEW [Academic Units: 4.0 ; Semester 1 ; Pre-requisite: Nil ; Contact Hours: Lec: 39 hr ; Tut: 12 hrs] Vectors. Kinematics. Forces and torques. Newton s laws of motion. Impulse and momentum.

More information

EE5310: Analog Electronic Circuits EE3002: Analog Circuits

EE5310: Analog Electronic Circuits EE3002: Analog Circuits EE5310: Analog Electronic Circuits EE3002: Analog Circuits Introduction S. Aniruddhan https://courses.iitm.ac.in Department of Electrical Engineering Indian Institute of Technology, Madras Chennai, 600036,

More information

Fall 2017 Project Proposal

Fall 2017 Project Proposal Fall 2017 Project Proposal (Henry Thai Hoa Nguyen) Big Picture The goal of my research is to enable design automation in the field of radio frequency (RF) integrated communication circuits and systems.

More information

Who am I? EECS240 Spring Administrative. Teaching Staff. References. Lecture Notes. Advanced Analog Integrated Circuits Lecture 1: Introduction

Who am I? EECS240 Spring Administrative. Teaching Staff. References. Lecture Notes. Advanced Analog Integrated Circuits Lecture 1: Introduction Who am I? EECS240 Spring 2013 Advanced Analog Integrated Circuits Lecture 1: Introduction Lingkai Kong Ph.D. in EECS, UC Berkeley, Dec. 2012. Currently a post-doc at BWRC Thesis: 60GHz Energy-Efficient

More information

Check out from stockroom:! Two 10x scope probes

Check out from stockroom:! Two 10x scope probes University of Utah Electrical & Computer Engineering Department ECE 3510 Lab 6 Basic Phase - Locked Loop M. Bodson, A. Stolp, 2/26/06 rev,3/1/09 Note : Bring a proto board, parts, and lab card this week.

More information

A Low Area, Switched-Resistor Loop Filter Technique for Fractional-N Synthesizers Applied to a MEMS-based Programmable Oscillator

A Low Area, Switched-Resistor Loop Filter Technique for Fractional-N Synthesizers Applied to a MEMS-based Programmable Oscillator A Low Area, Switched-Resistor Loop Filter Technique for Fractional-N Synthesizers Applied to a MEMS-based Programmable Oscillator ISSCC 00, Session 3. M.H. Perrott, S. Pamarti, E. Hoffman, F.S. Lee, S.

More information

Function Generator Using Op Amp Ic 741 Theory

Function Generator Using Op Amp Ic 741 Theory Function Generator Using Op Amp Ic 741 Theory Note: Op-Amps ua741, LM 301, LM311, LM 324 & AD 633 may be used To design an Inverting Amplifier for the given specifications using Op-Amp IC 741. THEORY:

More information

SOI technology platforms for 5G: Opportunities of collaboration

SOI technology platforms for 5G: Opportunities of collaboration SOI technology platforms for 5G: Opportunities of collaboration Dr. Ionut RADU Director, R&D SOITEC MOS AK workshop, Silicon Valley December 6th, 2017 Sourcing value from substrate Robert E. White ISBN-13:

More information

PROCESS-VOLTAGE-TEMPERATURE (PVT) VARIATIONS AND STATIC TIMING ANALYSIS

PROCESS-VOLTAGE-TEMPERATURE (PVT) VARIATIONS AND STATIC TIMING ANALYSIS PROCESS-VOLTAGE-TEMPERATURE (PVT) VARIATIONS AND STATIC TIMING ANALYSIS The major design challenges of ASIC design consist of microscopic issues and macroscopic issues [1]. The microscopic issues are ultra-high

More information

Structure-exploiting symbolic-numerical model reduction of nonlinear electrical circuits

Structure-exploiting symbolic-numerical model reduction of nonlinear electrical circuits Structure-exploiting symbolic-numerical model reduction of nonlinear electrical circuits ECMI 2010, Wuppertal, Germany, July 26-30, 2010 Oliver Schmidt Slide 1 Research Network SyreNe SyreNe System Reduction

More information

ALL-DIGITAL FREQUENCY SYNTHESIZER IN DEEP-SUBMICRON CMOS

ALL-DIGITAL FREQUENCY SYNTHESIZER IN DEEP-SUBMICRON CMOS ALL-DIGITAL FREQUENCY SYNTHESIZER IN DEEP-SUBMICRON CMOS ROBERT BOGDAN STASZEWSKI Texas Instruments PORAS T. BALSARA University of Texas at Dallas WILEY- INTERSCIENCE A JOHN WILEY & SONS, INC., PUBLICATION

More information

KINGS COLLEGE OF ENGINEERING* DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING QUESTION BANK

KINGS COLLEGE OF ENGINEERING* DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING QUESTION BANK KINGS COLLEGE OF ENGINEERING* DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING QUESTION BANK SUB.NAME : LINEAR INTEGRATED CIRCUITS SUB CODE: EC1254 YEAR / SEMESTER : II / IV UNIT- I IC FABRICATION

More information

EE C245 ME C218 Introduction to MEMS Design Fall 2010

EE C245 ME C218 Introduction to MEMS Design Fall 2010 Instructor: Prof. Clark T.-C. Nguyen EE C245 ME C218 Introduction to MEMS Design Fall 2010 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley

More information

ECE520 VLSI Design. Lecture 2: Basic MOS Physics. Payman Zarkesh-Ha

ECE520 VLSI Design. Lecture 2: Basic MOS Physics. Payman Zarkesh-Ha ECE520 VLSI Design Lecture 2: Basic MOS Physics Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Wednesday 2:00-3:00PM or by appointment E-mail: pzarkesh@unm.edu Slide: 1 Review of Last Lecture Semiconductor

More information

Radiation-hard/high-speed data transmission using optical links

Radiation-hard/high-speed data transmission using optical links Radiation-hard/high-speed data transmission using optical links K.K. Gan a, B. Abi c, W. Fernando a, H.P. Kagan a, R.D. Kass a, M.R.M. Lebbai b, J.R. Moore a, F. Rizatdinova c, P.L. Skubic b, D.S. Smith

More information

AN294. Si825X FREQUENCY COMPENSATION SIMULATOR FOR D IGITAL BUCK CONVERTERS

AN294. Si825X FREQUENCY COMPENSATION SIMULATOR FOR D IGITAL BUCK CONVERTERS Si825X FREQUENCY COMPENSATION SIMULATOR FOR D IGITAL BUCK CONVERTERS Relevant Devices This application note applies to the Si8250/1/2 Digital Power Controller and Silicon Laboratories Single-phase POL

More information

2. There are many circuit simulators available today, here are just few of them. They have different flavors (mostly SPICE-based), platforms,

2. There are many circuit simulators available today, here are just few of them. They have different flavors (mostly SPICE-based), platforms, 1. 2. There are many circuit simulators available today, here are just few of them. They have different flavors (mostly SPICE-based), platforms, complexity, performance, capabilities, and of course price.

More information

More Moore: Does It Mean Mixed-Signal Integration or Dis-Integration?

More Moore: Does It Mean Mixed-Signal Integration or Dis-Integration? More Moore: Does It Mean Mixed-Signal Integration or Dis-Integration? Ravi Subramanian, Ph.D. Berkeley Design Automation, Inc. 2013 Berkeley Design Automation, Inc. 1 Outline Introduction Structural Shift

More information

Parallel Computing 2020: Preparing for the Post-Moore Era. Marc Snir

Parallel Computing 2020: Preparing for the Post-Moore Era. Marc Snir Parallel Computing 2020: Preparing for the Post-Moore Era Marc Snir THE (CMOS) WORLD IS ENDING NEXT DECADE So says the International Technology Roadmap for Semiconductors (ITRS) 2 End of CMOS? IN THE LONG

More information

Michael S. McCorquodale, Ph.D. Founder and CTO, Mobius Microsystems, Inc.

Michael S. McCorquodale, Ph.D. Founder and CTO, Mobius Microsystems, Inc. Self-Referenced, Trimmed and Compensated RF CMOS Harmonic Oscillators as Monolithic Frequency Generators Integrating Time Michael S. McCorquodale, Ph.D. Founder and CTO, Mobius Microsystems, Inc. 2008

More information

Taheri: A 4-4.8GHz Adaptive Bandwidth, Adaptive Jitter Phase Locked Loop

Taheri: A 4-4.8GHz Adaptive Bandwidth, Adaptive Jitter Phase Locked Loop Engineering, Technology & Applied Science Research Vol. 7, No. 2, 2017, 1473-1477 1473 A 4-4.8GHz Adaptive Bandwidth, Adaptive Jitter Phase Locked Loop Hamidreza Esmaeili Taheri Department of Electronics

More information

Practical Limitations of State of the Art Passive Printed Circuit Board Power Delivery Networks for High Performance Compute Systems

Practical Limitations of State of the Art Passive Printed Circuit Board Power Delivery Networks for High Performance Compute Systems Practical Limitations of State of the Art Passive Printed Circuit Board Power Delivery Networks for High Performance Compute Systems Presented by Chad Smutzer Mayo Clinic Special Purpose Processor Development

More information

FUNDAMENTALS OF ANALOG TO DIGITAL CONVERTERS: PART I.1

FUNDAMENTALS OF ANALOG TO DIGITAL CONVERTERS: PART I.1 FUNDAMENTALS OF ANALOG TO DIGITAL CONVERTERS: PART I.1 Many of these slides were provided by Dr. Sebastian Hoyos January 2019 Texas A&M University 1 Spring, 2019 Outline Fundamentals of Analog-to-Digital

More information