Continuous-Time Systems
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1 Continuous-Time Systems Continuous time waveforms Analog RF High-freq./speed continuous time Radio design community today: analog ~= RF Bluetooth chip (Cambridge Silicon) Mixed-signal Low-freq. Continuous-time IC design community (opamps) Digital + analog/rf tight interaction Mixed-domain includes non-electronic eg: mech., optical Slide 1
2 Applications beyond ICs Internal combustion engine NEMS switch Photonic interconnect Integrated photonic demux Mechanical Optical Energy Nanodevices Biology MEMS disc resonator Energy sources Intracellular reactions Energy-efficient buildings Biological systems Drug design (CADD) Si-InP bulk-process laser Spin-torque devices Carbon nanotubes Energy grids Slide 2
3 Continuous-Time Analysis Fundamentals Modelling: nonlinear differential equations Solving nonlinear equations numerically Solving linear matrix equations numerically Solving differential equations numerically Linearization Frequency-domain concepts Analysing the effects of variability Linear differential equations: steady states Sensitivities Noise: modelling and analysis Slide 3
4 Analog Effects in Digital Electronics 2-input NAND Timing/Delay Correctness Interference/ Noise Slide 4
5 Noise and Variability Geometrical variability Oxide thicknesses: O(10) atoms White noise (time domain) ubiquitous in devices Mechanism similar to biological reactions (inherently stochastic) Spread of parameters showing correlation Time-varying RTS noise (discrete-continuous) RTS noise (freq. domain) Noise/variability are of crucial importance for both analog and digital Impact of device variability (Intel: Shekhar Borkar) Slide 5
6 Analog Issues in Digital (contd.) analog issues becoming show-stoppers analog problems have proliferated clean boolean abstractions much less relevant to actual implementations contributing to Moore's law slowdown analog/mixed-signal key focus at Intel (show Top's slides) Slide 6
7 Start: High-Level System Concept System design starts from simplifications/abstractions Idealized representations: proof of concept simulation/verification Credits: Karim Chabrak. Slide 7
8 Top-Down Design Refinement Manual (skilled) design process: little/no automated synthesis Transceiver block for UMTS Credits: Karim Chabrak. Reference Phase Detector Lowpass Filter VCO Frequency Divider Slide 8
9 Circuit-Level Design (Analog/MS) choose (or invent) ckt topology design loop: most time-consuming step choose parameters... W, L, res/cap values, placement, supplies, s-1000s of runs typical: DC, model and simulate transient, AC, noise, sensitivity, HB,... check simulated performances against desired eg: gain, distortion/im, CMRR, phase margin (stability), lock range, jitter/snr/ber, delay, read/write access times, yield, performances met? exit loop skilled manual process not met? change parameters, retry specialized optimizers (occasionally) too many tries and no success? try other topologies relax desired specs; retry (change system at higher levels to compensate) simulation time: #1 designer complaint some circuits (eg, PLLs) take so long that designs fab without adequate simulation high numbers of chip failures after fab (3-5 respins) Slide 9
10 Bottom Up Validation Transceiver block for UMTS placement/layout + extraction Reference Phase Detector loop: simulate system, validate operation, redesign Lowpass Filter Frequency Divider VCO loop: simulate + redesign extracted ckt embed in system Credits: Karim Chabrak. Slide 10
11 Abstraction-Based Verification too expensive: impractical Credits: Karim Chabrak. Low level models Credits: Karim Chabrak. Reference Phase Detector Lowpass Filter Frequenc y Divider VCO use simpler higher level model Accurate? Consistent? Slide 11
12 The Gap EE Times The primary problem hindering the change to analog top-down design and bottom-up verification has been the lack of tool support for the design process between system-level specification and transistor-level implementation, as well as between transistor implementation and chip fabrication. These missing tools are commonly referred to as The Gap." - EE Times, 2001 Slide 12
13 EE Times on The Gap : continued At this point, you may wonder why you should bother with behavioral libraries and calibration. Why not just submit the transistor-level design to some smart software and let it come up with a model? Unfortunately, despite some claims to the contrary, practical model synthesis is still a long way off. Attempts at this technology rely on pre-existing templates, which are unlikely to exist for leading-edge or proprietary designs. There's no pushbutton approach to analog modeling, and from all indications, this will remain the case for some time to come. - EE Times, 2001 Slide 13
14 Mixed-Signal/Domain Design Today McCorquodale et al, U of Michigan Design Validation many re-spins: the norm Slide 14
15 Design Validation System Verification Flow: the Future Automated abstraction needed to generate higher-level models McCorquodale et al, U of Michigan Slide 15
16 Goal: Automated Macromodelling Low-level model (detailed, big) Macromodelling Higher-level model (consistent, simpler, smaller) Automate! Computational Algorithms Push button generation (fast) Consistency/ Fidelity Accuracy vs Size tradeoffs Slide 16
Continuous-Time Systems
Continuous-Time Systems Continuous time waveforms Analog RF High-freq./speed continuous time Radio design community today: analog ~= RF Bluetooth chip (Cambridge Silicon) Mixed-signal Low-freq. Continuous-time
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