Seating EE 330 Spring 2018

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1 ROW Samuel Willford Kenneth Wendt Tyler Schurk Alvin Rymash Charles Rigsby Yao-Wei Lee Lingkai Lang Brian Kirkpatrick Jacob osse Christopher oodrich Matthew oetzman Leo Freier rant Duncan Timothy Day Zaran Claes Ritika Chakravarty Alex Carpenter Kevin Carlson Zachary Bumstead Jacob Brown William Brandt Adithya Basnayake Kevin Angeliu Derek Nash Cassandra Plata Pengyu Qu Mitchell Hagar Brendon Mcehee Matt Strong 7 Fengnan Yang Yimin Wang David Schmadeke rant Larson Hamish Hay Monte Friestad Abuhjar Ahmed Jiaxin Li Nicholas Parsons Aboullah Al Obaidi 7 8 Jonathan Hugen Omar Elsherbiny Yao Cheah Mir Ahbab Anael Perruchoud Seating EE 330 Spring 2018

2 Bipolar Processes EE 330 Lecture 29 Device Sizes Parasitic Devices JFET Thyristors Thyristors SCR Basic operation

3 Topical Coverage Change Will have several additional lectures on amplifier structures but will temporarily suspend discussion of amplifiers to consider Thyristors This is being done so that the Thyristor laboratory experiments can be conducted this week

4 Outline Bipolar Processes Comparison of MOS and Bipolar Process Parasitic Devices in CMOS Processes JFET Special Bipolar Processes Thyristors SCR TRIAC

5 Review from a Previous Lecture B C E E C vertical npn B A-A Section B C E C B E lateral pnp C B E B C E B-B Section

6 Review from a Previous Lecture D S A-A Section S D p-channel JFET B-B Section

7 Review from a Previous Lecture B C E E C vertical npn B B C E C B lateral pnp E C B E E B C

8 Review from a Previous Lecture Diode (capacitor) S W L D D S D Resistor S p-channel JFET

9 Will consider next the JFET but first some additional information about MOS Devices Enhancement and Depletion MOS Devices Enhancement Mode n-channel devices V T > 0 Enhancement Mode p-channel devices V T < 0 Depletion Mode n-channel devices V T < 0 Depletion Mode p-channel devices V T > 0

10 Enhancement and Depletion MOS Devices n-channel p-channel Enhancement Depletion Depletion mode devices require only one additional mask step Older n-mos and p-mos processes usually had a depletion device and an enhancement device Depletion devices usually not available in CMOS because applications usually do not justify the small increasing costs in processing

11 S The JFET D With V S =0, channel exists under gate between D and S S D Under sufficiently large reverse bias (depletion region widens and channel disappears - pinches off )

12 S The JFET D S D Under smaller reverse bias (depletion region widens and channel thins)

13 S The JFET D S D Under small reverse bias and large negative V DS (channel pinches off)

14 The JFET D D S D S n-channel S p-channel p-channel JFET Square-law model of p-channel JFET 0 VS VP 2IDSSp VDS ID S P DS V -V - V VS VP V S+0.3 V DS> VS -VP VP 2 2 V S IDSSp VS VP V DS< V S-VP VP (I DSSp carries negative sign) Functionally identical to the square-law model of MOSFET Parameters I DSS and V P characterize the device I DSS proportional to W/L where W and L are width and length of n+ diff V P is negative for n-channel device, positive for p-channel device thus JFET is depletion mode device Must not forward bias S junction by over about 300mV or excessive base current will flow (red constraint) Widely used as input stage for bipolar op amps

15 The JFET D D S D S n-channel S p-channel n-channel JFET (not available in this process) Square-law model of n-channel JFET 0 VS VP 2IDSS VDS I V -V - V V V VS V < V -V VP 2 2 V S IDSS VS VP VDS > VS -VP VP D S P DS S P DS S P Functionally identical to the square-law model of MOSFET Parameters I DSS and V P characterize the device I DSS proportional to W/L where W and L are width and length of n+ diff V P is negative for n-channel device, positive for p-channel device thus JFET is depletion mode device Must not forward bias S junction by over about 300mV or excessive base current will flow (red constraint) Widely used as input stage for bipolar op amps

16 The Schottky Diode C A Metal-Semiconductor Junction One contact is ohmic, other is rectifying Not available in all processes Relatively inexpensive adder in some processes Lower cut-in voltage than pn junction diode High speed

17 The MESFET S D Metal-Semiconductor Junction for ate Drain and Source contacts ohmic, other is rectifying Usually not available in standard CMOS processes Must not forward bias very much Lower cut-in voltage than pn junction diode High speed

18 The Thyristor A bipolar device in CMOS Processes Consider a Bulk-CMOS Process S D S D p n p n Have formed a lateral pnpn device! Will spend some time studying pnpn devices

19 MOS and Bipolar Area Comparisions How does the area required to realize a MOSFET compare to that required to realize a BJT? Will consider a minimum-sized device in both processes

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22 Consider Initially the Emitter in the BJT surrounded by a base region

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25 From design rules (left to right) 4.3, 5.1, 5.4, 5.6,

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27 Add n+ buried for collector From design rule

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29 Add n-epi region from design rules 2.3 and

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31 1 5 Add contact to n-epi region from design rules 2.3 and

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34 1 5 But, there are some rather strict rules relating to the epi contact from (left to right) rules 4.4, 5.4, NOT TO SCALE Note: 26 required Between p-base and isolation diffusion 55

35 Consider a structure with a collector contact on both sides of epi Note: Not to vertical Scale Note: 26 required Between p-base and isolation diffusion

36 Note: Not to vertical Scale Note: 26 required Between p-base and isolation diffusion 50 55

37 Note: Not to vertical Scale 50 55

38 Note: Not to vertical Scale Bounding Area = Major contributor to large size of BJT is the isolation diffusion which diffuses laterally a large distance beyond the drawn edges of the isolation mask

39 Comparison with Area for n-channel MOSFET in Bulk CMOS Bounding Area =

40 Minimum-Sized MOSFET Bounding Area = Active Area =

41 MOSFET BJT Note: Not to vertical Scale

42 Area Comparison between BJT and MOSFET BJT Area = n-channel MOSFET Area = Area Ratio = 21:1

43 Two-Port Amplifier Models Bipolar Processes Comparison of MOS and Bipolar Process Parasitic Devices in CMOS Processes JFET Special Bipolar Processes Thyristors SCR TRIAC Outline

44 Thyristors The good and the bad!

45 Thyristors The good SCRs Triacs The bad Parasitic Device that can destroy integrated circuits

46 The SCR Silicon Controlled Rectifier Widely used to switch large resistive or inductive loads Widely used in the power electronics field Widely used in consumer electronic to interface between logic and power Anode A ate C Cathode Usually made by diffusions in silicon p n p n A A A C C C Symbols Consider first how this 4-layer 3-junction device operates

47 Operation of the SCR A I F A p n p I C V F n V C A I F A C 1 n n B 1 p p C 2 E 1 n C Not actually separated but useful for describing operation p E 2 B 2 I C1 Q 1 I B2 C Q 2 I C2 I B1 I

48 Variation of Current ain (β) with Bias for BJT Note that current gain gets very small at low base current levels

49 I Operation of the SCR I A C I F p n p n C 1 n n B 1 p p C 2 E 1 n V F C I C1 Q 1 I B2 I F I B1 A p Q 2 A I C2 I E 2 B 2 Consider a small positive bias (voltage or current) on the gate (V C <0.5V) and a positive and large voltage V F Will have VC1 VF - 0.5V Thus Q 1 has a large positive voltage on its collector Since VB E1 is small, I C1 will be small as will I C2 so diode equation governs BE junction of Q 1 I F will be very small C

50 Operation of the SCR A I F C 1 n n B 1 p p C 2 E 1 n C I F A p A E 2 B 2 I I C p n p n V F I C1 Q 1 I B2 C I B1 Q 2 I C2 I Now let bias on the gate increase (V C around 0.6V) so Q 1 and Q 2 in FA V V - 0.5V C1 F From diode equation, base voltage V BE1 will increase and collector current I C1 will increase Thus base current I B2 will increase as will the collector current of I C2 Under assumption of operation in FA region get expression I = I + β β I B1 1 2 B1 This is regenerative feedback (actually can show pole in RHP)

51 Very Approximate Analysis Showing RHP Pole A R L I C1 I B2 I F A Q 2 C 1 n n B 1 p p C 2 E 1 n C p E 2 B 2 V CC V F Q 1 I C2 V C I B1 CB I I V I RBE sr C 1 BE B 1 2 V sc I I I I B B1 C 2 I C2 1 2 B1 I R V B1 BE p R C BE B

52 Operation of the SCR V V - 0.6V C1 F Under assumption of operation in FA region get expression I B1 = I + β1β 2IB1 What will happen with this is regenerative feedback? If I is small (and thus β 1 and β 2 are small) I F will be very small If I larger but less than, β β I will continue to flow 1 2 B1 it can be removed and current I C1 will continue to increase and drive Q 1 into SAT This will try to drive V A towards 0.9V (but forced to be V F!) The current in V F will go towards The SCR will self-destruct because of excessive heating! C 1 n n B 1 p p C 2 E 1 n Too bad the circuit self-destructed because the small gate current was able to control a lot of current! V F C I C1 Q 1 I B2 C I F I B1 A Q 2 I C2 A p I E 2 B 2 I

53 Operation of the SCR Consider a modified application by adding a load (depicted as R L ) V I A C I F p n p n V F R L V CC R L V CC V F I C1 Q 1 I B2 C I F A Q 2 I C2 I B1 I V I All operation is as before, but now, after the triggering occurs, the voltage V F will drop to approximately 0.8 V and the voltage V CC -.8 will appear across R L If V CC is very large, the SCR has effectively served as a switch putting V CC across the load and after triggering occurs, I can be removed! But, how can we turn it off? Will discuss that later

54 Operation of the SCR SCR model I f V, V F 1 F I f V 2 I V I F A C V F As for MOSFET, Diode, and BJT, several models for SCR can be developed The Ideal SCR Model 1, IF f1 IA VF, V or 2 I f V I f V I F I F I f V I 2I

55 Operation of the SCR Consider the Ideal SCR Model I f V I F 1 I F, I f V 2I I V I F A C V F I F I =0 I H is very small I H V BF0 V F I F I =I 1 >0 I 1 is small (but not too small) I H V F V BF1

56 Operation of the SCR Operation with the Ideal SCR V CC R L Load Line: Analysis: V CC = IFR L+VF V CC = IFR L+VF I f V I F 1 I F, V I I F VF The solution of these two equations is at the intersection of the load line and the device characteristics I H V R CC L I F I =0 Load Line V CC when I =0 V F Note three intersection points Two (upper and lower) are stable equilibrium points, one is not When operating at upper point, V F =0 so V CC appears across R L We say SCR is ON When operating at lower point, I F approx 0 so no signal across R L We say SCR is OFF When I =0, will stay in whatever state it was in

57 Operation of the SCR Operation with the Ideal SCR I F A I f V I F 1 I F, I C V F I F V On State I =0 V F Off State For notational convenience will drop subscript unless emphasis is needed I f V, I I f V I F 1 I F, F F

58 Operation of the SCR V CC Operation with the Ideal SCR R L Now assume it was initially in the OFF state and then a gate current was applied I I F VF I H V R CC L I F I =0 Load Line V CC V F V CC = IFR L+VF I f V, I F F V V R CC L I F Load Line Now there is a single intersection point so a unique solution The SCR is now ON I H I =I 1 >0 V CC V F Removing the gate current will return to the previous solution (which has 3 intersection points) but it will remain in the ON state

59 Operation of the SCR Operation with the Ideal SCR V CC R L Turning SCR off when I =0 V R CC L I F Load Line V I I F VF I H I =0 V CC V BF0 V F Reduce V CC so that V CC /R L goes below I H This will provide a single intersection point V CC can then be increased again and SCR will stay off Must not increase V CC much above V BF0 else will turn on

60 Operation of the SCR Operation with the Ideal SCR V CC R L Turning SCR off when I =0 I F VF I V R CC L I F V Load Line I H I =0 V CC V BF0 V F

61 Operation of the SCR V CC Operation with the Ideal SCR Often V CC is an AC signal (often 110V) I F R L VF SCR will turn off whenever AC signal goes negative I V V R CC L I F Load Line I H I =0 V CC V BF0 V F V R CC L

62 Operation of the SCR V CC Operation with the Ideal SCR Often V CC is an AC signal (often 110V) I F R L VF SCR will turn off whenever AC signal goes negative I V V R CC L I F Load Line I H I =0 V CC V BF0 V F V R CC L

63 Operation of the SCR Operation with the Ideal SCR V CC R L Turning SCR off when I >0 I F VF V R CC L I F Load Line V I I H I =I 1 >0 V CC V F V R Reduce V CC so that V CC /R L goes below I H This will provide a single intersection point CC L But when V CC is then increased SCR will again turn on Will not turn off if I is very large

64 End of Lecture 29