Dual 160 MHz Rail-to-Rail Amplifier AD8042

Transcription

1 a FEATURES Single AD and Quad AD also Available Fully Specified at + V, + V, and V Supplies Output Swings to Within mv of Either Rail Input Voltage Range Extends mv Below Ground No Phase Reversal with Inputs. V Beyond Supplies Low Power of. ma per Amplifier High Speed and Fast Settling on V: MHz db Bandwidth (G = +) V/ s Slew Rate 9 ns Settling Time to.% Good Video Specifications (R L =, G = +) Gain Flatness of. db to MHz.% Differential Gain Error. Differential Phase Error Low Distortion dbc Worst MHz Drives ma. V from Supply Rails APPLICATIONS Video Switchers Distribution Amplifiers A/D Driver Professional Cameras CCD Imaging Systems Ultrasound Equipment (Multichannel) PRODUCT DESCRIPTION The AD is a low power voltage feedback, high speed amplifier designed to operate on + V, + V, or ± V supplies. It has true single supply capability with an input voltage range extending mv below the negative rail and within V of the positive rail. V.V V V G = R L = k TO +.V s Figure. Output Swing: Gain =, V S = + V CONNECTION DIAGRAM -Lead Plastic DIP and SOIC OUT IN +IN V S Dual MHz Rail-to-Rail Amplifier AD AD 7 +V S OUT The output voltage swing extends to within mv of each rail, providing the maximum output dynamic range. Additionally, it features gain flatness of. db to MHz while offering differential gain and phase error of.% and. on a single V supply. This makes the AD useful for professional video electronics such as cameras, video switchers, or any high speed portable equipment. The AD s low distortion and fast settling make it ideal for buffering single supply, high speed A/D converters. The AD offers low power supply current of ma max and can run on a single. V power supply. These features are ideally suited for portable and battery powered applications where size and power are critical. The wide bandwidth of MHz along with V/µs of slew rate on a single V supply make the AD useful in many general purpose, high speed applications where single supplies from. V to V and dual power supplies of up to ± V are needed. The AD is available in -lead plastic DIP and SOIC. CLOSED LOOP GAIN db 9 9 G = + C L = pf R L = k TO.V IN +IN Figure. Frequency Response REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9, Norwood, MA -9, U.S.A. Tel: 7/9-7 Fax: 7/-7 Analog Devices, Inc.,

2 AD SPECIFICATIONS T A = C, V S = V, R L = k to. V, unless otherwise noted.) ADA Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE db Small Signal Bandwidth, V O <. V p-p G = + MHz Bandwidth for. db Flatness G = +, R L = Ω. R F = Ω MHz Slew Rate G =, V O = V Step V/µs Full Power Response V O = V p-p MHz Settling Time to % G =, V O = V Step ns Settling Time to.% 9 ns NOISE/DISTORTION PERFORMANCE Total Harmonic Distortion f C = MHz, V O = V p-p, G = +, R L = kω 7 db Input Voltage Noise f = khz nv/ Hz Input Current Noise f = khz 7 fa/ Hz Differential Gain Error (NTSC, IRE) G = +, R L = Ω to. V.. % G = +, R L = 7 Ω to. V. % Differential Phase Error (NTSC, IRE) G = +, R L = Ω to. V.. Degrees G = +, R L = 7 Ω to. V. Degrees Worst Case Crosstalk f = MHz, R L = Ω to. V db DC PERFORMANCE Input Offset Voltage 9 mv T MIN T MAX mv Offset Drift µv/ C Input Bias Current.. µa T MIN T MAX. µa Input Offset Current.. µa Open-Loop Gain R L = kω 9 db T MIN T MAX 9 db INPUT CHARACTERISTICS Input Resistance kω Input Capacitance. pf Input Common-Mode Voltage Range. to + V Common-Mode Rejection Ratio V CM = V to. V 7 db OUTPUT CHARACTERISTICS Output Voltage Swing R L = kω to. V. to.97 V Output Voltage Swing: R L = kω to. V. to.9. to.9 V Output Voltage Swing: R L = Ω to. V. to.. to. V Output Current T MIN to T MAX, V OUT =. V to. V ma Short Circuit Current Sourcing 9 ma Sinking ma Capacitive Load Drive G = + pf POWER SUPPLY Operating Range V Quiescent Current (Per Amplifier).. ma Power Supply Rejection Ratio V S = V to V, or V S+ = + V to + V 7 db OPERATING TEMPERATURE RANGE + C Specifications subject to change without notice. REV. B

3 SPECIFICATIONS T A = C, V S = V, R L = k to. V, unless otherwise noted.) AD ADA Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE db Small Signal Bandwidth, V O <. V p-p G = + MHz Bandwidth for. db Flatness G = +, R L = Ω, R F = Ω MHz Slew Rate G =, V O = V Step 7 V/µs Full Power Response V O = V p-p MHz Settling Time to % G =, V O = V Step ns Settling Time to.% ns NOISE/DISTORTION PERFORMANCE Total Harmonic Distortion f C = MHz, V O = V p-p, G =, R L = Ω db Input Voltage Noise f = khz nv/ Hz Input Current Noise f = khz fa/ Hz Differential Gain Error (NTSC, IRE) G = +, R L = Ω to. V, Input V CM = V. % R L = 7 Ω to. V, Input V CM = V. % Differential Phase Error (NTSC, IRE) G = +, R L = Ω to. V, Input V CM = V. Degrees R L = 7 Ω to. V, Input V CM = V.7 Degrees Worst Case Crosstalk f = MHz, R L = kω to. V db DC PERFORMANCE Input Offset Voltage 9 mv T MIN T MAX mv Offset Drift µv/ C Input Bias Current.. µa T MIN T MAX. µa Input Offset Current.. µa Open-Loop Gain R L = kω 9 db T MIN T MAX 9 db INPUT CHARACTERISTICS Input Resistance kω Input Capacitance. pf Input Common-Mode Voltage Range. to + V Common-Mode Rejection Ratio V CM = V to. V 7 db OUTPUT CHARACTERISTICS Output Voltage Swing R L = kω to. V. to.97 V Output Voltage Swing: R L = kω to. V. to.9. to.9 V Output Voltage Swing: R L = Ω to. V. to.. to. V Output Current T MIN to T MAX, V OUT =. V to. V ma Short Circuit Current Sourcing ma Sinking 7 ma Capacitive Load Drive G = + 7 pf POWER SUPPLY Operating Range V Quiescent Current (Per Amplifier).. ma Power Supply Rejection Ratio V S = V to V, or V S+ = + V to + V db OPERATING TEMPERATURE RANGE 7 C Specifications subject to change without notice. REV.B

4 AD SPECIFICATIONS T A = C, V S = V, R L = k to V, unless otherwise noted.) ADA Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE db Small Signal Bandwidth, V O <. V p-p G = + 7 MHz Bandwidth for. db Flatness G = +, R L = Ω, R F = Ω MHz Slew Rate G =, V O = V Step V/µs Full Power Response V O = V p-p MHz Settling Time to % G =, V O = V Step ns Settling Time to.% ns NOISE/DISTORTION PERFORMANCE Total Harmonic Distortion f C = MHz, V O = V p-p, G = +, R L = kω 7 db Input Voltage Noise f = khz nv/ Hz Input Current Noise f = khz 7 fa/ Hz Differential Gain Error (NTSC, IRE) G = +, R L = Ω.. % G = +, R L = 7 Ω. % Differential Phase Error (NTSC, IRE) G = +, R L = Ω.. Degrees G = +, R L = 7 Ω. Degrees Worst Case Crosstalk f = MHz, R L = Ω db DC PERFORMANCE Input Offset Voltage 9. mv T MIN T MAX mv Offset Drift µv/ C Input Bias Current.. µa T MIN T MAX. µa Input Offset Current.. µa Open-Loop Gain R L = kω 9 9 db T MIN T MAX db INPUT CHARACTERISTICS Input Resistance kω Input Capacitance. pf Input Common-Mode Voltage Range. to + V Common-Mode Rejection Ratio V CM = V to +. V 7 db OUTPUT CHARACTERISTICS Output Voltage Swing R L = kω.97 to +.97 V Output Voltage Swing: R L = kω. to +..9 to +.9 V Output Voltage Swing: R L = Ω to +.. to +. V Output Current T MIN to T MAX, V OUT =. V to +. V ma Short Circuit Current Sourcing ma Sinking ma Capacitive Load Drive G = + pf POWER SUPPLY Operating Range V Quiescent Current (Per Amplifier) 7 ma Power Supply Rejection Ratio V S = V to V, or V S+ = + V to + V db OPERATING TEMPERATURE RANGE + C Specifications subject to change without notice. REV. B

5 AD ABSOLUTE MAXIMUM RATINGS Supply Voltage V Internal Power Dissipation Plastic DIP Package (N) W Small Outline Package (R) W Input Voltage (Common Mode) ±V S ±. V Differential Input Voltage ±. V Output Short Circuit Duration Observe Power Derating Curves Storage Temperature Range (N, R) C to + C Lead Temperature Range (Soldering sec) C NOTES Stresses above those listed under Absolute Maximum Ratings may cause perm nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Specification is for the device in free air: -Lead Plastic DIP Package: θ JA = 9 C/W -Lead SOIC Package: θ JA = C/W MAXIMUM POWER DISSIPATION The maximum power that can be safely dissipated by the AD is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately C. Exceeding this limit temporarily may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 7 C for an extended period can result in device failure. While the AD is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature ( C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves. MAXIMUM POWER DISSIPATION W.... -LEAD PLASTIC-DIP PACKAGE -LEAD SOIC PACKAGE T J = C 7 9 AMBIENT TEMPERATURE C Figure. Maximum Power Dissipation vs. Temperature ORDERING GUIDE Supply Temperature Package Package Model Voltages Range Description Option ADAN V, ± V C to + C -Lead Plastic DIP N- ADAN V C to 7 C -Lead Plastic DIP N- ADAR V, ± V C to + C -Lead Plastic SOIC SO- ADAR V C to 7 C -Lead Plastic SOIC SO- ADAR-REEL C to + C " Tape and REEL SO- ADAR-REEL7 C to + C 7" Tape and REEL SO- ADACHIPS C to + C Die CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. B

6 AD Typical Performance Characteristics FREQUENCY 9 7 T = C PARTS, SIDE A & B MEAN =.mv STD DEVIATION =. SAMPLE SIZE = ( ADS) OPEN-LOOP GAIN db 9 9 T = C 7 V OS mv TPC. Typical Distribution of V OS LOAD RESISTANCE TPC. Open-Loop Gain vs. R L to. V FREQUENCY MEAN =. V/ C STD DEV =. V/ C SAMPLE SIZE = OPEN-LOOP GAIN db R L = k V OS DRIFT V/ C TPC. V OS Drift Over C to + C TEMPERATURE C TPC. Open-Loop Gain vs. Temperature INPUT BIAS CURRENT A V CM = V OPEN-LOOP GAIN db 9 7 R L = TO.V R L = TO.V.. 7 TEMPERATURE C TPC. I B vs. Temperature OUTPUT VOLTAGE V TPC. Open-Loop Gain vs. Output Voltage REV. B

7 AD INPUT VOLTAGE NOISE nv/ Hz k k k M M M G FREQUENCY Hz TPC 7. Input Voltage Noise vs. Frequency DIFFERENTIAL GAIN ERROR % DIFFERENTIAL PHASE ERROR deg. NTSC Subcarrier (.79 MHz) G = + R L = TO.V G = + R L = TO.V V S = V G = + R L = V S = V G = + R L =. 7 9 MODULATING RAMP LEVEL IRE TPC. Differential Gain and Phase Errors. TOTAL HARMONIC DISTORTION dbc 7, A V =, R L = TO.V, A V =, R L = TO.V 9, A V =, R L = k TO.V V S = V, A V =, R L = TO.V, A V =, R L = k TO.V NORMALIZED GAIN db MHz G = + R F = R L = TO.V 7 9 FUNDAMENTAL TPC. Total Harmonic Distortion. TPC.. db Gain Flatness WORST HARMONIC dbc 7 9 MHz MHz MHz, G = +, R L = k TO.V OPEN LOOP GAIN db PHASE GAIN G = + R F = R L = TO.V 9 PHASE Degrees OUTPUT VOLTAGE V p-p TPC 9. Worst Harmonic vs. Output Voltage.. 7 TPC. Open-Loop Gain and Phase vs. Frequency REV. B 7

8 AD CLOSED LOOP GAIN db G = + C L = pf R L = k TO.V T = C T = + C T = + C TPC. Closed-Loop Frequency Response vs. Temperature SETTING TIME ns G = R L = k TO MIDPOINT C L = pf V S = +V,.% V S = V,.% V S = +V, % V S = V,.% V S = V, % V S = V, %.. BIPOLAR INPUT STEP V TPC. Settling Time CLOSED LOOP GAIN db G = + C L = pf R L = k V S = V R L & C L TO.V R L & C L TO.V V S = V COMMON-MODE REJECTION db 7 TEST CIRCUIT:.k.k IN CM.k.k OUT Vs = V 9 k k M M M FREQUENCY Hz M TPC. Closed-Loop Frequency Response vs. Supply TPC 7. CMRR vs. Frequency OUTPUT RESISTANCE.. G = + R BT V OUT R BT = R BT =.. TPC. Output Resistance vs. Frequency OUTPUT SATURATION VOLTAGE V. V S = +V.7 +V V OH (+ C). +V V OH (+ C) +V V OH ( C).... +V OL (+ C). +V OL (+ C) +V OL ( C) LOAD CURRENT ma TPC. Output Saturation Voltage vs. Load Current EV. B

9 AD SUPPLY CURRENT ma V S = V V S = +V V S = +V % OVERSHOOT V S = +V V OUT = mv STEP G = + G = +. 7 TEMPERATURE C 9 LOAD CAPACITANCE pf TPC 9. Supply Current vs. Temperature TPC. % Overshoot vs. Load Capacitance V S = +V V S = +V R F = k R L = k TO +.V PSRR db 7 PSRR +PSRR NORMALIZED GAIN db G = + G = + G = + G = + R F = 9 k k M M M FREQUENCY Hz M TPC. PSRR vs. Frequency TPC. Frequency Response vs. Closed-Loop Gain OUTPUT VOLTAGE V p-p 9 7 V S = V R L = k G =.... TPC. Output Voltage Swing vs. Frequency CROSSTALK db V S = +V V IN =.V p-p G = + R F = k V OUT V OUT, R L = k TO +.V V OUT, R L = TO +.V V OUT 7 V OUT V OUT, R L = TO +.V 9 V OUT V OUT, R L = k TO +.V. TPC. Crosstalk (Output-to-Output) vs. Frequency REV. B 9

10 AD V V V.77V V S = +V G = R L = TO +.V +.V A V = + V S = +V V IN = mv p-p R L = k TO.V C L = pf +.V V V V.V.V s +.V mv ns TPC a. Output Swing with Load Reference to Supply Midpoint TPC 7. mv Pulse Response, V S = + V V V.9V V S = +V G = R L = TO GND V G = R L = k TO +.V V.V V V.V V V.V s.v s TPC b. Output Swing with Load Reference to Negative Supply TPC. Rail-to-Rail Output Swing, V S = + V.V.V A V = + V S = +V C L = pf R L = k TO +.V V IN = V p-p +.V V IN = mv p-p R L = k TO.V V S = +V C L = pf A V = +V.V +.V.V.V.V ns +.V mv ns TPC. One Volt Pulse Response, V S = + V TPC 9. mv Pulse Response, V S = + V REV. B

11 AD Overdrive Recovery Overdrive of an amplifier occurs when the output and/or input range are exceeded. The amplifier must recover from this overdrive condition. As shown in Figure, the AD recovers within ns from negative overdrive and within ns from positive overdrive. shown). This circuit topology allows the AD to drive ma of output current with the outputs within. V of the supply rails. On the input side, the device can handle voltages from. V below the negative rail to within. V of the positive rail. Exceeding these values will not cause phase reversal; however, the input ESD devices will begin to conduct if the input voltages exceed the rails by greater than. V. +V +.V V V V S = +V V IN = +V p-p G = + R L = k TO +.V ns DRIVING CAPACITIVE LOADS The capacitive load drive of the AD can be increased by adding a low valued resistor in series with the load. Figure shows the effects of a series resistor on capacitive drive for varying voltage gains. As the closed-loop gain is increased, the larger phase margin allows for larger capacitive loads with less overshoot. Adding a series resistor with lower closed-loop gains accomplishes this same effect. For large capacitive loads, the frequency response of the amplifier will be dominated by the roll-off of the series resistor and capacitive load. Figure. Overdrive Recovery Circuit Description The AD is fabricated on Analog Devices proprietary extra-fast Complementary Bipolar (XFCB) process which enables the construction of PNP and NPN transistors with similar f T s in the GHz GHz region. The process is dielectrically isolated to eliminate the parasitic and latch-up problems caused by junction isolation. These features allow the construction of high frequency, low distortion amplifiers with low supply currents. This design uses a differential output input stage to maximize bandwidth and headroom (see Figure ). The smaller signal swings required on the first stage outputs (nodes SP, SN) reduce the effect of nonlinear currents due to junction capacitances and improve the distortion performance. With this design harmonic distortion of better than 77 MHz into Ω with V OUT = V p-p (Gain = +) on a single V supply is achieved. V CC V IN P V IN N V EE R Q C7 I R R Q7 Q Q Q R I R9 Q V EE SIP Q SIN R Q I I R Q Q Q R R7 Q7 Q Q Q7 Q I7 Q9 Q Q7 Q Figure. AD Simplified Schematic I9 V EE V CC I I C C9 Q V OUT The AD s rail-to-rail output range is provided by a complementary common-emitter output stage. High output drive capability is provided by injecting all output stage predriver currents directly into the bases of the output devices Q and Q. Biasing of Q and Q is accomplished by I and I, along with a common-mode feedback loop (not Q CAPACITIVE LOAD pf mv STEP WITH % OVERSHOOT R S = R S C L R S = R S = CLOSED-LOOP GAIN V/V Figure. Capacitive Load Drive vs. Closed-Loop Gain Single Supply Composite Video Line Driver The two op amps of an AD can be configured as a single supply dual line driver for composite video. The wide signal swing of the AD enables this function to be performed without using any type of clamping or dc restore circuit which can cause signal distortion. Figure 7 shows a schematic for a circuit that is driven by a single composite video source that is ac coupled, level shifted and applied to both + inputs of the two amplifiers. Each op amp provides a separate 7 Ω composite video output. To obtain single supply operation, ac coupling is used throughout. The large capacitor values are required to ensure that there is minimal tilting of the video signals due to their low frequency ( Hz) signal content. The circuit shown was measured to have a differential gain of.% and a differential phase of.. The input is terminated in 7 Ω and ac coupled via C IN to a voltage divider that provides the dc bias point to the input. Setting the optimal bias point requires some understanding of the nature of composite video signals and the video performance of the AD. REV. B

12 AD COMPOSITE VIDEO IN 7.99k k F R G k.99k +V R G k F R F k.µf 7 R F k F F. F F. F F R T 7 R T 7 7 COAX R L 7 R L 7 V OUT V OUT Figure 7. Single Supply Composite Video Line Driver Using AD Signals of bounded peak-to-peak amplitude that vary in duty cycle require larger dynamic swing capability than their peak-topeak amplitude after ac coupling. As a worst case, the dynamic signal swing required will approach twice the peak-to-peak value. The two bounding cases are for a duty cycle that is mostly low, but occasionally goes high at a fraction of a percent duty cycle and vice versa. Composite video is not quite this demanding. One bounding extreme is for a signal that is mostly black for an entire frame, but has a white (full intensity), minimum width spike at least once per frame. The other extreme is for a video signal that is full white everywhere. The blanking intervals and sync tips of such a signal will have negative going excursions in compliance with composite video specifications. The combination of horizontal and vertical blanking intervals limit such a signal to being at its highest level (white) for only about 7% of the time. As a result of the duty cycle variations between the two extremes presented above, a V p-p composite video signal that is multiplied by a gain of two requires about. V p-p of dynamic voltage swing at the output for an op amp to pass a composite video signal of arbitrary duty cycle without distortion. Some circuits use a sync tip clamp along with ac coupling to hold the sync tips at a relatively constant level in order to lower the amount of dynamic signal swing required. However, these circuits can have artifacts like sync tip compression unless they are driven by sources with very low output impedance. The AD not only has ample signal swing capability to handle the dynamic range required without using a sync tip clamp, but also has good video specifications like differential gain and differential phase when buffering these signals in an ac-coupled configuration. To test this, the differential gain and differential phase were measured for the AD while the supplies were varied. As the lower supply is raised to approach the video signal, the first effect to be observed is that the sync tips become compressed before the differential gain and differential phase are adversely affected. Thus, there must be adequate swing in the negative direction to pass the sync tips without compression. As the upper supply is lowered to approach the video, the differential gain and differential phase were not significantly adversely affected until the difference between the peak video output and the supply reached. V. Thus, the highest video level should be kept at least. V below the positive supply rail. Taking the above into account, it was found that the optimal point to bias the noninverting input is at. V dc. Operating at this point, the worst case differential gain is measured at.% and the worst-case differential phase is.. The ac-coupling capacitors used in the circuit at first glance appear quite large. A composite video signal has a lower frequency band edge of Hz. The resistances at the various ac coupling points especially at the output are quite small. In order to minimize phase shifts and baseline tilt, the large value capacitors are required. For video system performance that is not to be of the highest quality, the value of these capacitors can be reduced by a factor of up to five with only a slightly observable change in the picture quality. Single-Ended-to-Differential Driver Using a cross-coupled single-ended-to-differential converter, the AD makes a good general purpose differential line driver. This can be used for applications such as driving category twisted pair wire which is becoming common for data communications in buildings. Figure shows a configuration for a circuit that performs this function that can be used for video transmission over a differential pair or various data communication purposes. V IN AD R B k +V R A k R A k 7 AMP V. F R IN k R F k AMP 9.9 R B k. F F.. F m Figure. Single-Ended-to-Differential Twisted Pair Line Driver V OUT REV. B

13 AD Each of the AD s op amps is configured as a unity gain follower by the feedback resistors (R A ). Each op amp output also drives the other as a unity gain inverter via the two R B s, creating a totally symmetrical circuit. If the + input to Amp is grounded and a small positive signal is applied to the + input of Amp, the output of Amp will be driven to saturation in the positive direction and the input of Amp driven to saturation in the negative direction. This is similar to the way a conventional op amp behaves without any feedback. If a resistor (R F ) is connected from the output of Amp to the + input of Amp, negative feedback is provided which closes the loop. An input resistor (R I ) will make the circuit look like a conventional inverting op amp configuration with differential outputs. The gain of this circuit from input to either output will be ±R F /R I. Or the single-ended-to-differential gain will be R F /R I. This gives the circuit the advantage of being able to adjust its gain by changing a single resistor. The cable has a characteristic impedance of about Ω. Each driver output is back terminated with a pair of. Ω resistors to make the source look like Ω. The receive end is terminated with Ω, and the signal is measured differentially with a pair of scope probes. One channel on the oscilloscope is inverted and then the signals are added. The scope photo in Figure 9 shows a MHz, V p-p input signal driving the circuit with m of category twisted pair wire. V 9 IN V mv ns. F V IN.9k.9k AD +V +V k +V k. F k +V. F +V. F +V. F k k DV DD AV DD AV DD k V IN A OTR BIT 7 V IN B BIT BIT. F CAPT BIT 9. F AD9 BIT /. F CAPB BIT 7. F BIT7 V REF 7 BIT SENSE BIT9 CML BIT. F BIT CLOCK CLK BIT REFCOM DV SS AV SS AV SS 9 7 Figure. AD Differential Driver for the AD9 -Bit, MSPS A/D Converter The circuit was tested with a MHz input signal and clocked at MHz. An FFT response of the digital output is shown in Figure. Pin is biased at. V by the voltage divider and bypassed. This biases each output at. V. V IN is ac coupled such that V IN going positive makes V IN A go positive and V IN B go in the negative direction. The opposite happens for a negative going V IN. V OUT % mv Figure 9. Differential Driver Frequency Response Single Supply Differential A/D Driver The single-ended-to-differential converter circuit is also useful as a differential driver for video speed, single-ended, differential input A/D converters. Figure is a schematic that shows such a circuit differentially driving an AD9, a -bit, MSPS A/D converter. VERTICAL SCALE db/div FUND FRQ 977 SMPL FRQ 9 7 THD. SNR 7. SINAD 7.79 SFDR.7 HARMONICS (dbc) nd. rd.7 th 99. th 9.7 th th 9. th 97. 9th 9. Figure. FFT of AD9 Output When Driven by AD REV. B

14 AD HDSL Line Driver HDSL or high-bit-rate digital subscriber line is becoming popular as a means to provide data communication at DS rates (. MBPS) over moderate distances via conventional telephone twisted pair wires. In these systems, the transceiver at the customer s end is sometimes powered via the twisted pair from a power source at the central office. It is sometimes required to raise the dc voltage of the power source to compensate for IR drops in long lines or lines with narrow gauge wires. Because of this, it is highly desirable to keep the power consumption of the customer s transceiver as low as possible. One means to realize significant power savings is to run the transceiver from a ±V supply instead of the more conventional ± V. The high output swing and current drive capability of the AD make it ideally suited to this application. Figure shows a circuit for the analog portion of an HDSL transceiver using the AD as the line driver. V IN. F k k k 7 / AD k / AD ATT 7AF 9DJ9 7 V OUT Layout Considerations The specified high speed performance of the AD requires careful attention to board layout and component selection. Proper RF design techniques and low-pass parasitic component selection are necessary. The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low impedance path. The ground plane should be removed from the area near the input pins to reduce the stray capacitance. Chip capacitors should be used for the supply bypassing. One end should be connected to the ground plane and the other within / inch of each power pin. An additional large (.7 µf µf) tantalum electrolytic capacitor should be connected in parallel, but not necessarily so close, to supply current for fast, large signal changes at the output. The feedback resistor should be located close to the inverting input pin in order to keep the stray capacitance at this node to a minimum. Capacitance variations of less than pf at the inverting input will significantly affect high speed performance. Stripline design techniques should be used for long signal traces (greater than about inch). These should be designed with a characteristic impedance of Ω or 7 Ω and be properly terminated at each end. 9.7 F 9 k k k k k / AD 9 V REC. F Figure. HDSL Line Driver REV. B

15 AD OUTLINE DIMENSIONS -Lead Plastic Dual-in-Line Package [PDIP] (N-) Dimensions shown in inches and (millimeters).99 (.9). (.).799 (7.). (.) PIN.9 (.) MAX.9 (.). (.9). (.). (.). (.) BSC.97 (.77). (.).9 (.). (.).99 (.) MIN SEATING PLANE. (.). (7.).99 (.9). (.9). (.).79 (.) -Lead Standard Small Outline Package [SOIC] Narrow Body (R-) Dimensions shown in millimeters and (inches). (.9). (.9). (.7). (.97). (.). (.) Revision History PIN COPLANARITY. (.9). (.).7 (.) BSC. (.). (.).7 (.). (.) SEATING PLANE. (.9).9 (.7). (.9). (.99).7 (.). (.7) CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MS- AA Location Page 7/ Data Sheet changed from REV. A to REV. B. Changes to SPECIFICATIONS REV. B

16 PRINTED IN U.S.A. C9 7/(B)