SILICON CARBIDE (SiC) is an excellent material for the

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1 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 2, FEBRUARY Repetitive-Avalanche-Induced Electrical Parameters Shift for 4H-SiC Junction Barrier Schottky Diode Siyang Liu, Chao Yang, Weifeng Sun, Senior Member, IEEE, Qingsong Qian, Yu Huang, Xing Wu, Minjun Wu, Qingling Yang, and Litao Sun Abstract The electrical parameters shift of 4H-SiC junction barrier Schottky diode under the repetitive avalanche current stress has been experimentally investigated. Using technical computer-aided design simulation and high resolution transmission electron microscopy analysis at atomic scale, it has been demonstrated that the forward voltage drop of the device has no variation during the stress due to the intactness of active area. However, the reverse breakdown voltage is gradually increased with the stress time, which results from hot electron injection and trapping into the SiO 2 dielectric at the outer edge of p-type junction termination. Index Terms 4H-SiC, junction barrier Schottky (JBS) diode, parameters shift, repetitive avalanche. I. INTRODUCTION SILICON CARBIDE (SiC) is an excellent material for the power semiconductor device due to its outstanding properties: 1) an order of magnitude higher breakdown electrical field; 2) three times wider bandgap; and 3) three times higher thermal conductivity than the conventional silicon [1] [4]. High-power junction barrier Schottky (JBS) diode based on the SiC material has been widely used in the dc dc converter, the power factor correction, the uninterruptible power supply, the motor control, and so on [5] [11]. For the high power diode, strong reverse avalanche ruggedness is inevitably required [12] [16]. However, even if a rugged device survives the breakdown initially, repeated operation under the reverse avalanche condition may gradually wear out the device. Although the reliability issues of the SiC JBS diode under the forward stress have attracted attention Manuscript received July 25, 2014; revised November 3, 2014 and November 22, 2014; accepted November 24, Date of publication December 9, 2014; date of current version January 20, This work was supported in part by the Distinguished Young Scientists Foundation of Jiangsu Province under Grant BK , in part by the National Natural Science Foundation of China under Grant , in part by Hong Kong, Macao, and Taiwan Science and Technology Cooperation Program of China under Grant 2014DFH10190, in part by the Qing Lan Project through the Chinese Post-Doctoral Foundation under Grant 2012M520053, and in part by the Scientific Research Foundation through the Graduate School, Southeast University, Nanjing, China, under Grant YBPY1403. The review of this paper was arranged by Editor M. Darwish. S. Liu, C. Yang, W. Sun, Q. Qian, and Y. Huang are with the National ASIC System Engineering Research Center, Southeast University, Nanjing , China ( swffrog@seu.edu.cn). X. Wu, M. Wu, Q. Yang, and L. Sun are with the Key Laboratory of MEMS, Ministry of Education, Southeast University, Nanjing , China. Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TED Fig. 1. Schematic of the investigated 4H-SiC JBS diode. recently [17], [18], much less concern has been given to address the reliability of the device under the repetitive reverse avalanche condition. In this paper, the electrical parameters shift for 4H-SiC JBS diode after the repetitive avalanche stress is investigated in detail. The results show that, although the forward voltage drop (V F ) of the JBS diode maintains unchanged, an interesting shift of the reverse breakdown voltage (BV) is observed as the stress time increases. Based on the technical computer-aided design (T-CAD) simulation and high resolution transmission electron microscopy (HRTEM) analysis, the intrinsic mechanisms responsible for the unchanged V F and shifted BV have been discussed. II. DEVICE STRUCTURE AND EXPERIMENT Fig. 1 shows the schematic cross section of the investigated 4H-SiC JBS diode, and the device is designed and fabricated by ourselves. The depth of the n-drift layer is 6 μm, the width of the p + ring is 2 μm, the depth of the p-type junction termination edge (p-jte) is 0.8 μm, the width of the p-jte is 3 μm, and the spacing of the adjacent p + rings and the spacing between the p + ring and the p-jte are both 4.5 μm. In addition, the n-drift layer is low doped with the doping concentration of cm 3 to block the high voltage, and the p-jte is doped with cm 3 to optimize the breakdown performance. The breakdown point is located at the p-jte region. The rated reverse BV and forward operation current of the JBS diode are 600 V and 10 A, respectively. The test setup shown in Fig. 2(a) is used to generate the repetitive dynamic avalanche current pulse for stressing the IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See for more information.

2 602 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 2, FEBRUARY 2015 Fig. 3. Variations of the V F and BV for the investigated JBS device with the increase of the avalanche current pulse number. Fig. 2. (a) Test setup and (b) typical current and voltage waveforms of the DUT during the repetitive avalanche condition. JBS diode. A metal oxide semiconductor (MOS) transistor switch with higher BV than the JBS diode under test (DUT) has been used. The dc voltage source and the inductor L are 100 V and 3.2 mh, respectively. The diode D 0 is necessary for charging the inductor. During the avalanche test, the MOS device is first turned ON and the inductor current is then built up linearly. When the inductor current has reached the predetermined value, the MOS device is turned OFF and the DUT avalanches. Fig. 2(b) shows the typical current and voltage waveforms of the DUT during the repetitive avalanche test, and it can be seen that the avalanche current through the DUT almost decreases linearly. In this paper, the predetermined peak avalanche current is 3 A ( 80% of the maximum rugged avalanche current), and all tests have been performed at room temperature. III. RESULTS AND DISCUSSION Fig. 3 shows the variations of the V F and BV for the JBS device with the increase of the avalanche current pulse number. It can be seen that the BV increases monotonously, which is the same as that in the commercial device of [19], but no obvious shift is observed for the V F. To understand the physical mechanisms of these interesting phenomena, the T-CAD simulation and HRTEM analysis are carried out. The simulated current flowing path of the JBS device under the 3 A avalanche current stress condition has been shown in Fig. 4. It is clear that, for this type of device, the avalanche current flows mainly through the p-jte but not in the central active area of the device, which implies that the damage is located at the device termination. Fig. 4. Current flowing path of the JBS device under the avalanche current stress condition. For the HRTEM analysis, the TEM sample is prepared by the focused ion beam (FIB) using a gallium beam in a dual beam Helios 600i system. The JBS device is overstressed to fail by applying over the maximum rugged avalanche current before FIB cut. Then, the region of interest is cut out by in situ lift-out FIB technique. Low-kilovolt FIB cleaning process has been used to remove the surface amorphous layer. After the TEM sample preparation, HRTEM can be carried out using an image aberration-corrected TEM (FEI Titan ) with an acceleration voltage of 300 kv. The e-beam is carefully spread out to avoid any e-beam-induced structure damage while maintaining the atomistic resolution. Fig. 5(a) shows the TEM photo of the p-jte region of the device, it can be seen that the anode corner metal above the p-jte has obvious burn mark, which is in line with the simulated current flowing path. The result demonstrates once more that the damage point under the repetitive avalanche stress is focused on the termination region. Fig. 5(b) shows the TEM diffraction pattern from the central active area of the device using highenergy e-beam exposure, no any stacking fault can be observed in this region [18], which also supports the above current path simulation well. It is noted that the value of the V F depends on the active area, thereby, the intact active area leads to

3 LIU et al.: REPETITIVE-AVALANCHE-INDUCED ELECTRICAL PARAMETERS SHIFT 603 Fig. 5. (a) TEM photo of p-jte region and (b) TEM diffraction pattern from central active area after applying over maximum rugged avalanche current. Fig. 7. (a) Equipotential distributions of the fresh device. (b) Device with injected electrons at a density level of cm 3 placed along the SiO 2 dielectric surface X = μm. Fig. 6. Perpendicular electrical field and the I.I. generation rate along the surface of SiC material at the device termination when the JBS is biased under the 3 A avalanche current stress condition. the unchanged V F. However, the intrinsic mechanism of the BV shift due to the damage of the device termination near the p-jte should be further analyzed. Fig. 6 shows the perpendicular electrical field and the impact ionization (I.I.) generation rate along the surface of SiC material at the device termination when the JBS is biased under the 3 A avalanche current stress condition. It is clear that the peak perpendicular electrical field and the peak I.I. generation rate are both located at the outer edge of the p-jte (X = 3 μm), and the perpendicular electrical field is positive (the direction is pointing to the cathode of the device), which is in favor of a hot electron injection into the silicon dioxide (SiO 2 ) dielectric. Actually, the quality of the SiO 2 /SiC interface is very poor due to the materials properties, and the dielectric is easy for hot carrier injection and trapping. In that way, the injected electrons will change the electrical field distribution in the p-jte region where the breakdown point of the JBS diode is located. As a result, the BV shift gradually happens. To identify the mechanism, the T-CAD simulations with the injected electrons at a density level of cm 3 placed along the SiO 2 dielectric surface X = μm are performed to study their influences upon the device reliability characteristics. Fig. 7 shows the equipotential distributions of the fresh device and the device with the electrons placement. Comparing with the fresh device, the injected electrons will assist the surface depletion of the n-drift layer and push the equipotential lines away from the p-jte, resulting in the more sparse potential distribution near the sensitive p-jte. Thereby, the lower electrical field is built up in the p-jte region and

4 604 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 2, FEBRUARY 2015 the two stressed devices. It can be seen that both the BV are recovering with the time increasing. This is because the hot electrons trapped into the SiO 2 dielectric layer are gradually released with the time when the stress is removed. Fig. 9 also demonstrates that higher ambient temperature results in faster recovery, which is because the higher temperature provides higher activation energy to help trapped hot electrons release. Consequently, by the T-CAD simulations and all the above experiments, it is concluded that the BV shift of JBS device results from the hot electron injection and trapping into the SiO 2 dielectric at the outer edge of the p-jte. Fig. 8. Simulated reverse BV characteristics for the fresh device and the devices with different trapped electron concentrations. IV. CONCLUSION The electrical parameters shift for the 4H-SiC JBS diode after the repetitive avalanche stress is investigated in this paper. It has been found that, for the device whose breakdown point is located at the p-jte region, the avalanche current flows mainly through the p-jte but not in the central active area of the device. As a result, the forward V F of the device has no any variation due to the intactness of active area. However, the reverse BV is increased during the stress, which we suppose to result from the hot electron injection and trapping into the SiO 2 dielectric at the outer edge of the p-jte. Thereby, in practical application, the dynamic reverse avalanche is positive for the long-term reliability of this kind of 4H-SiC JBS device. REFERENCES Fig. 9. BV variations under different ambient temperatures for the two same stressed devices. larger BV will be achieved comparing with the fresh case. Fig. 8 shows the simulated reverse BV characteristics for the fresh device and the devices with different trapped electron concentrations. It can be seen that the BV of the device will increase for more trapped electrons, which is consistent with the experimental results in Fig. 3. Furthermore, we hope to find more experimental evidences to prove the mechanism of hot electron injection and trapping. The usual direct methods to detect the hot carrier injection need the help of metal electrode that covers the damage region, such as the charge pumping method [20], [21], the dciv method [22], [23], and the CV method [24], [25]. However, to avoid the high peak electrical field crowding at the metal electrode edge, there is not any metal to cover the outer edge of p-type JTE in SiC JBS device, as shown in Fig. 1. As a result, the direct methods are very difficult to verify hot electron injection and trapping into the SiO 2 dielectric at the outer edge of p-type JTE. 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