TMOS E FET. Power Field Effect Transistor MTP8N50E. N Channel Enhancement Mode Silicon Gate
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1 TMOS E FET. Power Field Effect Transistor N Channel Enhancement Mode Silicon Gate MTP8N5E This high voltage MOSFET uses an advanced termination scheme to provide enhanced voltage blocking capability without degrading performance over time. In addition, this advanced TMOS E FET is designed to withstand high energy in the avalanche and commutation modes. This new energy efficient design also offers a drain to source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters, PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Robust High Voltage Termination Avalanche Energy Specified Source to Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode G Diode is Characterized for Use in Bridge Circuits I DSS and V DS(on) Specified at Elevated Temperature D S TMOS POWER FET 8. AMPERES 5 VOLTS R DS(on) =.8 OHM CASE 221A 9, Style 5 TO-22AB MAXIMUM RATINGS ( unless otherwise noted) Rating Symbol Value Unit Drain to Source Voltage V DSS 5 Vdc Drain to Gate Voltage (R GS = 1. M ) V DGR 5 Vdc Gate to Source Voltage Continuous Gate to Source Voltage Non repetitive (tp 1 ms) V GS ±2 V GSM ±4 Vdc Vpk Drain Current T C = 25 C Drain Current T C = 1 C Drain Current Single Pulse (tp 1 s) Total Power T C = 25 C Derate above 25 C I D I D I DM P D Adc Apk Watts W/ C Operating and Storage Temperature Range T J, T stg 55 to 15 C Single Pulse Drain to Source Avalanche Energy STARTING (V DD = 25 Vdc, V GS = 1 Vdc, PEAK I L = 8. Apk, L = 16 mh, R G = 25 ) E AS 51 mj Thermal Resistance Junction to Case Junction to Ambient R JC 1. R JA 62.5 C/W Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 5 sec. T L 26 C Semiconductor Components Industries, LLC, 24 August, 24 Rev. XXX 1 Publication Order Number: MTP8N5E/D
2 MTP8N5E ELECTRICAL CHARACTERISTICS (T C = 25 C unless otherwise noted) Characteristic Symbol Min Typ Max Unit OFF CHARACTERISTICS Drain to Source Breakdown Voltage (V GS = Vdc, I D = 25 µadc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (V DS = 5 Vdc, V GS = Vdc) (V DS = 4 Vdc, V GS = Vdc, T J = 125 C) Gate Body Leakage Current (V GS = ±2 Vdc, V DS = Vdc) ON CHARACTERISTICS (1) Gate Threshold Voltage (V DS = V GS, I D = 25 µadc) Threshold Temperature Coefficient (Negative) Static Drain to Source On Resistance (V GS = 1 Vdc, I D = 4. Adc) Drain to Source On Voltage (V GS = 1 Vdc) (I D = 8. Adc) (I D = 4. Adc, T J = 125 C) Forward Transconductance (V DS = 15 Vdc, I D = 4. Adc) V (BR)DSS 5 I DSS I GSS 1 V GS(th) R DS(on).6.8 V DS(on) g FS 4. DYNAMIC CHARACTERISTICS Input Capacitance C iss pf Output Capacitance (V DS = 25 Vdc, V GS = Vdc, f = 1. MHz) C oss Transfer Capacitance C rss SWITCHING CHARACTERISTICS (2) Turn On Delay Time t d(on) 15 5 ns Rise Time Turn Off Delay Time (R go + C17n = 9.1 ) t r t d(off) 4 15 Fall Time t f 32 6 Gate Charge (see Figure 8) Vdc mv/ C Adc nadc Vdc mv/ C Ohms Vdc mhos Q T 4 64 nc (V DS = 4 Vdc, I D = 8. Adc, Q 1 8. V GS = 1 Vdc) Q 2 17 Q SOURCE DRAIN DIODE CHARACTERISTICS Forward On Voltage V SD Vdc (I S = 8. Adc, V GS = Vdc) (I S = 8. 8Adc, V GS = Vdc, T J = 125 C) 1.1 Reverse Recovery Time t rr 32 ns (I S = 8. Adc, V GS = Vdc, t a 179 di S /dt = 1 A/ s) t b 141 Reverse Recovery Stored Charge Q RR 3. C INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead.25 from package to center of die) L D 4.5 nh Internal Source Inductance (Measured from the source lead.25 from package to source bond pad) L S 7.5 (1) Pulse Test: Pulse Width 3 s, Duty Cycle 2.%. (2) Switching characteristics are independent of operating junction temperature. 2
3 MTP8N5E TYPICAL ELECTRICAL CHARACTERISTICS ID, DRAIN CURRENT (AMPS) V V GS = 1 V 7 V 6 V 5 V ID, DRAIN CURRENT (AMPS) V DS 1 V 1 C 25 C T J = 55 C V DS, DRAIN TO SOURCE VOLTAGE (VOLTS) V GS, GATE TO SOURCE VOLTAGE (VOLTS) Figure 1. On Region Characteristics Figure 2. Transfer Characteristics R DS(on), DRAIN TO SOURCE RESISTANCE (OHMS) RDS(on), DRAIN TO SOURCE RESISTANCE (NORMALIZED) V GS = 1 V I D, DRAIN CURRENT (AMPS) I D, DRAIN CURRENT (AMPS) Figure 3. On Resistance versus Drain Current and Temperature V GS = 1 V I D = 8 A 25 T J = 1 C T J, JUNCTION TEMPERATURE ( C) 25 C 55 C I DSS, LEAKAGE (na) R DS(on), DRAIN TO SOURCE RESISTANCE (OHMS) , 1, 1, 1 1 V GS = 1 V 15 V Figure 4. On Resistance versus Drain Current and Gate Voltage V GS = V T J = 125 C 1 C 25 C V DS, DRAIN TO SOURCE VOLTAGE (VOLTS) Figure 5. On Resistance Variation with Temperature Figure 6. Drain to Source Leakage Current versus Voltage 3
4 MTP8N5E TYPICAL ELECTRICAL CHARACTERISTICS 4 V DS = V V GS = V 1, V GS = V C, CAPACITANCE (pf) C iss C rss C oss C iss C, CAPACITANCE (pf) 1, 1 C iss C oss C rss 1 5. C rss 5. V GS V DS DRAIN TO SOURCE VOLTAGE (VOLTS) GATE TO SOURCE OR DRAIN TO SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation Figure 8. High Voltage Capacitance Variation, GATE TO SOURCE VOLTAGE (VOLTS) GS V Q1 Q3 8. Q2 16 QT Q g, TOTAL GATE CHARGE (nc) Figure 9. Gate to Source and Drain to Source Voltage versus Total Charge 24 V GS V DS I D = 8 A V DS, DRAIN TO SOURCE VOLTAGE (VOLTS) t, TIME (ns) 1 1 I D = 8 A V DD = 25 V V GS = 1 V t d(off) t r t f 1 t d(on) R G, GATE RESISTANCE (OHMS) Figure 1. Resistive Switching Time Variation versus Gate Resistance IS, SOURCE CURRENT (AMPS) V GS = V I D, DRAIN CURRENT (AMPS) V GS = 2 V SINGLE PULSE T C = 25 C R DS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 s 1 s 1 ms 1 ms dc V SD, SOURCE TO DRAIN VOLTAGE (VOLTS) V DS, DRAIN TO SOURCE VOLTAGE (VOLTS) Figure 11. Diode Forward Voltage versus Current Figure 12. Maximum Rated Forward Biased Safe Operating Area 4
5 MTP8N5E, SINGLE PULSE DRAIN TO SOURCE AS AVALANCHE ENERGY (mj) I D = 8 A E T J, STARTING JUNCTION TEMPERATURE ( C) 15 Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1..1 D = SINGLE PULSE t, TIME (seconds) Figure 14. Thermal Response 5
6 MTP8N5E PACKAGE DIMENSIONS CASE 221A 9 ISSUE AA H Q Z L V G B N D A K F T U S R J C T SEATING PLANE STYLE 5: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. INCHES MILLIMETERS DIM MIN MAX MIN MAX A B C D F G H J K L N Q R S T U V Z
7 MTP8N5E Notes 7
8 MTP8N5E E FET and TMOS are trademarks of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION NORTH AMERICA Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 8217 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada ONlit@hibbertco.com Fax Response Line: or Toll Free USA/Canada N. American Technical Support: Toll Free USA/Canada EUROPE: LDC for ON Semiconductor European Support German Phone: (+1) (Mon Fri 2:3pm to 7:pm CET) ONlit german@hibbertco.com French Phone: (+1) (Mon Fri 2:pm to 7:pm CET) ONlit french@hibbertco.com English Phone: (+1) (Mon Fri 12:pm to 5:pm GMT) ONlit@hibbertco.com EUROPEAN TOLL FREE ACCESS*: *Available from Germany, France, Italy, UK, Ireland CENTRAL/SOUTH AMERICA: Spanish Phone: (Mon Fri 8:am to 5:pm MST) ONlit spanish@hibbertco.com Toll Free from Mexico: Dial for Access then Dial ASIA/PACIFIC: LDC for ON Semiconductor Asia Support Phone: (Tue Fri 9:am to 1:pm, Hong Kong Time) Toll Free from Hong Kong & Singapore: ONlit asia@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center Nishi Gotanda, Shinagawa ku, Tokyo, Japan Phone: r14525@onsemi.com ON Semiconductor Website: For additional information, please contact your local Sales Representative. 8 MTP8N5E/D
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MTW3NE Power MOSFET 3 Amps, Volts NChannel TO47 This advanced Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a draintosource
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Small Signal MOSFET V, 8 ma, Single, N Channel, Gate ESD Protection, SC 75 Features Low Gate Charge for Fast Switching Small.6 x.6 mm Footprint ESD Protected Gate AEC Q Qualified and PPAP Capable NVA4N
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NTGST Power MOSFET, Volts PChannel TSOP Features Ultra Low R DS(on) Higher Efficiency Extending Battery Life Miniature TSOP Surface Mount Package PbFree Package is Available Applications Power Management
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NTRP, NVTRP Power MOSFET V,.9 A, Single, P Channel, SOT Features Leading Planar Technology for Low Gate Charge / Fast Switching Low R DS(ON) for Low Conduction Losses SOT Surface Mount for Small Footprint
More informationDesigner s Data Sheet TMOS E FET. High Energy Power FET
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Preferred Device Power MOSFET 3 Amps, 5 Volts NChannel TO64 This high voltage MOSFET uses an advanced termination scheme to provide enhanced voltageblocking capability without degrading performance over
More informationDistributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. Preferred Device Small Signal MOSFET 500 ma, 60 Volts N Channel Features
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NTB6P, NTBV6 Power OSFET -6 V, -8. A P Channel, D PAK Features Designed for Low R DS(on) Withstands High Energy in Avalanche and Commutation odes AEC Q Qualified NTBV6 These Devices are Pb Free and are
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NDDN3U N-Channel Power MOSFET V, 3 m Features % Avalanche Tested These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS Compliant ABSOLUTE MAXIMUM RATINGS ( unless otherwise noted) V (BR)DSS R DS(ON)
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Dual Volt P-Channel PowerTrench MOSFET General Description This P-Channel MOSFET has been designed specifically to improve the overall efficiency of DC/DC converters using either synchronous or conventional
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The MJE/MJF18204 have an application specific state of the art die dedicated to the electronic ballast ( light ballast ) and power supply applications. Improved Global Efficiency Due to Low Base Drive
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NTA7N, NVTA7N Small Signal MOSFET V, 4 ma, Single, N Channel, Gate ESD Protection, SC 7 Features Low Gate Charge for Fast Switching Small.6 x.6 mm Footprint ESD Protected Gate NV Prefix for Automotive
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NTMFDCN Dual N-Channel Power MOSFET 3 V, High Side A / Low Side 7 A, Dual N Channel SOFL Features Co Packaged Power Stage Solution to Minimize Board Space Minimized Parasitic Inductances Optimized Devices
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MTP36N6V Preferred Device Power MOSFET 3 Amps, 6 Volts NChannel TO This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching
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MTPN6E Preferred Device Power MOSFET Amp, 6 Volts NChannel TO This high voltage MOSFET uses an advanced termination scheme to provide enhanced voltageblocking capability without degrading performance over
More informationNTK3139P. Power MOSFET. 20 V, 780 ma, Single P Channel with ESD Protection, SOT 723
NTK9P Power MOSFET V, 78 ma, Single P Channel with ESD Protection, SOT 7 Features P channel Switch with Low R DS(on) % Smaller Footprint and 8% Thinner than SC 89 Low Threshold Levels Allowing.5 V R DS(on)
More information500 mw SOD 123 Surface Mount
500 mw SOD 123 Surface Mount Three complete series of Zener diodes are offered in the convenient, surface mount plastic SOD 123 package. These devices provide a convenient alternative to the leadless 34
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MTWNE Preferred Device Power MOSFET Amps, Volts NChannel TO7 This high voltage MOSFET uses an advanced termination scheme to provide enhanced voltageblocking capability without degrading performance over
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More informationPUBLICATION ORDERING INFORMATION. Semiconductor Components Industries, LLC
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