Computing of the Future

Transcription

1 -Overview- S. J. Ben Yoo, Venkatesh Akella, Keren Bergman, Horst Simon

2 What would Computing be like 20 years from Now? (1) brainstorm on future computing with extremely low power & high-performance with novel interconnects, (2) promote government agencies to form new programs in this area, (3) promote industry-academia-government/national lab collaborations. 2

3 Today s Data Centers and Super Computers MegaWatts of Power 100 s of racks 3

4 $ for Power and Cooling in Data Centers 4 Courtesy: IBM research

5 Moore s Law : density not performance Ref. Cramming more components onto integrated circuits by Gordon Moore, Electronics, Vol. 38. April 19,

6 Processor Performance 6

7 Ideal vs. Actual Scaling Courtesy: IBM research 7

8 Power Cliff and Opportunities Courtesy: IBM research 8

9 Super Computing (e.g. IBM BlueGene) Courtesy of Alan Benner, IBM System Implications of Optical I/O Courtesy: IBM research 9

10 The Rise of Chip Multiprocessors (CMPs) Emerging trend replicate computational logic: maintain processing throughput while lowering clock frequencies and supply voltages. Parallel architectures: better processing performance per watt Power The GHz race is grinding to a halt P dyn V dd2 fp leak V dd exp(-qv t /(kt)) V dd 2 cores at and 2 ~4x reduction in dynamic power equal performance As number of cores grows, key is to performance: scalable, fast, and power-efficient: interconnection networks f 2 (10)

11 Balancing Computing and Communications Amdahl s rule match computation and communications for best operation match memory capacity and memory I/O bandwidth for best operation Currently, growing gap between actual computer performance and the theoretical maximum performance rating. Current trends in decreasing Bytes/FLOP 10 TeraFLOPS chip will need 10 TB/sec or ~100 Tb/s communications!! (US wide Internet traffic is ~3 Tb/s today) Electronic communications on-chip will no longer keep up with the demand and power efficiency requirement 11

12 Balancing Bandwidth and FLOPS Figure: Courtesy Robert Drost, Stanford IFC Meeting, Dec 2006 Our Design Space 1 byte per flop 12

13 Balancing Bandwidth vs Memory Capacity PicoBlade Design Space 1 byte per flop Figure: Courtesy Robert Drost, Stanford IFC Meeting, Dec

14 Acknowledgement: Energy Efficient Large-Scale Computing with Nanophotonic Interconnects Venkatesh Akella (UCDavis), Raj Amirtharajah (UCDavis), Bevan Baas (UCDavis), Keren Bergman (Columbia), Van Carey (UC Berkeley), Shanhui Fan (Stanford), Soheil Ghiasi (UC Davis), James Harris (Stanford), Saif Islam (UC Davis), Michal Lipson (Cornell), Kai Liu (UCDavis), David Miller (Stanford), James Shackelford (UC Davis), S. J. Ben Yoo (UC Davis), and many others UCDavis, Stanford, UCBerkeley, Cornell, Columbia Univ. 14

15 Issues-Future Computing Systems Performance/power ratio is a real issue Memory I/O bottleneck, Power bottleneck Optics and Electronics can help each other Optics is especially good at interconnecting in parallel without impedance, crosstalk, and timingjitter concerns Parallel processing is good, but software, virtualization, and resource management must work. We need a systematic approach 15

16 Proposed Center Thrusts Thrust 1: Future Computing System Architecture Thrust 2: Resource Management and Virtualization Thrust 3: Optical Interconnect and Nanotechnologies Thrust 4: Systems Integration Thrust 5: Testbed and Application Studies 16

17 Optical link power consumption with Nanophotonics Bit rate 10Gbps 10 optical channels Modulator capacitance 1 ff Receiver circuit power consumption 1 mw Total Input optical power P in = 1 mw Waveguide loss α wg ~1.6 db/cm Power consumption per channel: Power efficiency (mw/gbps) P total = (P tr,elec + P tr,opt ) + P wg + (P rec,opt + P rec,elec ) Electrical link Optical link 2.3 mw/gbps 30 μw/gbps Bit Rate (Gbps) Transmitter Waveguide Receiver = ( ) (0.05+1) ª 1.18 mw Electrical Link data ref: Poulton, Dally, Horowitz et al, IEEE J SSC Power efficiency = 118 μw/gbps (fj/bit)

18 Microresonator-based Optical Interconnected Networks (simplified perspective) λ 3 λ 2 λ 1 λ 1 λ 1 Bus waveguide λ 1 λ 1 λ 1 λ 4 λ 1 Modulator Tunable Filter P D λ 1 λ 1 λ 1 Off-chip light source 18 Wavelength Conversion? O/O/O or O/E/O => Size and Power and b-rate Optical Regen? 2R/3R? => Optically Clocked Receivers/Regens Optical-Label/Header? => Electrical signaling effective in short distance Optical Buffers? => Size and Power and b-rate

19 3-D nanophotonic-electronic multi-core architectures Optical coherent ring + modulators+ offchip Laser+ detectors Memory CPU array + caches HEAT SINK Optical Interconnect + modulators+ offchip Laser+ detectors Flash Disk CPU array + caches Memory CPU array + caches HEAT SINK Optical coherent ring + modulators+ offchip Laser+ detectors Memory CPU array + caches HEAT SINK 19

20 Electro-Optical Codesign Issues Electrical interface circuits for micro-resonator based optical interconnects 20 Explore pre-emphasis to improve ring switching speed Challenge is to minimize power consumption Optical power vs. electrical power tradeoffs Ex: driving photodiodes rail-to-rail eliminates TIA, shown useful for optical clock Φ 1-N distribution (Miller ISSCC05) Integrating receiver also eliminates TIA (Palermo ISCC07) Must be simplified further to reduce power consumption Courtesy Brongersma, Fan, Miller MURI Stanford

21 Si Wire Ring Resonator for low-power switching/routing Low drive power optical modulators Photonic wire Return bend ±2dB loss E1 Y1 Y2 Y1 a b E1 = Y2 c d E 2 Racetrack resonator 10μm E2 R. Baets et. al., LEOS Annual Meeting Prof. Lipson s Group: Si Nano PICs with V switching

22 22 Plasmonic Devices Best of both worlds? (optics and electronics) 0.5 n eff = E x Field ε = 1 ε = 1 ε = ε = ε = ε = 1 ε = nm

23 Massively-Parallel Nanowire Interconnection 1.E-10 1.E-11 Low Noise Contacts Hooge parameter 10-3 A/R 1.E-12 1.E-13 Nanotube Si Nanowire Carbon Nanotube 1.E-14 1.E-15 Nano-bridge Courtesy of M. Saif Islam UCDavis, HP 1.E-16 Reza, Bosman, Islam, Kamins, Sharma and Williams, Submitted to IEEE Trans. Nanotechnology, 2005 Good Ohmic Contacts Not labor intensive or costly Mass-manufacturable 23

24 Deliverables for Workshop Computing of the Future (1) brainstorm on future computing with extremely low power & high-performance with novel interconnects, (2) promote government agencies to form new programs in this area, (3) promote industry-academia-government/national lab collaborations. Write a Report Plan our 24

25 Today s Morning Agenda Day: Friday, February 29 7:30 am Breakfast 8:15 am Registration 9:00 am Workshop Introduction, Overview, and Goals S. J. Ben Yoo, UC Davis 9:30 am Results from the Zettaflops Workshop 2007 Erik P. DeBenedictis, Sandia National Labs 10:00 am Tera-scale Computing - motivation and challenges Jerry Bautista, Intel 10:30 am Break 11:00 am Hardware Design Constraints for Power Efficient Scientific Computing John Shalf, LBL 11:30 am The Future Evolution of High-Performance Microprocessors Rob Schreiber, HP Labs 12:00 Noon Optical Interconnects to Chips David A. B. Miller, Stanford 25

26 Today s Afternoon Agenda Day: Friday, February 29 12:30 pm Lunch 1:30 pm Nano-Photonic Interconnection Networks for Chip-Multiprocessor Computing Systems Keren Bergman, Columbia Univ. 2:00 pm IntraChip Optical Networks for a Future Supercomputer-on-a-Chip Jeffrey Kash, IBM Research 2:30 pm Nanoscale waveguides, metallic slots, and switches Shanhui Fan, Stanford Univ. 2:45 pm Nanowires: Massively Parallel Interconnects Saif Islam, UC Davis 3:00 pm NSA s Center for Excellence in Computing and ACS Programs David Bisant, Department of Defense Lance Joneckis, Institute of Defence Analysis 3:20 pm Break 3:50 pm Discussions: Moderated by S. J. Ben Yoo, UC Davis 5:30 pm Social 6:00 pm ~8:00 pm Dinner Banquet 26

27 27 Tomorrow s Lab Tour Agenda Day: Saturday, March 1, :00 am Depart Crowne Plaza SFO 9:30 am Arrive at UC Davis Campus 9:40 am Northern California Nanotechnology Center Tour Frank Yaghmaie, UC Davis 10:00 am 167-core ASAP II chip demo Bevan Baas, UC Davis 10:20 am Nano-wire device demo Saif Islam, UCDavis 10:35 am Photonic Integrated System-on-a-Chip tour S. J. Ben Yoo, UCDavis 10:50 am Spintronic Devices tour Kai Liu, UCDavis 11:05 am Depart Davis for Stanford 12:40 pm Lunch at Stanford 1:20 pm Photonic Interconnects and Plasmonics David A. B. Miller (or Staff), Stanford 2:20 pm Depart Stanford for Crowne Plaza Hotel, SFO 2:50 pm Crowne Plaza Hotel, SFO Arrival