CMOS Implementation of Voltage Controlled Oscillator

Transcription

1 CMOS Implementation of Voltage Controlled Oscillator A PROJECT REPORT Submitted by Syeda Masrura Nazerin Rajeswari Mitra Moumita Pal Somedutta Ghosh Soumavo Karmakar in partial fulfillment for the award of the degree of B.TECH IN Electronics & Communication Engineering UNDER THE GUIDANCE OF Mr. Subir Maity Department of Electronics & Communication Engineering INSTITUTE OF SCIENCE & TECHNOLOGY

2 ABSTRACT In this project, we have designed a Voltage Controlled Oscillator which is implemented with the help of CMOS. The CMOS used here has a channel length of about 0.18µm and the whole simulation is done in T-SPICE. The main part of the Voltage Controlled Oscillator is the ring oscillator. This ring oscillator consists of an odd number of invertors which increases the delay and decreases the frequency. The differential amplifier is used in this project for noise immunity since the double ended configuration removes the common mode noise. The voltage control circuit is a cascade current mirror circuit. The full circuit is then simulated using T-Spice and the output waveform is plotted which shows the effect of voltage on the frequency. The results obtained are slow frequency value of f7.5486e+007 and fast frequency value of e

3 Contents 1. Introduction Block Diagram Working principle of VCO Applications 5 2. Complementary metal oxide semiconductor(cmos) Technical details Compositions Inversion Logic Principle of Oscillation Ring Oscillator Properties of ring oscillator Output frequency Differential amplifier Single ended and differential operation Basic differential bar Qualitative analysis Differential configuration of Ring Oscillator Types of VCOs Harmonic oscillators Relaxation oscillators Harmonic oscillator VCOs VCO Topologies Parallel Tuned Colpitts VCO Series Tuned Colpitts VCO (Clapp VCO) Wideband Colpitts VCO Hartley VCO Wideband Differential Push-Push VCO

4 8.4 Differential Cross-Coupled VCO Negative Resistance VCO Franklin VCO Cascode VCO Vackar VCO Voltage Controlled Mechanism Design Description Differential amplifier Ring Oscillator Control Circuit Voltage controlled Oscillator Program Simulation results Result Waveform Measurement result summary Conclusion Advantages Disadvantages Uses...37 References...38 List of figures

5 Chapter 1 Introduction A voltage controlled oscillator (VCO) is an electrical circuit that produces an oscillatory output voltage. A voltage-controlled oscillator (VCO) provides a periodic signal where the frequency of the periodic signal is related to the level of an input voltage control signal supplied to the VCO. A voltage controlled oscillator is simply an oscillator having a frequency output that is proportional to an applied voltage. Oscillators frequently consist of one or two transistors, an inductor (L), and a capacitor (C) in an LC tank circuit, followed by a buffering amplifier. An oscillator circuit may be implemented with a tuned amplifier having positive feedback from the amplifier's output terminal to its input terminal, which design takes advantage of the instability possible in circuits having such a feedback loop. 1.1 Block Diagram The block diagram of a voltage controlled oscillator is shown below:- 1.2 Working principle of a VCO Fig. 1.1 Block diagram of VCO An oscillator circuit may act as an active device, such as a transistor, to produce power gain; or may be used in feedback network, routing a sufficient amount of the active device's output signal to an input of the active device, to sustain oscillations. A voltage-controlled oscillator (VCO) forms a periodic output signal where a frequency of the periodic output signal is related to the level of an input control voltage. The center frequency of a VCO is 9

6 the frequency of the periodic output signal formed by the VCO when the input control voltage is set to a nominal level. The voltage-controlled oscillator has a characteristic gain, which often is expressed as a ratio of the VCO output frequency to the VCO input voltage. VCOs typically utilize a variable control voltage input to produce a frequency output. The control voltage input typically may be tuned so that the VCO produces a desired, operational frequency output. The input control voltage is then adjusted up or down to control the frequency of the periodic output signal. A voltage controlled oscillator is capable of varying an oscillating frequency in response to a change in control voltages. A VCO typically employs one or more variable capacitors (varactors) to allow for adjustment of the frequency of oscillation for the VCO. The tuning range of the VCO refers to the range of oscillation frequencies achieved by varying the varactors. To reduce the tuning range requirement, a VCO may employ a programmable capacitor bank to aid with the adjustment of the oscillation frequency. The capacitor bank contains a bank of tuning capacitors that may be individually switched on or off. Each tuning capacitor reduces the oscillation frequency when switched on. 1.3 Applications Narrow band VCO's generally have better phase noise than wide band VCO's. Application wise, wide tuning VCO are recommended for electronic counter measures such as radar, surveillance, etc., and narrow band VCO's are used in phase lock applications in receiver and transmitter systems. 10

7 Chapter 2 Complementary metal oxide semiconductor (CMOS) Complementary metal oxide semiconductor (CMOS) is a technology for constructing integrated circuits. CMOS technology is used in microprocessors, microcontrollers, static RAM, and other digital logic circuits. CMOS technology is also used for several analog circuits such as image sensors, data converters, and highly integrated transceivers for many types of communication. CMOS is also sometimes referred to as complementary-symmetry metal oxide semiconductor. The words "complementarysymmetry" refer to the fact that the typical digital design style with CMOS uses complementary and symmetrical pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) for logic functions. Two important characteristics of CMOS devices are high noise immunity and low static power consumption. Significant power is only drawn when the transistors in the CMOS device are switching between on and off states. Consequently, CMOS devices do not produce as much waste heat as other forms of logic, for example transistor-transistor logic (TTL) or NMOS logic. CMOS also allows a high density of logic functions on a chip. It was primarily for this reason that CMOS became the most used technology to be implemented in VLSI chips. The phrase "metal oxide semiconductor" is a reference to the physical structure of certain field-effect transistors, having a metal gate electrode placed on top of an oxide insulator, which in turn is on top of a semiconductor material. 2.1 Technical details "CMOS" refers to both a particular style of digital circuitry design, and the family of processes used to implement that circuitry on integrated circuits (chips). CMOS circuitry dissipates less power than logic families with resistive loads. Since this advantage has increased and grown more important, CMOS processes and variants have come to dominate. CMOS circuits use a combination of p-type and n- type metal oxide semiconductor field-effect transistors (MOSFETs) to implement logic gates and other digital circuits found in computers, telecommunications equipment, and signal processing equipment. 2.2 Composition The main principle behind CMOS circuits that allows them to implement logic gates is the use of p-type and n-type metal oxide semiconductor field-effect transistors to create paths to the output from either the voltage source or ground. When a path to output is created from the voltage source, the circuit is said to be pulled up. The other circuit state occurs when a path to output is created from ground and the output pulled down to the ground potential. 2.3 Inversion Fig. 2.1 Static CMOS Inverter 11

8 CMOS circuits are constructed in such a way that all PMOS transistors must have either an input from the voltage source or from another PMOS transistor. Similarly, all NMOS transistors must have either an input from ground or from another NMOS transistor. The composition of a PMOS transistor creates low resistance between its source and drain contacts when a low gate voltage is applied and high resistance when a high gate voltage is applied. On the other hand, the composition of an NMOS transistor creates high resistance between source and drain when a low gate voltage is applied and low resistance when a high gate voltage is applied. CMOS accomplishes current reduction by complementing every nmosfet with a pmosfet and connecting both gates and both drains together. A high voltage on the gates will cause the nmosfet to conduct and the pmosfet not to conduct while a low voltage on the gates causes the reverse. This arrangement greatly reduces power consumption and heat generation. However, during the switching time both MOSFETs conduct briefly as the voltage goes from one state to another. This induces a brief spike in power consumption and becomes a serious issue at high frequencies. The image on the right shows what happens when an input is connected to both a PMOS transistor (top of diagram) and an NMOS transistor (bottom of diagram). When the voltage of input A is low, the NMOS transistor's channel is in a high resistance state. This limits the current that can flow from Q to ground. The PMOS transistor's channel is in a low resistance state and much more current can flow from the supply to the output. Because the resistance between the supply voltage and Q is low, the voltage drop between the supply voltage and Q due to a current drawn from Q is small. The output therefore registers a high voltage. On the other hand, when the voltage of input A is high, the PMOS transistor is in an OFF (high resistance) state so it would limit the current flowing from the positive supply to the output, while the NMOS transistor is in an ON (low resistance) state, allowing the output to drain to ground. Because the resistance between Q and ground is low, the voltage drop due to a current drawn into Q placing Q above ground is small. This low drop results in the output registering a low voltage. In short, the outputs of the PMOS and NMOS transistors are complementary such that when the input is low, the output is high, and when the input is high, the output is low. Because of this behavior of input and output, the CMOS circuits' output is the inversion of the input. 2.4 Logic: Fig. 2.2 NAND gate in CMOS logic More complex logic functions such as those involving AND and OR gates require manipulating the paths between gates to represent the logic. When a path consists of two transistors in series, both transistors must have low resistance to the corresponding supply voltage, modeling an AND. When a path consists of two transistors in parallel, either one or both of the transistors must have low resistance to connect the supply voltage to the output, modeling an OR. Shown on the right is a circuit diagram of a NAND gate in CMOS logic. If both of the A and B inputs are high, then both the NMOS transistors (bottom half of the diagram) will conduct, neither of the PMOS 12

9 transistors (top half) will conduct, and a conductive path will be established between the output and V ss (ground), bringing the output low. If either of the A or B inputs is low, one of the NMOS transistors will not conduct, one of the PMOS transistors will, and a conductive path will be established between the output and V dd (voltage source), bringing the output high. An advantage of CMOS over NMOS is that both low-to-high and high-to-low output transitions are fast since the pull-up transistors have low resistance when switched on, unlike the load resistors in NMOS logic. In addition, the output signal swings the full voltage between the low and high rails. This strong, more nearly symmetric response also makes CMOS more resistant to noise. 13

10 Chapter 3 Principle of Oscillation The block diagram of a sinusoidal oscillator of an amplifier with gain A(ω) and a frequency selective network or feedback network with gain B(ω) connected in a positive feedback loop is shown below. We conclude an input signal V in to understand the principle of oscillation although no input signal is applied in an actual oscillator circuit. V in V I =V in + V f V out =AV I V f =B V out Fig. 3.1 Block diagram of a sinusoidal oscillator Let initially S1 is closed and S2 is open i.e. V f = 0. thus, V I = V in and V out / V I = A(ω) and V f / V out = B(ω) So V f = B(ω) V out = B(ω) A(ω) V I (i) V f / V I = B(ω) A(ω) = open loop gain.(ii) Here both A(ω) and B(ω) are functions of frequency. If for a particular frequency, ω = ω o, we have B(ω o )A(ω o ) = 1 and from eq. (i), we get V f = V I = V in (iii) Now let S1 is open and S2 is closed to close the loop, so since V f = V I at ω = ω o, the feedback signal will be in phase with the input signal and have the same magnitude. Hence the system will sustain oscillations at the particular frequency ω o (=2πf o ), even if V in is withdrawn. The gain of the feedback amplifier is given by 14

11 A f = A(ω) / (1-A(ω)B(ω)..(iv) At a specific frequency ω o, if the loop gain A(ω o )B(ω o ) is unity, then from above eq. A f will be infinity i.e. the circuit will have a finite output for zero input signal thus the amplifier circuit with feedback will work as an oscillator. Since both A and B are complex quantities they give two alternative sets of conditions. A(ω)B(ω) = 1 and A(ω)B(ω) = 0 The first condition dictates that the signal fed back to the input should be of the same magnitude as the input signal, while the second condition dictates that the feedback should be positive with zero or 360 o phase shift. Thus at wo the phase of the loop gain should be either zero or 360 o and the magnitude of the loop gain should be unity. This is known as Barkhaunsen criterion. It the first condition is satisfied, but not the second then oscillations will die out because the input signal will gradually decay due to phase cancellations of the signals fed back to the input after successive trips round the loop. The second condition determines the frequency of oscillation while the first condition provides the condition of sustained oscillation. A practical oscillator doesn t require an input signal. The random movement of electrons in conductors and resistors, random emissions of carriers in a transistor and diode, random electron-hole recombination phenomenon produce random fluctuations of voltage of very small magnitude called electrical noise. Noise has broad spectrum consisting of all frequencies. The noise voltage at w=wo is the starting or triggering signal from which oscillation grows, viz.,net phase shift is zero. For starting of oscillations in fact AB should be slightly greater than unity. But in steady state AB = 1 and AB = 0. 15

12 Chapter 4 Ring Oscillator A ring oscillator is a device composed of an odd number of NOT gates whose output oscillates between two voltage levels, representing true and false. The NOT gates, or inverters, are attached in a chain; the output of the last inverter is fed back into the first. A ring oscillator consists of a number of gain stages in a loop. Because a single inverter computes the logical NOT of its input, it can be shown that the last output of a chain of an odd number of inverters is the logical NOT of the first input. This final output is asserted a finite amount of time after the first input is asserted; the feedback of this last output to the input causes oscillation. A circular chain composed of an even number of inverters cannot be used as a ring oscillator; the last output in this case is the same as the input. The open-loop circuit contains only one pole, thereby providing a maximum frequency-dependent phase shift of 90. Since the common-source stage exhibits a dc phase shift of 180 due to the signal inversion from the gate to the drain, the maximum total phase shift is 270. The loop therefore fails to sustain oscillation growth.so the above example suggests that oscillation may occur if the circuit contains multiple stages and hence multiple poles. When two significant poles appear in the signal path, allowing the frequency-dependent phase shift to approach 180. Unfortunately, this circuit exhibits positive feedback near zero frequency due to the signal inversion through each common-source stage.as a result, it simply latches up rather than oscillates. 4.1 Properties of ring oscillator 1. Oscillation may occur if the circuit contains multiple stages and hence multiple poles. 2. The total number of inversion in the loop must be odd, so that the circuit does not latch up. 3. The number of stages in ring oscillators is determined by various requirements, including speed, power dissipation, noise immunity etc. 4. Three to five stages provide optimum performance. 5. The ring oscillator is a member of the class of time delay oscillators. 6. The ring oscillator is a distributed version of the delay oscillator 7. The ring oscillator uses an odd number of inverter to give the effect of a single inverting amplifier with a gain of greater than one. 8. Adding pairs of inverters to the ring increases the total delay and thereby decreases the oscillator frequency. 9. Changing the supply voltage changes the delay through each inverter, with higher voltages typically decreasing the delay and increasing the oscillator frequency. 16

13 Fig. 4.1 Circuit diagram of ring oscillator Fig. 4.2 Output waveform: 4.2 Output frequency The most common way to derive an equation for the oscillation frequency of an N-stage ring oscillator is to assume each stage provide a delay of t d. The signal must go through each of the N delay stage twice to provide one period of oscillation, due to rising and falling edges of each delay stage. Therefore, the period is 2.Nt d. So the oscillating frequency isf = 1/2Nt d Adjusting the delay of each ring cell according to the control signal can tune the frequency of this ring oscillator when used in PLL. 17

14 Chapter 5 Differential amplifier 5.1 Single ended and differential operatio: A single ended signal is defines as one that is measures with respect to a fixed potential, usually the ground. A differential signal is defined as one that is measured between two nodes that have equal and opposite signal excursions around a fixed potential. In the strict sense, the two nodes must also exhibit equal impedance to that potential. Fig. 5.1 illustrates the two types of signals conceptually. The center potential in differential signaling is called the common-mode level. Fig. 5.1(a) Single ended operation Fig. 5.1(b) Differential operation An important advantage of differential operation over single-ended signaling is higher immunity to environmental noise. Consider the example depicted in Fig. 5.1(a), where two adjacent lines in a circuit carry a small, sensitive signal and a large clock waveform. Due to capacitive coupling between the lines, transitions on line L 2 corrupt the signal on line L 1. Now suppose, as shown in Fig. 5.1(b), the sensitive signal is distributed as two equal and opposite phases. If the clock is placed midway between the two, the transitions disturb the differential phases equally, leaving the difference intact. Since the common-mode level of the two phases is distributed but the differential output is not corrupted, we say this arrangement rejects the common-mode noise. Fig. 5.2(a) Single ended operation Fig. 5.2(b) Differential operation 5.2 Basic differential bar To amplify a differential signal we may incorporate two identical single-ended signal paths to process the two phases. 18

15 a Fig. 5.3 Differential amplifier Fig. 5.4 Effect of different CM level Such a circuit indeed offers some advantages of differential signaling: high rejection of supply noise, higher output swings, etc. But what happens if V in1 and V in2 experience a large common-mode disturbance or simply do not have a well defined common-mode dc level? As the input CM level, V in,cm, changes, so do the currents in M 1 and M 2, thus varying both the transconductance of the devices and the output CM level. The variation of the transconductance in turn leads to a change in the small signal gain while the departure of the output CM level from its ideal value lowers the maximum allowable output swings. For example, as shown in Fig. 5.4, if the input CM level is excessively low, the minimum values of V in1 and V in2 may infact turn off M 1 and M 2, leading to severe clipping at the output. It is important that the bias currents of the devices have minimal dependence on the input CM level. Fig 5.5 Differential pair A simple modification can resolve the above issue. The differential pair employs a current source I SS to make I D1 + I D2 independent of V in,cm. Thus, if V in1 = Vi n2, the bias current of each transistor equals 19

16 I SS /2 and the output common-mode level is V DD - R D I SS /2. it is instructive to study the large signal behavior of the circuit for both differential and common-mode input variations. 5.3 Qualitative analysis Let us assume that in fig 4 V in1 - V in2 varies from to +. If V in1 is much more negative than V in2, M 1 is off, M 2 is on and I D2 = I SS. Thus, V out1 = V DD and V out2 = V DD - R D I SS. As V in1 is brought closer to Vin2, M 1 gradually turns on, drawing a fraction of I SS from RD1 and hence lowering V out1. Since I D1 + I D2 = I SS, the drain current of M 2 decreases and V out2 rises. As shown in Fig 5.6, for V in1 = V in2, we have V out1 = V out2 = V DD R D I SS /2. as V in1 becomes more positive than V in2, M 1 carries a greater current than does M 2 and V out1 drops below V out2. for sufficiently large V in1 V in2, M 1 hogs all of I SS, turning off M 2. as a result, V out1 = V DD R DD I SS and V out2 = V DD Fig 5.6 V out1 -V out2 versus V in1 -V in2. 20

17 Chapter 6 Differential configuration of Ring Oscillator In ring oscillator differential amplifier is used to increase its noise immunity. As a noise problem is faced due to its stages. Though noise immunity of ring VCO is much higher than its single stage. Still differential amplifier is used as noise immunity is a main concern for designers. Moreover, an advantage of complimentary output is available for this differential amplifier. Here is a circuit of the differential amplifier. Fig. 6.1 Ring oscillator differential amplifier Now let s take a look how the circuit is used in the ring oscillator. This circuit is used in the ring oscillator. Fig. 6.2 MOS representation of differential amplifier 21

18 Chapter 7 Types of VCOs VCOs can be generally categorized into two groups based on the type of waveform produced: 1) harmonic oscillators, and 2) relaxation oscillators. 7.1 Harmonic oscillators generate a sinusoidal waveform. They consist of an amplifier that provides adequate gain and a resonant circuit that feeds back signal to the input. Oscillation occurs at the resonant frequency where a positive gain arises around the loop. Some examples of harmonic oscillators are crystal oscillators and LC-tank oscillators. When part of the resonant circuit's capacitance is provided by a varactor diode, the voltage applied to that diode varies the frequency. 7.2 Relaxation oscillators can generate a sawtooth or triangular waveform. They are commonly used in monolithic integrated circuits (ICs). They can provide a wide range of operational frequencies with a minimal number of external components. Relaxation oscillator VCOs can have three topologies: 1) grounded-capacitor VCOs, 2) emitter-coupled VCOs, and 3) delay-based ring VCOs. The first two of these types operate similarly. The amount of time in each state depends on the time for a current to charge or discharge a capacitor. The delay-based ring VCO operates somewhat differently however. For this type, the gain stages are connected in a ring. The output frequency is then a function of the delay in each of stages. 7.3 Harmonic oscillator VCOs have these advantages over relaxation oscillators Frequency stability with respect to temperature, noise, and power supply is much better for harmonic oscillator VCOs. They have good accuracy for frequency control since the frequency is controlled by a crystal or tank circuit. A disadvantage of harmonic oscillator VCOs is that they cannot be easily implemented in monolithic ICs. Relaxation oscillator VCOs are better suited for this technology. Relaxation VCOs are also tunable over a wider range of frequencies. 22

19 Chapter 8 VCO Topologies 8.1 Parallel Tuned Colpitts VCO There are 3 types of BJT Colpitts VCOs. Common-Collector, Common-Emitter and Common- Base. The most used is Common-Collector configuration where the output is often taken from the collector terminal, simply acting as a buffer for the oscillator connection at the base-emitter terminals. This is the only Colpitts arrangement in which the load is not part of the three-terminal model or the oscillator equation; though care must be taken to ensure that the collector output voltage does not significantly feedback through the base-collector junction capacitance. As an alternative, the output of the common collector could also be taken across emitter resistance Re. Fig 8.1 Parallel Tuned Colpitts VCO The ratio of the feedback capacitors in the Colpitts VCO (C3 and C4), is more important than the capacitor s actual values. A good place to start is with a one to one ratio. The loaded Q of the resonator circuit can be increased by reducing C3 or increasing C4. Doing so however, reduces the loop gain in the oscillator, and enough loop gain must be maintained to guarantee oscillation start-up under all conditions (mainly under different temperatures and system output loads). The value of the collector resistor, R3 affects the oscillator loop gain. As in a common collector amplifier, the lower the impedance in the collector circuit the more loop gain the circuit will have. This resistor provides another means of controlling the loop gain of the oscillator since a good oscillator design has just enough loop gain to guarantee reliable oscillation start-up. If there is to much loop gain the oscillator will operate in deep compression which will load the Q of the resonator circuit because the input impedance at the base of the transistor is very low when current saturation occurs. The resistor also tends to minimize the level of the harmonics. L2 is chosen as an RF choke to provide a high impedance in the emitter circuit and ensure that most of the oscillator power is fed back to the base of Q1 instead of being dissipated in R2. Emitter resistor R2 is used for current feedback thus providing a stable DC bias point that will be independent of the beta of the transistor. 23

20 C1 capacitor defines the amount of coupling between the active device and the resonator. The lighter the coupling (a smaller value of C1), the better the loaded Q of the resonator is, which results in a better phases noise performance. However, the compromise is a reduced output power and the potential for the VCO not to start under all operating conditions (especially at higher temperatures when current gain is reduced). Designing the system with too light of a coupling may also results in a sensitive design which may yield potential manufacturing problems. The final tuning component of the oscillator, C2 sets the voltage tuning gain of the oscillator. This capacitor should keep the coupling as light as possible while maintaining the required frequency tuning range of the VCO so that the varactor s phase noise contribution is reduced to a minimum. If the coupling is too light, the oscillator may not start under certain conditions. The worst case condition for this oscillator topology is when V-varicap is set at zero volts. A good way to check if C2 is large enough for reliable oscillator start up is to monitor the output power of the VCO with zero volts on the tune line. The power with V-varicap at 0V should be within 1 db of the power with V-varicap at 3V. If C2 is too small, the output power of the VCO will fall off sharply when V-varicap approaches zero volts or the oscillator may stop completely. One good reason to use a transistor with a high Ft such as the BFP420 (Ft = 25GHz) is that C2 can be small and oscillation start-up will be reliable simultaneously. In order to ensure that the loaded Q of the resonator circuit is not the limiting factor in phase noise performance, the varactor can be replaced with a fixed 2.5pF capacitor and compare the results. A varactor can degrade up to 5-6dB The varactor can reduce the Q of the resonator circuit but this effect is secondary to the varactor modulation due to its own equivalent noise resistance. One way of reducing this effect is to parallel two or more varactors of smaller value while keeping the same tuning curve. This effectively reduces the equivalent noise resistance Series Tuned Colpitts VCO (Clapp VCO) Fig 8.2 Series Tuned Colpitts VCO (Clapp VCO) The series-tuned Colpitts circuit (or Clapp oscillator) works in much the same way as the parallel one. The difference is that the variable capacitor, C1, is positioned so that it is well-protected from being swamped by the large values of C3 and C4. 24

21 In fact, small values of C3, C4 would act to limit the tuning range. Fixed capacitance, C2, is often added across the varicap to allow the tuning range to be reduced to that required, without interfering with C3 and C4, which set the amplifier coupling. The series-tuned Colpitts has a reputation for better stability than the parallel-tuned original. Note how C3 and C4 swamp the capacitances of the amplifier in both versions. The oscillation frequency is given by: ω 2 L = [1/(C2+Cvar)]+(1/C3)+(1/C4) Wideband Colpitts VCO Fig. 8.3 Wideband Colpitts VCO This wideband Colpitts VCO uses a series back-to-back connection of two SMV1232 varactors instead of a single varactor. This connection allows lower capacitance at high voltages, while maintaining the tuning ratio of a single varactor. The back-to-back varactor connection also helps reduce distortion and the effect of fringing and mounting capacitances. The wideband Colpitts feedback capacitances C3, C4 were optimized to provide a flat power response over the wide tuning range. These values may also be re-optimized for phase noise if required. The circuit is very sensitive to the transistor choice (tuning range and stability) due to the wide bandwidth requirement. DC bias is provided through resistors R6 and R7, which may affect phase noise, but allows the exclusion of RF chokes. This reduces costs and the possibility of parasitic resonances which is the common cause of spurious responses and frequency instability. 25

22 8.2 Hartley VCO Fig. 8.4 Hartley VCO The Hartley VCO is similar to the parallel tuned Colpitts, but the amplifier source is tapped up on the tank inductance instead of the tank capacitance. A typical tap placement is 10 to 20% of the total turns up from the cold end of the inductor. (It s usual to refer to the lowest-signal voltage end of an inductor as cold and the other, with the highest signal voltage as hot.). The same as in Colpitts case a good place to start is with a one to one ratio. C2 limits the tuning range as required. C1 is reduced to the minimum value that allows reliable starting. This is necessary because the Hartley s lack of the Colpitts s capacitive divider would otherwise couple the transistor capacitances to the tank more strongly than in the Colpitts, potentially affecting the circuit s frequency stability. 8.3 Wideband Differential Push-Push VCO Fig. 8.5 Wideband Differential Push-Push VCO 26

23 The circuit schematic shows a pair of transistors in a single feedback loop, connected so that collector currents would be 180 shifted. A pair of back-to-back connected SMV1232 varactors is used to allows lower capacitance at the high voltage range, without changing the tuning ratio. Varactor DC biasing is provided through resistors R8, R9 and R10, which may affect the phase noise, but eliminate the need for inductive chokes. This eliminates the possibility of parasitic resonances that could affect the wide tuning range and also cause for frequency instability and spurs. The DC chokes, L1 and L2 are used for phase correction between pairs and their losses is dominated by the series emitter resistors R6 and R7. The DC blocking series capacitances C1 and C2, including associated parasitics, shall have the SRF outside of the tuning range. A three-pole Low Pass Filter at the output is used to filter the unwanted spurious. 8.4 Differential Cross-Coupled VCO Fig. 8.6 Differential Cross-Coupled VCO The cross-coupled differential transistor pair presents a negative resistance to the resonator due to positive feedback. This negative resistance cancel the losses from the resonator enabling sustained oscillation. Frequency variation is achieved with two varicap diodes BB135. An optimal trade-off between thermal noise- induced phase noise and DC power dissipation can be achieved when the oscillation amplitude is designed to set the differential pair transistors to operate at the boundary between saturation and linear regions. The excess noise factor F is dominated by the noise from the tail current source near even harmonics of the carrier frequency. In order to improve phase noise this contribution has to be minimized. An efficient way of doing this is to use a noise filtering technique. An inductor L3 and capacitor C5 forms a 2nd order low-pass filter which prevents noise at even harmonics from being injected into the feedback path of the oscillator. 27

24 The noise filter leaves low-frequency noise from the tail current source unaffected. Low-frequency noise from the tail current source is also up-converted to the carrier as amplitude modulation. Lowfrequency noise on the tuning line modulates the non-linear capacitance of the varactors giving rise to phase noise variation with control voltage. The phase noise degradation due to control voltage noise is very significant at the lower tuning range where the varactors are most non-linear. The stack of two varactors reduces the varactor gain Kvco at the lower tuning range which in turn reduces phase noise variation with control voltage. 8.5 Negative Resistance VCO Fig. 8.7 Negative Resistance VCO The resonator of the Negative Resistance VCO is a series-tuned base network consisting of two series varicap capacitances and an inductor for the positive reactance element. Performance is highly dependent on the transistor type. Certain component values are critical. This oscillator actually works best when lower Ft transistors are used. The circuit can be envisioned as a series-tuned Clapp, with internal transistor base-to-emitter capacitance and collector-toemitter capacitance acting as a voltage divider. Microwave transistors with little internal capacitance do not work well except at the high end of the useful range of this oscillator type. Higher Ft devices required increased capacitance added at the emitter. At the low end of the frequency range, adding external base-toemitter capacitance is sometimes necessary, If bias conditions result in a emitter resistance below about 200 ohms, an RF choke may be required in series with the resistance. This choke must be free of any resonances in the operating frequency range. The output can be taken from several points. The L1 inductor can be tapped. As the tap is moved toward the transistor, more power is coupled out. If the tap is too close to the transistor, the loading reduces the oscillation margin, and the operating frequency becomes more load dependent. The output can be taken by capacitive coupling at the emitter (low level) or at the collector (higher level, but have more spurious). Because the negative resistance oscillator uses a series-tuned resonator, the varactors lead inductance becomes a part of the resonator. This is an advantage over varactor-tuned oscillators using parallel resonators. The base coupling capacitor inductance and transistor base inductance are also absorbed. The loaded Q of negative resistance oscillators is typically less than 5 and this circuit defies attempts at improving the Q. When used as a broadband varactor-tuned VCO, the low loaded Q does not 28

25 limit phase noise performance significantly because varactor modulation noise predominates, particularly at higher offset frequencies. 8.6 Franklin VCO Franklin oscillator uses two transistor stages having the same common terminal (emitter for bipolar device) when the greater power gain and better isolation from the resonant circuit is possible compared with the case of a single-stage configuration. There are two possible configurations for the resonant circuit, parallel and series. The circuit presented below uses a parallel LC resonant circuit (L1 and the varctor diode). In the case of a parallel resonant circuit configuration, the resonant LC circuit is isolated from the input of the first stage and the output of the second stage by means of small shunt capacitances C1 and C2 having high reactances at the resonant frequency. Fig. 8.8 Franklin VCO In this circuit, each stage shifts phase 180 so that the total phase shift is 360 which is equivalent to zero phase shift. We may say that one stage serves as the phase inverting element in place of the RC or LC network which generally performs this function. It is, from an analytical viewpoint, immaterial which stage we choose to look upon as amplifier or phase inverter. The configuration is essentially symmetrical in this respect; both stages provide amplification and phase inversion. The salient feature of the Franklin oscillator is that the tremendous amplification enables operation with very small coupling to the resonant circuit. Therefore, the frequency is relatively little influenced by changes in the active device, and the Q of the resonant circuit is substantially free from degradation. The closest approach to the high frequency stability inherent in this oscillator is attained by restriction of operation to, or near to, the Class-A region. This should not be accomplished by lowering the amplification of the two stages, but, rather by making the capacitors C1 and C2 very small. Additionally, a voltage-follower 'buffer' stage is helpful in this regard. Extraction of energy directly from the resonant tank, would, of course, definitely negate the frequency stability otherwise attainable. Obviously, the Franklin oscillator is intended as a low-power frequency-governing stage, not as a power oscillator. 29

26 8.7 Cascode VCO To provide higher isolation of the load from the VCO resonant circuit a cascode VCO configuration, can be used. The negative resistance oscillation conditions for common emitter transistor Q1 are provided by using the feedback inductance L1. Fig. 8.9 Cascode VCO 8.8 Vackar VCO And here is the winner. If you want to build a very stable, low phase noise, and low spurious VCO, definitely Vackar VCO is the choice. This is not a common type in the RF professional world, one reason could be the name of its inventor. A Vackar VCO is a variation of the split-capacitance oscillator model. It is similar to a Colpitts or Clapp VCO in this respect. It differs in that the output level is more stable over frequency, and has a wider bandwidth when compared to a Colpitts or Clapp design. Fig Vackar VCO The Vackar VCO circuit incorporates a π-section tank to attain the needed 180 phase-reversal in the feedback loop. 30

27 However, the inverted feedback signal is not directly fed back to the input of the active device; rather, it is loosely coupled through a small capacitor. Often, a shunt capacitor is introduced to further reduce the coupling. The basic idea is to isolate the resonant circuit as much as possible from the input of the active device, consistent with obtaining reliable oscillation. This circuit is particularly advantageous with solid-state devices, and especially with bipolar transistors that have inordinately-low input impedances and that present a widely-varying reactance to the tuned circuit as a consequence of temperature and voltage changes. Once the overall circuit is operational, the values of capacitance C1 in series with C var and collector capacitance (C2) may be optimized for best stability. Generally, it will be found that the capacitor closest to the collector of the transistor can be several times larger than the capacitor associated with the base circuit. The introduction of attenuation in the feedback loop (via the small capacitor in the Vackar) prevents over-excitation and effectively isolates the resonant circuit from the active device. The frequency tuning range of Vackar VCO is above one octave, not observable to many oscillator types. The frequency tuning is provided independently of the coupling to the LC tank circuit. The parametric variables of the transistor (which depends by the bias current and temperature), are isolated from the resonator. The transistor input is not overloaded as other VCO circuits and the collector output has low impedance providing low gain just to maintain the oscillation. The feedback division ratio is fixed (typical range for coupling ratio is 1:4 up to 1:9). Even if the VCO is tuned, the impedance divider is fixed, in this way increasing the stability. Two negative sides of Vackar VCO are the critical starting oscillation point, and the low output level, which always requires to use a buffer amplifier. When the oscillation doesn t start means that it doesn t have enough positive feedback, as for to begin the oscillation and maintain it in the time. In the above schematic C3 and C4 are critical values finding this point. L2 is used as an RF choke with SRF outside of the frequency range, to don t affect the tuning range and flatness over frequency. It is important that the RF choke in the collector circuit 'looks good' at the operating frequency (presents a high inductive reactance). Resonances from distributed capacitance in the choke windings, especially those in the series-resonant mode, can degrade stability or even inhibit oscillation. Ferrite-core chokes are generally suitable for this application. Sensitivity to RF choke characteristics is common to all oscillator circuits that use chokes for shunt-feeding the DC operating voltage to the oscillator. 31

28 Chapter 9 Voltage Controlled Mechanism Fig. 9.1 Ring oscillator using differential configuration The resistors shown in the above diagram can be replaced with active MOSFETs that are biased in the linear region of V-I characteristics curve which is shown below. B C A s Fig.9.2 Drain current vs. Drain-Source voltage. The MOSFETs are biased in the region AB. As in this region V I, therefore here the MOS acts as a resistor. As we have already seen in the Ring Oscillator that relation between the output frequency & time delay is given by, F out = 1/2NT d 32

29 The T d depends upon resistance(r) & capacitance (c) of the Ring Oscillator. This capacitance is parasitic in nature & hence can t be controlled. So only by controlling R we can control T d. M 1 M 2 M 3 M 4 Fig. 9.3 The resistance of the two PMOS(M 1 and M 2 ) is denoted by Ron. Relation between R on & the gate voltage of the two MOS is given by: R on = 1 /µ n c ox (w/l)(v GS -V TH ) Therefore R on is inversely proportional to V gs. So by controlling V gs we can vary Resistance(R on ). By varying R on we can vary T d & hence from eq. We can vary F out. Therefore by controlling V gs we can control F out. In the control circuit of VCO if we apply a control voltage(v control ) then we can control the output frequency of VCO which is F out. Thus if V control is increased PMOS will move towards turning off. So resistance will decrease & F out will increase. The common-source topology exhibits a relatively high input impedence while providing voltage gain & requiring a minimal voltage headroom. As such it finds wide application in analog circuits & its frequency response is of interest. Fig. 9.4 Common-source topology 33

30 Above fig. is of a common- source resistance,r s. We identify all of the capacitances of the circuits,noting that C gs & C db are grounded capacitances while C gd appears between the input & the output. Assuming that & M 1 operates in saturation,let us find estimate the transfer function by associating one pole with each node. The total capacitance seen from X to ground is equal to C gs plus the Miller multiplication of C gd : C gs + (1- A v )C gd, where A v = -g m R d. The magnitude of the input pole is therefore given by W in = 1/R s [C gs +(1+g m R d )C gd ] At the output node,the total capacitance seen to ground is equal to C db plus the Miller effect of C gd : C db + (1-Av -1 )C gd = C db + C gd.thus, W out = 1/R d (C db + C gd ) Another approximation of the output pole can be obtained if R s is relatively large. Simplifying the circuit as shown in the fig. below where the effect of R s is neglected, Fig. 9.5 Where C eq = C gd C gs /(C gd + C gs ). Thus the output pole is roughly equal to We then surmise the transfer function is V out /V in = -g m R d /(1+s/w in )(1+s/w out ) 34

31 Chapter 10 Design Description 10.1 Differential amplifier: 10.2 Ring Oscillator The first circuit shows a differential amplifier which forms the basic unit of the voltage controlled oscillator. The differential amplifier consists of two PMOS at the top, two in the middle and two NMOS at the bottom. 35

32 The two PMOS, P1 and P2 have Vb1 and Vb2 as inputs respectively. These PMOS are biased in the linear region and hence they act as active resistors. The resistance may be denoted as Ron. The two PMOS, P3 and P4 are the main driver MOS with inputs as Inp and Inm. The two NMOS, N1 and N2 are both controlled by tuning voltage Vtune. Therefore they act like constant current source to bias the differential amplifier circuit. The current flowing through them is controlled by Vtune. This current is denoted by Iss. In this circuit the product of Iss and Ron has to be a constant else the current to NMOS will change. The second circuit shows a Ring Oscillator. It is a cascaded stage of N number of differential amplifiers (where N is odd number). The propagation delay of each amplifier equals to RC time delay. Therefore as the number of amplifiers increase the RC time delay also increases. Frequency of oscillation f out = 1/ (2NT d ) where Td is propagation delay of each stage. The Vb1 and Vb2 act as control voltage of the Ring Oscillator circuit. If the Vb1 or Vb2 is changed, the resistance R in RC time delays also changes. The parasitic capacitance C is not possible to change. Only R can be controlled. Hence the propagation time delay (T d ) can be controlled by changing the voltages Vb1 and Vb2. And by changing this Td the frequency fout can be changed Control Circuit: The above circuit is the control circuit for the voltage controlled oscillator. There are two arms with two PMOS and one NMOS in each of the arm. The Vtune controls the current flow. It is basically a cascade current mirror circuit. The Vb1 and Vb2 voltages are controlled by this control circuit. Vbias shown is ideally grounded. If this Vbias is increased, the current flow decreases. This is because current flow depends upon gate to source voltage and drain to source voltage. By varying this current, the current flow in the left arm changes. Now as the circuit acts like a current mirror, the current flow in the other arm also changes. The 36

33 voltage varies at resistor output and hence the Vb1 and Vb2 voltages to differential amplifier change. And by this change in the Vb1 and Vb2 voltages, the propagation time delay can be controlled Voltage controlled Oscillator The output that is obtained through the VCO is differential in nature. This differential output has to be converted to a single ended output. This is achieved through the above circuit. The differential output is passed through an amplifier and converted to a single ended output. Thus we get a single output and hence this is the final circuit of the VCO Program: * SPICE export by: SEDIT * Export time: Thu Nov 11 10:56: * Design: vco1 * Cell: system * View: Main * Export as: top-level cell * Export mode: hierarchical * Exclude.model: no * Exclude.end: no * Expand paths: yes * Wrap lines: no * Root path: F:\spice\vco1 * Exclude global pins: no * Control property name: SPICE ********* Simulation Settings - General section *********.lib "E:\Tanner\Libraries\Models\Generic_025.lib" TT *************** Subcircuits *****************.subckt contrl Vb1 Vb2 Vbias Vtune Gnd Vdd * Devices: SPICE.ORDER >

34 MM7n N_1 Vtune Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MM6n Vb2 N_2 N_1 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MM5n N_2 N_2 Vbias 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MM4p Vb2 Vb2 Vb1 Vdd PMOS W=5u L=250n AS=4.5p PS=11.8u AD=4.5p PD=11.8u MM3p N_2 Vb2 N_3 Vdd PMOS W=5u L=250n AS=4.5p PS=11.8u AD=4.5p PD=11.8u MM2p Vb1 Vb1 Vdd Vdd PMOS W=5u L=250n AS=4.5p PS=11.8u AD=4.5p PD=11.8u MM1p N_3 Vb1 Vdd Vdd PMOS W=5u L=250n AS=4.5p PS=11.8u AD=4.5p PD=11.8u.ends.subckt diffamp Inm Inp Outm Outp VTune Vb1 Vb2 Gnd Vdd W=5.00u * Devices: SPICE.ORDER > MN1 Outm VTune Gnd Gnd NMOS W=2.5u L=2u AS=2.25p PS=6.8u AD=2.25p PD=6.8u MN2 Outp VTune Gnd Gnd NMOS W=2.5u L=2u AS=2.25p PS=6.8u AD=2.25p PD=6.8u MP1 N_2 Vb1 Vdd Vdd PMOS W=5u L=250n AS=4.5p PS=11.8u AD=4.5p PD=11.8u MP2 N_1 Vb2 N_2 Vdd PMOS W=5u L=250n AS=4.5p PS=11.8u AD=4.5p PD=11.8u MP3 Outm Inp N_1 Vdd PMOS W=W L=250n AS='if(1, (900n*if(0,W/1,W)+floor(1/2)*1.25u*if(0,W/1,W)), (2*900n*if(0,W/1,W)+(floor(1/2)- 1)*1.25u*if(0,W/1,W)))' PS='if(1, (2*900n+if(0,W/1,W)+if(0,W/1,W)*1+floor(1/2)*2*(1.25u+if(0,W/1,W)*1)), (2*2*900n+if(0,W/1,W)+if(0,W/1,W)*1+(floor(1/2)-1)*2*(1.25u+if(0,W/1,W)*1)))' AD='if(1, (900n*if(0,W/1,W)+floor(1/2)*1.25u*if(0,W/1,W)), floor(1/2)*1.25u*if(0,w/1,w))' PD='if(1, (2*900n+if(0,W/1,W)+if(0,W/1,W)*1+floor(1/2)*2*(1.25u+if(0,W/1,W)*1)), floor(1/2)*2*(1.25u+if(0,w/1,w)*1))' MP4 Outp Inm N_1 Vdd PMOS W=W L=250n AS='if(1, (900n*if(0,W/1,W)+floor(1/2)*1.25u*if(0,W/1,W)), (2*900n*if(0,W/1,W)+(floor(1/2)- 1)*1.25u*if(0,W/1,W)))' PS='if(1, (2*900n+if(0,W/1,W)+if(0,W/1,W)*1+floor(1/2)*2*(1.25u+if(0,W/1,W)*1)), (2*2*900n+if(0,W/1,W)+if(0,W/1,W)*1+(floor(1/2)-1)*2*(1.25u+if(0,W/1,W)*1)))' AD='if(1, (900n*if(0,W/1,W)+floor(1/2)*1.25u*if(0,W/1,W)), floor(1/2)*1.25u*if(0,w/1,w))' PD='if(1, (2*900n+if(0,W/1,W)+if(0,W/1,W)*1+floor(1/2)*2*(1.25u+if(0,W/1,W)*1)), floor(1/2)*2*(1.25u+if(0,w/1,w)*1))'.ends.subckt core Outn Outp Vbias Vtune Gnd Vdd WP=5.00u Xcontrl_1 N_3 N_2 Vbias Vtune Gnd Vdd contrl Xdiffamp_1 Outp Outn N_6 N_5 Vtune N_3 N_2 Gnd Vdd diffamp W=5.00u Xdiffamp_2 N_5 N_6 N_9 N_8 Vtune N_3 N_2 Gnd Vdd diffamp W=5.00u Xdiffamp_3 N_8 N_9 N_11 N_10 Vtune N_3 N_2 Gnd Vdd diffamp W=5.00u Xdiffamp_4 N_10 N_11 N_13 N_12 Vtune N_3 N_2 Gnd Vdd diffamp W=5.00u Xdiffamp_5 N_12 N_13 N_15 N_14 Vtune N_3 N_2 Gnd Vdd diffamp W=5.00u Xdiffamp_6 N_14 N_15 N_17 N_16 Vtune N_3 N_2 Gnd Vdd diffamp W=5.00u Xdiffamp_7 N_16 N_17 Outn Outp Vtune N_3 N_2 Gnd Vdd diffamp W=5.00u.ends ********* Simulation Settings - Parameters and SPICE Options *********.param Vpower =

35 * Devices: SPICE.ORDER == Xcore_1 N_4 N_3 N_1 N_2 Gnd Vdd core WP=5.00u * Devices: SPICE.ORDER > MMN1 N_5 N_3 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MMN2 Out N_4 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MMP2 Out N_5 Vdd Vdd PMOS W=2.5u L=250n M=2 AS=4.5p PS=13.6u AD=3.125p PD=7.5u MMP1 N_5 N_5 Vdd Vdd PMOS W=2.5u L=250n M=2 AS=4.5p PS=13.6u AD=3.125p PD=7.5u Vvdd Vdd Gnd DC Vpower Vvbias N_1 Gnd DC 600m Vvtune N_2 Gnd PWL(0s 0v 10ns 0v 20ns.5v 40ns 0.9v 50ns 1.5v 70ns 1.5v 90ns 0.9v 100ns 0v).PRINT TRAN V(N_2).PRINT TRAN V(Out).MEASURE TRAN SlowFreq_Period TRIG V(Out) VAL='Vpower/2.0' TD='4.5n' RISE='1' TARG V(Out) VAL='Vpower/2.0' TD='4.5n' RISE='1+1' OFF.MEASURE TRAN SlowFreq PARAM='1.0/SlowFreq_Period*1' ON.MEASURE TRAN FastFreq_Period TRIG V(Out) VAL='Vpower/2.0' TD='45n' RISE='1' TARG V(Out) VAL='Vpower/2.0' TD='45n' RISE='1+1' OFF.MEASURE TRAN FastFreq PARAM='1.0/FastFreq_Period*1' ON ********* Simulation Settings - Analysis section *********.op.tran/powerup 100p 100n ********* Simulation Settings - Additional SPICE commands *********.OPTIONS poweruplen=1ns.end 39

36 Chapter 11 Simulation Results 11.1 Result T-Spice - Tanner SPICE Version Standalone hardware lock Product Release ID: T-Spice Win :01:33 Copyright Tanner EDA Opening output file "C:\DOCUME~1\Ist\LOCALS~1\Temp\system.out" Parsing "C:\DOCUME~1\Ist\LOCALS~1\Temp\system.sp" Reading library entry "TT" from "E:\Tanner\Libraries\Models\Generic_025.lib" Reading library entry "TT_NMOS_PARAMETERS" from "Generic_025.lib" Reading library entry "TT_PMOS_PARAMETERS" from "Generic_025.lib" Reading library entry "MOS_BIN_MODEL" from "Generic_025.lib" Reading library entry "Typ" from "Generic_025.lib" Reading library entry "RES_CAP" from "Generic_025.lib" Loaded BSIM3v31 model library, Berkeley BSIM3 VERSION 3.1 with extensions Accuracy and Convergence options: numndset dchold = 100 Timestep and Integration options: poweruplen = 1e-009 relq relchgtol = Model Evaluation options: dcap = 2 defnrb = 0 [sq] defnrd = 0 [sq] defnrs = 0 [sq] tnom = 25 [deg C] General options: temp = 25 [deg C] threads = 2 Output options: acout = 1 ingold = 0 Device and node counts: MOSFETs - 53 MOSFET geometries - 5 BJTs - 0 JFETs - 0 MESFETs - 0 Diodes - 0 Capacitors - 0 Resistors - 0 Inductors - 0 Mutual inductors - 0 Transmission lines - 0 Coupled transmission lines - 0 Voltage sources - 3 Current sources - 0 VCVS - 0 VCCS - 0 CCVS - 0 CCCS - 0 V-control switch - 0 I-control switch - 0 Macro devices - 0 External C model instances - 0 HDL devices - 0 Subcircuits - 0 Subcircuit instances - 9 Independent nodes - 35 Boundary nodes - 4 Total nodes

37 Measurement result summary SlowFreq = e+007 FastFreq = e+008 Parsing 0.03 seconds Setup 0.05 seconds DC operating point 0.05 seconds Transient Analysis 1.61 seconds Overhead 2.22 seconds Total 3.95 seconds Simulation completed 11.2 Waveform When the input is (which is shown in yellow colour in the above figure) the resulting output is shown (in green colour). Its clear from the output that at the places where the input is same (not changing), the output frequency is also Constant. When the input is changing the output frequency also changes according to that input 11.3 Measurement result summary SlowFreq = e+007 FastFreq = e