HI5812. CMOS 20 Microsecond, 12-Bit, Sampling A/D Converter with Internal Track and Hold. Features. Applications. Ordering Information.

Transcription

1 Data Sheet March 31, 2005 FN MOS 20 Microsecond, 12-it, Sampling /D onverter with Internal Track and Hold The is a fast, low power, 12-bit, successive approximation analog-to-digital converter. It can operate from a single 3V to 6V supply and typically draws just 1.9m when operating at 5V. The features a built-in track and hold. The conversion time is as low as 20µs with a 5V supply. The twelve data outputs feature full high speed MOS three-state bus driver capability, and are latched and held through a full conversion cycle. The output is user selectable, i.e., 12-bit, 8-bit (MSs), and/or 4-bit (LSs). data ready flag, and conversion-start input complete the digital interface. n internal clock is provided and is available as an output. The clock may also be over-driven by an external source. Ordering Information PRT NUMER INL (LS) (MX OVER TEMP.) TEMP. RNGE ( o ) PKGE PKG. DWG. # JIP ± to Ld PDIP E24.3 JIPZ (See Note) ± to Ld PDIP* (Pb-free) E24.3 Features onversion Time µs Throughput Rate ksps uilt-in Track and Hold Guaranteed No Missing odes Over Temperature Single Supply Voltage V Maximum Power onsumption mW Internal or External lock Pb-Free vailable (RoHS ompliant) pplications Remote Low Power Data cquisition Systems Digital udio DSP Modems General Purpose DSP Front End µp ontrolled Measurement System Professional udio Positioner/Fader Pinout (PDIP, SOI) TOP VIEW JI ± to Ld SOI M24.3 DRDY 1 24 V DD JIZ (See Note) ± to Ld SOI (Pb-free) M24.3 KI ± to Ld SOI M24.3 (LS) D0 D1 D2 D OEL STRT V REF - KIZ (See Note) ± to Ld SOI (Pb-free) M24.3 D4 D V REF + V IN *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IP/JEDE J STD-020. D6 D7 D8 D9 V SS V + V - OEM D11 (MS) D10 1 UTION: These devices are sensitive to electrostatic discharge; follow proper I Handling Procedures INTERSIL or Intersil (and design) is a registered trademark of Intersil mericas Inc. opyright Intersil mericas Inc. 2001, ll Rights Reserved ll other trademarks mentioned are the property of their respective owners.

2 Functional lock Diagram V DD V SS TO INTERNL LOGI STRT V IN 32 ONTROL + TIMING LOK DRDY V REF + 50Ω SUSTRTE OEM D11 (MS) D10 V + 2 D9 D8 V IT SUESSIVE PPROXIMTION REGISTER 12-IT EDGE TRIGGERED D LTHES D7 D6 D5 2 D4 P1 D3 D2 V REF - D1 D0 (LS) OEL 2

3 bsolute Maximum Ratings Supply Voltage V DD to V SS (V SS -0.5V) < V DD < +6.5V V + to V (V SS -0.5V) to (V SS +6.5V) V + to V DD ±0.3V nalog and Reference Inputs V IN, V REF +, V REF (V SS -0.3V) < V IN < (V DD +0.3V) Digital I/O Pins (V SS -0.3V) < V I/O < (V DD +0.3V) Operating onditions Temperature Range o to 85 o Thermal Information Thermal Resistance (Typical, Note 1) θ J ( o /W) PDIP Package* SOI Package Maximum Junction Temperature Plastic Packages o Maximum Storage Temperature Range ο to 150 o Maximum Lead Temperature (Soldering, 10s) o (SOI - Lead Tips Only) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. UTION: Stresses above those listed in bsolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θ J is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech rief T379 for details. Electrical Specifications V DD = V + = 5V, V REF + = V, V SS = V - = V REF - = GND, = External 750kHz, Unless Otherwise Specified 25 o -40 o TO 85 o PRMETER TEST ONDITIONS MIN TYP MX MIN MX UNITS URY Resolution its Integral Linearity Error, INL (End Point) J - - ±1.5 - ±1.5 LS K - - ±1.0 - ±1.0 LS Differential Linearity Error, DNL J - - ±2.0 - ±2.0 LS K - - ±1.0 - ±1.0 LS Gain Error, FSE (djustable to Zero) Offset Error, V OS (djustable to Zero) J - - ±3.0 - ±3.0 LS K - - ±2.5 - ±2.5 LS J - - ±2.0 - ±2.0 LS K - - ±1.0 - ±1.0 LS Power Supply Rejection, PSRR Offset Error PSRR Gain Error PSRR V REF = 4V V DD = V + = 5V ±5% V DD = V + = 5V ±5% - ±0.1 ±0.1 ±0.5 ±0.5 - ±0.5 ±0.5 LS LS DYNMI HRTERISTIS Signal to Noise Ratio, SIND RMS Signal J f S = Internal lock, f IN = 1kHz f S = 750kHz, f IN = 1kHz d d RMS Noise + Distortion K f S = Internal lock, f IN = 1kHz f S = 750kHz, f IN = 1kHz d d Signal to Noise Ratio, SNR RMS Signal J f S = Internal lock, f IN = 1kHz f S = 750kHz, f IN = 1kHz d d RMS Noise K f S = Internal lock, f IN = 1kHz f S = 750kHz, f IN = 1kHz d d Total Harmonic Distortion, THD J f S = Internal lock, f IN = 1kHz f S = 750kHz, f IN = 1kHz dc dc K f S = Internal lock, f IN = 1kHz f S = 750kHz, f IN = 1kHz dc dc 3

4 Electrical Specifications V DD = V + = 5V, V REF + = V, V SS = V - = V REF - = GND, = External 750kHz, Unless Otherwise Specified (ontinued) 25 o -40 o TO 85 o PRMETER TEST ONDITIONS MIN TYP MX MIN MX UNITS Spurious Free Dynamic Range, SFDR J f S =Internal lock, f IN = 1kHz f S = 750kHz, f IN = 1kHz d d K f S = Internal lock, f IN = 1kHz f S = 750kHz, f IN = 1kHz d d NLOG INPUT Input urrent, Dynamic t V IN = V REF +, 0V - ±50 ±100 - ±100 µ Input urrent, Static onversion Stopped - ±0.4 ±10 - ±10 µ Input andwidth -3d MHz Reference Input urrent µ Input Series Resistance, R S In Series with Input SMPLE W Input apacitance, SMPLE During Sample State pf Input apacitance, HOLD During Hold State pf DIGITL INPUTS OEL, OEM, STRT High-Level Input Voltage, V IH V Low-Level Input Voltage, V IL V Input Leakage urrent, I IL Except, V IN = 0V, 5V - - ±10 - ±10 µ Input apacitance, IN pf DIGITL OUTPUTS High-Level Output Voltage, V OH I SOURE = -400µ V Low-Level Output Voltage, V OL I SINK = 1.6m V Three-State Leakage, I OZ Except DRDY, V OUT = 0V, 5V - - ±10 - ±10 µ Output apacitance, OUT Except DRDY pf LOK High-Level Output Voltage, V OH I SOURE = -100µ (Note 2) V Low-Level Output Voltage, V OL I SINK = 100µ (Note 2) V Input urrent Only, V IN = 0V, 5V - - ±5 - ±5 m TIMING onversion Time (t ONV + t Q ) (Includes cquisition Time) µs lock Frequency Internal lock, ( = Open) khz External (Note 2) MHz lock Pulse Width, t LOW, t HIGH External (Note 2) ns perture Delay, t D PR (Note 2) ns lock to Data Ready Delay, t D1 DRDY (Note 2) ns lock to Data Ready Delay, t D2 DRDY (Note 2) ns Start Removal Time, t R STRT (Note 2) ns Start Setup Time, t SU STRT (Note 2) ns Start Pulse Width, t W STRT (Note 2) ns Start to Data Ready Delay, t D3 DRDY (Note 2) ns 4

5 Electrical Specifications V DD = V + = 5V, V REF + = V, V SS = V - = V REF - = GND, = External 750kHz, Unless Otherwise Specified (ontinued) 25 o -40 o TO 85 o PRMETER TEST ONDITIONS MIN TYP MX MIN MX UNITS lock Delay from Start, t D STRT (Note 2) ns Output Enable Delay, t EN (Note 2) ns Output Disabled Delay, t DIS (Note 2) ns POWER SUPPLY HRTERISTIS Supply urrent, I DD + I m NOTE: 2. Parameter guaranteed by design or characterization, not production tested. Timing Diagrams (EXTERNL OR INTERNL) t D1 DRDY t LOW STRT t D2 DRDY t HIGH DRDY D0 - D11 DT N - 1 DT N V IN HOLD N TRK N TRK N + 1 OEL = OEM = V SS FIGURE 1. ONTINUOUS ONVERSION MODE 5

6 Timing Diagrams (ontinued) (EXTERNL) t R STRT t SU STRT t W STRT STRT t D3 DRDY DRDY V IN HOLD TRK HOLD FIGURE 2. SINGLE SHOT MODE EXTERNL LOK (INTERNL) t R STRT t D STRT t W STRT STRT DON T RE t D3 DRDY DRDY V IN HOLD TRK HOLD FIGURE 3. SINGLE SHOT MODE INTERNL LOK 6

7 Timing Diagrams (ontinued) OEL OR OEM ten t DIS 1.6m D0 - D3 OR D4 - D11 HIGH IMPEDNE TO HIGH HIGH IMPEDNE TO LOW 50% 50% 90% 10% TO OUTPUT PIN 50pF -1.6m +2.1V FIGURE 4. FIGURE 4. FIGURE 4. OUTPUT ENLE/DISLE TIMING DIGRM 1.6m 50pF +2.1V -400µ FIGURE 5. GENERL TIMING LOD IRUIT 7

8 Typical Performance urves V DD = V + = 5V, V REF + = 4.608V 1.5 V DD = V + = 5V V REF + = 4.608V. = INTERNL. = 750kHz. = 1MHz INL ERROR (LSs) = INTERNL. = 750kHz. = 1MHz TEMPERTURE ( o ) V OS ERROR (LSs) TEMPERTURE ( o ) FIGURE 6. INL vs TEMPERTURE FIGURE 7. OFFSET VOLTGE vs TEMPERTURE 1.0 V DD = V + = 5V, V REF + = 4.608V 2 V DD = V + = 5V, T = 25 o = 750kHz DNL ERROR (LSs) = INTERNL. = 750kHz. = 1MHz TEMPERTURE ( o ) ERROR (LSs) FSE DNL INL V OS REFERENE VOLTGE, V REF (V) FIGURE 8. DNL vs TEMPERTURE FIGURE 9. URY vs REFERENE VOLTGE FS ERROR (LSs) V DD = V + = 5V, V REF + = 4.608V. = INTERNL. = 750kHz. = 1MHz PSRR (LSs) V DD = V + = 5V ±5% = 750kHz V REF + = 4.0V PSRR V OS TEMPERTURE ( o ) PSRR FSE TEMPERTURE ( o ) FIGURE 10. FULL SLE ERROR vs TEMPERTURE FIGURE 11. POWER SUPPLY REJETION vs TEMPERTURE 8

9 Typical Performance urves (ontinued) SUPPLY URRENT, I DD (m) 8 V DD = V + = 5V, V REF + = 4.608V INTERNL LOK TEMPERTURE ( o ) FIGURE 12. SUPPLY URRENT vs TEMPERTURE MPLITUDE (d) FREQUENY INS FIGURE 13. FFT SPETRUM INPUT FREQUENY = 1kHz SMPLING RTE = 50kHz SNR = 72.1d SIND = 71.4d EFFETIVE ITS = 11.5 THD = -79.1dc PEK NOISE = -80.9d SFDR = -80.9d 2000 INTERNL LOK FREQUENY (khz) 500 V DD = V + = 5V, V REF + = 4.608V ENO (ITS) V DD = V + = 5V V REF + = 4.608V 9 T = 25 o. = INTERNL 8. = 750kHz. = 1MHz TEMPERTURE ( o ) INPUT FREQUENY (khz) FIGURE 14. INTERNL LOK FREQUENY vs TEMPERTURE FIGURE 15. EFFETIVE ITS vs INPUT FREQUENY THD (dc) V DD = V + = 5V V REF + = 4.608V T = 25 o. =INTERNL. = 750kHz. = 1MHz SNR (dc) V DD = V + = 5V V REF + = 4.608V T = 25 o. = INTERNL. = 750kHz. = 1MHz INPUT FREQUENY (khz) INPUT FREQUENY (khz) FIGURE 16. TOTL HRMONI DISTORTION vs INPUT FREQUENY FIGURE 17. SIGNL NOISE RTIO vs INPUT FREQUENY 9

10 TLE 1. PIN DESRIPTIONS PIN NO. NME DESRIPTION 1 DRDY Output flag signifying new data is available. Goes high at end of clock period 15. Goes low when new conversion is started. 2 D0 it 0 (Least Significant it, LS). 3 D1 it 1. 4 D2 it 2. 5 D3 it 3. 6 D4 it 4. 7 D5 it 5. 8 D6 it 6. 9 D7 it D8 it D9 it V SS Digital Ground (0V). 13 D10 it D11 it 11 (Most Significant it, MS). 15 OEM Three-State Enable for D4-D11. ctive low input. 16 V - nalog Ground, (0V). 17 V + nalog Positive Supply. (+5V) (See text.) 18 V IN nalog Input. 19 V REF + Reference Voltage Positive Input, sets 4095 code end of input range. 20 V REF - Reference Voltage Negative Input, sets 0 code end of input range. 21 STRT Start onversion Input ctive Low, recognized after end of clock period Input or Output. onversion functions are synchronized to positive going edge. (See text.) 23 OEL Three-State Enable for D0 D3. ctive Low Input. 24 V DD Digital Positive Supply (+5V). Theory of Operation is a MOS 12-it nalog-to-digital onverter that uses capacitor-charge balancing to successively approximate the analog input. binarily weighted capacitor network forms the /D heart of the device. See the block diagram for the. The capacitor network has a common node which is connected to a comparator. The second terminal of each capacitor is individually switchable to the input, V REF + or V REF -. During the first three clock periods of a conversion cycle, the switchable end of every capacitor is connected to the input and the comparator is being auto-balanced at the capacitor common node. During the fourth period, all capacitors are disconnected from the input; the one representing the MS (D11) is connected to the V REF + terminal; and the remaining capacitors to V REF -. The capacitor-common node, after the charges balance out, will indicate whether the input was above 1 / 2 of (V REF + - V REF -). t the end of the fourth period, the comparator output is stored and the MS capacitor is either left connected to V REF + (if the comparator was high) or returned to V REF -. This allows the next comparison to be at either 3 / 4 or 1 / 4 of (V REF + - V REF -). t the end of periods 5 through 14, capacitors representing D10 through D1 are tested, the result stored, and each capacitor either left at V REF + or at V REF -. t the end of the 15th period, when the LS (D0) capacitor is tested, (D0) and all the previous results are shifted to the output registers and drivers. The capacitors are reconnected to the input, the comparator returns to the balance state, and the data-ready output goes active. The conversion cycle is now complete. nalog Input The analog input pin is a predominately capacitive load that changes between the track and hold periods of the conversion cycle. During hold, clock period 4 through 15, the input loading is leakage and stray capacitance, typically less than 5µ and 20pF. t the start of input tracking, clock period 1, some charge is dumped back to the input pin. The input source must have low enough impedance to dissipate the current spike by the end of the tracking period as shown in Figure 18. The amount of charge is dependent on supply and input voltages. The average current is also proportional to clock frequency. I IN DRDY 20m 10m 0m 5V 0V 5V 0V 200ns/DIV. ONDITIONS: V DD = V + = 5.0V, V REF + = 4.608V, V IN = 4.608V, = 750kHz, T = 25 o FIGURE 18. TYPIL NLOG INPUT URRENT s long as these current spikes settle completely by end of the signal acquisition period, converter accuracy will be preserved. The analog input is tracked for 3 clock cycles. With an external clock of 750kHz the track period is 4µs. 10

11 simplified analog input model is presented in Figure 19. During tracking, the /D input (V IN ) typically appears as a 380pF capacitor being charged through a 420Ω internal switch resistance. The time constant is 160ns. To charge this capacitor from an external zero Ω source to 0.5 LS (1/8192), the charging time must be at least 9 time constants or 1.4µs. The maximum source impedance (R SOURE Max) for a 4µs acquisition time settling to within 0.5LS is 750Ω. If the clock frequency was slower, or the converter was not restarted immediately (causing a longer sample time), a higher source impedance could be tolerated. V IN RSW 420Ω R SOURE R SOURE(MX) = t Q SMPLE In[ 2 N 1) R SW ] SMPLE 380pF FIGURE 19. NLOG INPUT MODEL IN TRK MODE Reference Input The reference input V REF + should be driven from a low impedance source and be well decoupled. s shown in Figure 20, current spikes are generated on the reference pin during each bit test of the successive approximation part of the conversion cycle as the chargebalancing capacitors are switched between V REF - and V REF + (clock periods 5-14). These current spikes must settle completely during each bit test of the conversion to not degrade the accuracy of the converter. Therefore V REF + and V REF - should be well bypassed. Reference input V REF - is normally connected directly to the analog ground plane. If V REF - is biased for nulling the converters offset it must be stable during the conversion cycle. 20m The is specified with a 4.608V reference, however, it will operate with a reference down to 3V having a slight degradation in performance. typical graph of accuracy vs reference voltage is presented. Full Scale and Offset djustment In many applications the accuracy of the would be sufficient without any adjustments. In applications where accuracy is of utmost importance full scale and offset errors may be adjusted to zero. The V REF + and V REF - pins reference the two ends of the analog input range and may be used for offset and full scale adjustments. In a typical system the V REF - might be returned to a clean ground, and the offset adjustment done on an input amplifier. V REF + would then be adjusted to null out the full scale error. When this is not possible, the V REF - input can be adjusted to null the offset error, however, V REF - must be well decoupled. Full scale and offset error can also be adjusted to zero in the signal conditioning amplifier driving the analog input (V IN ). ontrol Signal The may be synchronized from an external source by using the STRT (Start onversion) input to initiate conversion, or if STRT is tied low, may be allowed to free run. Each conversion cycle takes 15 clock periods. The input is tracked from clock period 1 through period 3, then disconnected as the successive approximation takes place. fter the start of the next period 1 (specified by t D data), the output is updated. The DRDY (Data Ready) status output goes high (specified by t D1 DRDY) after the start of clock period 1, and returns low (specified by t D2 DRDY) after the start of clock period 2. The 12 data bits are available in parallel on three-state bus driver outputs. When low, the OEM input enables the most significant byte (D4 through D11) while the OEL input enables the four least significant bits (D0 - D3). t EN and t DIS specify the output enable and disable times. I REF+ 10m 0m 5V 0V If the output data is to be latched externally, either the trailing edge of data ready or the next falling edge of the clock after data ready goes high can be used. When STRT input is used to initiate conversions, operation is slightly different depending on whether an internal or external clock is used. DRDY 5V 0V 2µs/DIV. ONDITIONS: V DD = V + = 5.0V, V REF + = 4.608V, V IN = 2.3V, = 750kHz, T = 25 o FIGURE 20. TYPIL REFERENE INPUT URRENT Figure 3 illustrates operation with an internal clock. If the STRT signal is removed (at least t R STRT) before clock period 1, and is not reapplied during that period, the clock will shut off after entering period 2. The input will continue to track and the DRDY output will remain high during this time. low signal applied to STRT (at least t W STRT wide) can now initiate a new conversion. The STRT signal (after a delay of (t D STRT)) causes the clock to restart. 11

12 Depending on how long the clock was shut off, the low portion of clock period 2 may be longer than during the remaining cycles. The input will continue to track until the end of period 3, the same as when free running. Figure 2 illustrates the same operation as above but with an external clock. If STRT is removed (at least t R STRT) before clock period 2, a low signal applied to STRT will drop the DRDY flag as before, and with the first positive-going clock edge that meets the (t SU STRT) setup time, the converter will continue with clock period 3. lock The can operate either from its internal clock or from one externally supplied. The pin functions either as the clock output or input. ll converter functions are synchronized with the rising edge of the clock signal. Figure 21 shows the configuration of the internal clock. The clock output drive is low power: if used as an output, it should not have more than 1 MOS gate load applied, and stray wiring capacitance should be kept to a minimum. The internal clock will shut down if the /D is not restarted after a conversion. The clock could also be shut down with an open collector driver applied to the pin. This should only be done during the sample portion (the first three clock periods) of a conversion cycle, and might be useful for using the device as a digital sample and hold. If an external clock is supplied to the pin, it must have sufficient drive to overcome the internal clock source. The external clock can be shut off, but again, only during the sample portion of a conversion cycle. t other times, it must be above the minimum frequency shown in the specifications. In the above two cases, a further restriction applies in that the clock should not be shut off during the third sample period for more than 1ms. This might cause an internal charge-pump voltage to decay. If the internal or external clock was shut off during the conversion time (clock cycles 4 through 15) of the /D, the output might be invalid due to balancing capacitor droop. n external clock must also meet the minimum t LOW and t HIGH times shown in the specifications. violation may cause an internal miscount and invalidate the results. Power Supplies and Grounding V DD and V SS are the digital supply pins: they power all internal logic and the output drivers. ecause the output drivers can cause fast current spikes in the V DD and V SS lines, V SS should have a low impedance path to digital ground and V DD should be well bypassed. Except for V +, which is a substrate connection to V DD, all pins have protection diodes connected to V DD and V SS. Input transients above V DD or below V SS will get steered to the digital supplies. The V + and V - terminals supply the charge-balancing comparator only. ecause the comparator is autobalanced between conversions, it has good low-frequency supply rejection. It does not reject well at high frequencies however; V - should be returned to a clean analog ground and V + should be R decoupled from the digital supply as shown in Figure 22. There is approximately 50Ω of substrate impedance between V DD and V +. This can be used, for example, as part of a low-pass R filter to attenuate switching supply noise. 10µF capacitor from V + to ground would attenuate 30kHz noise by approximately 40d. Note that back-to-back diodes should be placed from V DD to V + to handle supply to capacitor turn-on or turn-off current spikes. Dynamic Performance Fast Fourier Transform (FFT) techniques are used to evaluate the dynamic performance of the /D. low distortion sine wave is applied to the input of the /D converter. The input is sampled by the /D and its output stored in RM. The data is than transformed into the frequency domain with a 4096 point FFT and analyzed to evaluate the converters dynamic performance such as SNR and THD. See typical performance characteristics. Signal-To-Noise Ratio The signal to noise ratio (SNR) is the measured RMS signal to RMS sum of noise at a specified input and sampling frequency. The noise is the RMS sum of all except the fundamental and the first five harmonic signals. The SNR is dependent on the number of quantization levels used in the converter. The theoretical SNR for an N-bit converter with no differential or integral linearity error is: SNR = (6.02N ) d. For an ideal 12-bit converter the SNR is 74d. Differential and integral linearity errors will degrade SNR. INTERNL ENLE LOK SNR = 10 Log Sinewave Signal Power Total Noise Power OPTIONL EXTERNL LOK 100kΩ 18pF Signal-To-Noise + Distortion Ratio SIND is the measured RMS signal to RMS sum of noise plus harmonic power and is expressed by the following: FIGURE 21. INTERNL LOK IRUITRY SIND = 10 Log Sinewave Signal Power Noise + Harmonic Power (2nd - 6th) 12

13 Effective Number of its The effective number of bits (ENO) is derived from the SIND data; ENO = SIND Total Harmonic Distortion The total harmonic distortion (THD) is the ratio of the RMS sum of the second through sixth harmonic components to the fundamental RMS signal for a specified input and sampling frequency. Total Harmonic Power (2nd - 6th Harmonic) THD = 10 Log Sinewave Signal Power Spurious-Free Dynamic Range The spurious-free dynamic range (SFDR) is the ratio of the fundamental RMS amplitude to the RMS amplitude of the next largest spur or spectral component. If the harmonics are buried in the noise floor it is the largest peak. SFDR = 10 Log Sinewave Signal Power Highest Spurious Signal Power TLE 2. ODE TLE ODE DESRIPTION INPUT VOLTGE V REF+ = 4.608V V REF- = 0.0V (V) DEIML OUNT INRY OUTPUT ODE MS LS D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Full Scale (FS) FS - 1 LS /4 FS /2 FS /4 FS LS Zero The voltages listed above represent the ideal lower transition of each output code shown as a function of the reference voltage. +5V 0.1µF 4.7µF 10µF 0.1µF 0.01µF V + V DD V REF 4.7µF 0.1µF 0.001µF V REF+ D11. D0 DRDY OUTPUT DT OEM NLOG INPUT V IN OEL STRT 750kHz LOK V REF- V - V SS FIGURE 22. GROUND ND SUPPLY DEOUPLING 13

14 Die haracteristics DIE DIMENSIONS: 3200µm x 3940µm METLLIZTION: Type: lsi Thickness: 11kÅ ±1kÅ PSSIVTION: Type: PSG Thickness: 13kÅ ±2.5kÅ WORST SE URRENT DENSITY: 1.84 x 10 5 /cm 2 Metallization Mask Layout D1 D0 (LS) DRDY V DD OEL D2 D3 STRT V REF - D4 D5 D6 V REF + D7 V IN D8 V + V - D9 V SS D10 D11 (MS) OEM 14

15 Dual-In-Line Plastic Packages (PDIP) INDEX RE SE PLNE SETING PLNE D N N/2 D e D1 E1 NOTES: 1. ontrolling Dimensions: INH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per NSI Y14.5M Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication No Dimensions, 1 and L are measured with the package seated in JEDE seating plane gauge GS D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed inch (0.25mm). 6. E and e are measured with the leads constrained to be perpendicular to datum e and e are measured at the lead tips with the leads unconstrained. e must be zero or greater maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed inch (0.25mm). 9. N is the maximum number of terminal positions. 10. orner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a 1 dimension of inch ( mm) (0.25) M 2 L S e E L e e E24.3 (JEDE MS-001-F ISSUE D) 24 LED NRROW ODY DUL-IN-LINE PLSTI PKGE INHES MILLIMETERS SYMOL MIN MX MIN MX NOTES D D E E e S 2.54 S - e S 7.62 S 6 e L N Rev. 0 12/93 15

16 Small Outline Plastic Packages (SOI) N INDEX RE e D 0.25(0.010) M M E SETING PLNE S H (0.004) NOTES: 1. Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication Number Dimensioning and tolerancing per NSI Y14.5M Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. ontrolling dimension: MILLIMETER. onverted inch dimensions are not necessarily exact. µ 0.25(0.010) M α L M h x 45 o M24.3 (JEDE MS-013-D ISSUE ) 24 LED WIDE ODY SMLL OUTLINE PLSTI PKGE INHES MILLIMETERS SYMOL MIN MX MIN MX NOTES D E e 0.05 S 1.27 S - H h L N α 0 o 8 o 0 o 8 o - Rev. 0 12/93 ll Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil orporation s quality certifications can be viewed at Intersil products are sold by description only. Intersil orporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. ccordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil orporation and its products, see 16