Pixel readout electronics development for ALICE PIXEL VERTEX and LHCb RICH

Transcription

1 Pixel readot electronics development for ALICE PIXEL VERTEX and LHCb RICH W. Snoeys, M. Campbell, E. Cantatore, V. Cencelli*, R. Dinapoli**, E. Heijne, P. Jarron, P. Lamanna**, A. Marchioro, D. Minervini**, V. Qiqempoix, D. San Segndo Bello***, B. van Koningsveld, K. Wyllie EP Division - CERN, Geneva *Rome III INFN **INFN and Politecnico Bari ***Nikhef

2 Otline Previos fll readot chips n n Omega2 Omega3/LHC1 Two testchips n n 0.5 µm CMOS 0.25 µm CMOS New chip for ALICE pixel and LHCb RICH n n n n Chip description Design for radiation tolerance Design for testability Design for niformity Special isses Conclsions

3 Omega2 Delay line Data in C fb Threshold control crrent Inpt -A Coinc. nit D Q C test Binary position information Pixel 75x500 µm 2, 64 rows by 16 colmns Leakage crrent sensing cell at the bottom of each colmn Internal delay per pixel (crrent deprived invertors), dead for twice the trigger delay Shift register readot after level 1 trigger Limited testability : only one test row at the top Two metal layers only : no shielding between electronics and detector ~ 80 transistors/pixel (Self Aligned Contact 3 µm technology) Dies at < 50krad Test Inpt (only test row) Reset Delay control crrent Strobe Data ot

4 Omega3/LHC1 A Discriminator Pixel 50x500 µm 2, 128 rows by 16 colmns Internal delay per pixel (crrent deprived invertors), front end reset after small fraction of the trigger delay Shift register readot after level 1 trigger All pixels can be tested electrically Third metal shield ~ 380 transistors/pixel (Self Aligned Contact 1 µm technology Dies at < 50krad Discriminator (see left) trade-off between threshold niformity and speed Preamplifier feedback

5 Omega3 testability gave a wealth of information Top-down threshold variation de to resistive drop fixed in correction rn

6 3 bit delay adjst on half plane (~ channels) row row colmn Delay [ ns ] Before 96 colmn After

7 Omega2 and Omega3 worked well (CERN RD-19, WA97 and NA57) Pixel Ladders (6 chips) LHC1 : 2000 CMOS readot channels Half plane ~ sensing elements WA97 NA57 Experiment 1.2 M channels

8 Two test chips in commercial sbmicron CMOS 2 colmns of 64 pixels + 1 test pixel with analog otpts radiation tolerant layot 2 by 5 mm 2 LHC2TEST/ALICE1TEST 0.5 µm CMOS transistors fll mixed mode circit ALICE2TEST 0.25 µm CMOS transistors

9 Preamplifier Changes in front end Shaper Vref IN C fb OUT In Vbias DC level of inpt and otpt no longer copled Leakage crrent compensation ref : F. Krmmenacher, Ncl. Instr. and Meth., Vol. A305 (1991) Threshold setting Change in discriminator for speed, went to crrent comparator Iot to crrent comparator

10 0.5 µm test chip Conts (pro mille) Inpt (mv) ( thresh. ~ 2100 el.) Ileak = 1.4 na, noise ~ 180 e rms Ileak = 16 na, noise ~ 210 e rms Ileak = 100 na, noise ~ 330 e rms Leakage crrent compensation works (for both signs of leakage) Added delay (ns) Inpt charge (electrons, ncalib.) threshold = 1650 el. threshold = 2000 el. threshold = 6400 el. Timewalk LHC compatible

11 0.5 µm test chip : evoltion of Threshold and Threshold Variation with Xray Dose electrons Threshold Dose (krad) Threshold variation (rms) Spply crrents virtally naffected dring the irradiation! Circit dies arond 1 Mrad becase of transistor Vt-shifts which are still non-neglegible in 0.5 µm Confirmed for electrons, and for (cfr. F. Meddi et al.) gamma-rays and protons

12 0.5 µm test chip : conclsions 6 5 L d = 0.36 µm Threshold dispersion too large : edgeless transistor show mch larger mismatch (see left) 4 => need other front end topology σ Vth [mv] 3 2 L d = 2 µm L d = 1 µm L d = 0.5 µm Motivations to go deeper sbmicron : n Need more density n Will get even higher radiation tolerance 1 0 L d = 5 µm Need for frther modeling of edgeless transistors (Geom. Gate Area) -1/2 [1/µm] Mismatch for edgeless transistors cfr. G. Anelli et al.

13 0.25 µm testchip Inpt strctre 160 µm Test FF Front end 125 µm 420 µm Delay 60 µm 80 Mask FF + R/O 125 µm Eliminated the crrent mirror (cfr ISSCC 2000) and shrnk the front end from 260 µm to 125 µm Pt synchronos delay (one colmn static, other dynamic) in the empty space and kept other logic identical to 0.5 µm version 50 µw per pixel Noise e - rms Threshold dispersion 160 e - rms before 3 bit adjst, 25 e - rms after Used three metals only

14 0.25 µm test chip : 10 kev X-ray Irradiation Pixel Threshold, Threshold Dispersion and Noise Vs Total Dose electrons electrons dose (Mrad) dose (Mrad) average pixel threshold threshold dispersion (rms) noise (rms) Spply crrents virtally naffected dring the irradiation!

15 Proton irradiation in NA50 2mm 2mm 3.6 x protons/4mm 2 => 9 x protons/cm 2 Threshold and noise on hit colmn after proton irradiation and 4 hor room temperatre (Note: 1 mv = 100 e-)

16 Proton irradiation in NA50 Conclsions Also withstands non-niform irradiation Did not see any evidence of hard failre, i.e gate rptre... Threshold change and noise after proton irradiation and 20 hor room temperatre Note: 1 mv = 100 e-

17 Conclsions from test chips Challenges for fll chip Speed, threshold niformity and radiation tolerance (total ionizing dose and single event pset) proven Need to frther characterize enclosed devices Challenges for fll readot chip : n Architectre for two different applications n Large occpancy in LHCb, need to minimize dead time n Readot (=digital activity) while being sensitive n Large chip n Large system : testability, niformity n Design for radiation tolerance : design implications revisited

18 Two applications : pixel for tracking/vertex finding in ALICE Half Stave ladder2 ladder1 10 chips of one half-stave read ot seqentially in 400µs 120 half-staves read ot in parallel Minimal mass, thin sensors => e- most probable signal Spatial resoltion of 12µm in r-φ => 50 µm pixel pitch 1% average occpancy Level-1 trigger : latency of 5.5µs, few khz rate, bffering on chip Fll event readot in 400µs (deadtime abot 10%), 10 MHz clock Radiation tolerant to ~ 500 krad

19 And LHCb RICH : encapslation of pixel chip-sensor assembly in HYBRID PHOTON DETECTOR for particle ID Single photons yield 5000e- signal with 20kV accelerating potential 2.5mm x 2.5mm channel size, 5 x demagnification => 500µm 500µm granlarity 8% maximm occpancy 40 MHz event rate, also readot clock 1MHz average Level 0 trigger rate Bffering of Level-0 triggered events (latency of 4 µs) Readot of triggered event in 900ns (deadtime ˆ 1%)

20 New 8000 channel chip : pixel Shaper filter Comparator C in Preamp Thres. 3 delay 8 BCO coinc logic strobe 4-bit FIFO R W data FF analog test inpt test FF th adj FFs mask FF

21 Two applications : architectral soltion ALICE mode of operation

22 Two applications : LHCb mode of operation

23 FRONT END Voltage [V] differential voltage [V] Preamplifier otpt 0.0E E E E E E-07 Shaper Otpt E E E E E E Vth=20mV time [s] Differential to reject sbstrate and spply noise Closed loop complex poles for fast retrn to zero to be immne to pile-p of sbseqent signals

24 Delay : Pixel Cell : digital part n stores a hit for dration of trigger latency n latches the time-stamp of a hit from a periodic Grayencoded pattern (modlo n) on an 8-bit bs FIFO : n Read/write addressable by Gray encoded bs Risk of switching noise copling into analog circitry is redced by: n Gray encoding of patterns on bsses n Crrent starved logic cells

25 Pixel cell 125µm pre-amp (differential) shaper (differential) discriminator (+ fast-or) 60µW static consmption 265µm two digital delay nits trigger coincidence logic 4-event FIFO bffer readot logic 35µm 5 n-psettable latches for configration 6 metal layers n test inpt on/off 1500 transistors/pixel n pixel mask on/off layot for radiation n 3 bits of threshold adjst tolerance everywhere

26 Periphery and I/O Periphery contains: n Conters to generate timestamp n Conters to address FIFO bffers n 8-bit DACs to provide voltage and crrent references for analog circitry and crrent-starved logic I/O pads :Single-ended : Gnning Tranceiver Logic (GTL) n Low swing n Slew rate control Separate spply for otpt bffers Mltiple bonding pads for spply lines to redce indctance and limit on-chip power spply bonce dring switching

27 Design for testability Configration of peripheral logic and pixel cells by means of JTAG serial interface - n allows both write and read of configration settings (test,mask.) n n reading back of analog levels (crrents & voltages) generated by DACs connectivity tests of chips on stave sing bondary scan allows detection of bad chips on stave Every pixel can be addressed individally for testing sing analog inpt

28 Single event effects : Very important fine print n Single event indced latch-p : radiation tolerant layot very effective also here n Single event pset : special SEU hardened flipflops Power distribtion and voltage drops : n Motivation for (late) decision to switch from 5 to 6 metal layers n Local mirroring of sensitive biases to redce sensitivity to on-chip resistive drops Digital to analog cross-talk : n Slew rate control on all digital n Differential frontend

29 Conclsions Experience from omega2 and omega3/lhc1, and from the two test chips Commercial deep sbmicron CMOS allows : n High component density n Radiation tolerance n Good speed-power performance Fll scale pixel readot chip designed n One chip for Alice pixel vertex and LHCb RICH n 8000 readot channels n 13 M transistors in 14 by 16 mm 2 n 6 metals n Testability and system integration n Uniformity n Important fine print

30 Conclsions Basic bilding block in fll readot chip : 8 pixels/ transistors in 400 by 425 µm 2