A Low Power Capacitive Interface IC with Automatic Parasitic Offset Calibration using Dual-Range Digital Servo Loop

Transcription

1 IDE Jornal of Integrated ircits and Systems, VOL 02, No.1, pril 2016 Low Power apacitive Interface I with tomatic Parasitic Offset alibration sing Dal-Range Digital Servo Loop Yeongjin Mn, Ynjong Park, Hyngsep Kim, Yongwoon Ko and Hyongho Ko a Department of Electronics, hngnam National University, Daejeon 34134, Repblic of Korea hhko@cn.ac.kr bstract - apacitive sensor interfaces are widely sed for varios micro-electro mechanical system (MEMS), however, capacitive sensor interface circits sffer from severe parasitic capacitance problems. The parasitic capacitance, which is generally mch larger than the sensing capacitance, reslts the large otpt offset variations. Ths an additional parasitic cancellation with external calibration eqipment is reqired. This paper presents a low power capacitive interface I with atomatic parasitic calibration sing dal-range digital servo loop for capacitive micro sensors withot external eqipment. The otpt offset with few hndreds ff parasitic capacitance of the capacitive sensor interface mst be canceled to measre ff capacitance. To overcome the limitations of design rle and perform the wide compensation range, this paper proposed capacitor domain compensation (coarse range compensation) and charge domain compensation (fine range compensation). The chip is implemented sing 0.18 μm complementary metaloxide-semicondctor (MOS) process. The inpt parasitic capacitances in the range from pf to pf can be cancelled ot atomatically, and the reqired calibration time is lower than 6 ms. I. INTRODUTION Varios MEMS technologies, inclding accelerometers, gyroscopes, pressre sensors, toch-screen sensors, and so on, are designed sing capacitive sensor interfaces [1-2]. ecase the MEMS capacitive sensors are sensitive and have small size, the MEMS capacitive sensor interfaces reqire low offset, low noise, low power consmption and small active area. The capacitive sensing interfaces, however, reslt the large otpt offset variations de to mismatch problems with severe parasitic capacitances. The parasitic capacitances on the order of several hndreds of femtofarads to several picofarads are often mch higher than sensing capacitance charges on the order of several tens of femtofarads. Therefore, additional offset calibration is needed to compensate the parasitic capacitance mismatch in capacitive sensing I. n offset elimination is one of the most important problems in capacitive sensor interface I. Some papers on calibration process have been reported for minimizing the parasitic capacitance. The dal compensation loop consisting of capacitor domain compensation (coarse range compensation) and charge domain compensation (fine range compensation) is proposed for capacitive MEMS sensors. Since the otpt of the MEMS capacitive sensors is very small signal [2-4], the detected signal of MEMS sensors is necessary to remove the low-freqency noise and amplifier with high gain. For this prpose, the capacitive sensing chain with DS (correlated doble sampling) is sed to redce the flicker noise and the common mode interference. To achieve the low power consmption and small active area, this paper presents new one way capacitor array in capacitive sensor interface. ontrary to the conventional sensor interface, the proposed capacitor arrays have abot half active area and power consmption decreased by sing the new one way capacitor array architectre. This paper presents a low power capacitive interface I with atomatic parasitic calibration sing dal-range digital servo loop. To achieve both the high resoltion sb-ff capacitive calibration below physical design rles and the wide compensation range, capacitor domain compensation (coarse range compensation) and charge domain compensation (fine range compensation) are proposed. The previos capacitive Is adopt manal capacitive calibration with coarse resoltion. The presented capacitive interface I with dal range digital servo loop can perform atomatic parasitic cancellation and offset tracking. The proposed circit can atomatically compensate the offset variation, and additional calibration steps can be progressed withot external test eqipment.. ircit description II. EXPERIMENTS a. orresponding athor; hhko@cn.ac.kr opyright 2016 IDE ll rights reserved. This is an Open-ccess article distribted nder the terms of the reative ommo ns ttribtion Non-ommercial License ( 3.0) which permits nrestricted non-commercial se, distribtion, and reprodction in any medim, provided the original work is properly cited. 53

2 IDE Jornal of Integrated ircits and Systems, VOL 02, No.1, pril 2016 Oscillator Timing generator I/ erence Proposed capacitive sensing I o + Δ DOUT < 9 : 0 > apacitive sensing chain p 1? 7 LPF o - Δ p 2 DOUT < 9 : 0 > off _? 7? 7 LPF 12 bit D _ DOUT <9:0> Dal -Range Digital servo Loop Fig. 1. The block diagram of the proposed capacitive sensing circit with dal-range digital servo loop. Fig. 1 illstrates the overall architectre of the proposed capacitive interface I. The capacitive sensing chain adopts the correlated doble sampling (DS) techniqe to redce the low freqency noise, inclding the 1/f noise [5-6]. The capacitive sensing chain is composed of three amplification stages. In the first amplification stage, capacitive sensing amplifier (S) converts the inpt capacitance charge to otpt voltage. Second amplification stage, the programmable gain amplifier (PG), amplifies the otpt signal of S stage from 0 d to 30 d by sing 6 bit gain registers. The amplified signal of the PG otpt is compensated by the dal-range digital servo loop. Single to differential amplifier (SD) of third stage converts the single-ended otpt signal of the PG into the differential signal [7]. The otpt differential signals are converted to digital signals sing the 12-bit sccessive approximation register (SR) analog to digital converter (D) throgh low pass filters and bffers [8]. Dal-range digital servo loop adjsts the otpt offset to the desired vale sing binary search algorithm, and is implemented sing a comparator, SR logic, R-2R D, charge transfer switches, a charge-storing capacitor and switching cap D with 10-bit code.. apacitive sensing chain Φ 2 Φ 1 MEMS parasitic Sensor capacitance o+δ o+δ p p Fig. 2. apacitive sensing amplifier (S): onventional capacitor arrays calibration. V noise f Φ 2 Φ 1 Φ 2 MEMS Sensor o+δ o-δ parasitic capacitance p1 p2 <9:0> off _ Φcal LK 10bit R2R D alibration start 10bit to offset logic Digital inpt from fine calibration Digital inpt from coarse calibration Fig. 3. apacitor arrays with proposed charge-domain calibration. Fig. 2 and Fig. 3 show the S with offset calibration sing conventional capacitor arrays and proposed chargedomain fine calibration [1]. inary-weighted capacitor arrays are sed to cancel the inpt parasitic capacitance in the conventional S. ecase of the minimm design rles of capacitors, the resoltion of conventional offset calibration scheme sing inary-weighted capacitor arrays is limited. For example, in this process, the minimm capacitance of the metal-inslator-metal (MIM) capacitor is 20.8 ff ( 4 μm 4 μm 1.3 ff/μm2 ). The conventional offset calibration scheme cannot proceed calibration nder the 20.8 ff. lso, the otpt amplification stage to obtain highly gain has large offset. To achieve the high otpt offset accracy and the high capacitance-to-voltage conversion gain, the fine offset calibrations with sb-ff steps are highly desired. To implement the calibration capacitance smaller than physical design rle, the coarse calibration and the charge-domain fine calibration scheme are designed, as show in Fig. 3. The comparisons between the conventional capacitor array calibration scheme and the charge-domain calibration scheme are smmarized in Table 1. The coarse calibration with code can cancel the inpt parasitic capacitance in the range from pf to 10.6 pf sing one way binary-weighted capacitor arrays. This charge-domain calibration consists of switching cap D and control logic 54

3 IDE Jornal of Integrated ircits and Systems, VOL 02, No.1, pril 2016 adopting 10-bit sccessive approximation register (SR). fter the coarse calibration process, the fine calibration loop is progressed. apacitor implementation Minimm capacitor Size TLE I. omparisons between capacitor arrays calibration and charge-domain calibration. apacitor arrays calibration Physical capacitor (MIM or PIP) Limited by physical design rles (in this design, 20.8 ff = 4 μm 4 μm 1.3 ff/μm 2 ) Large (binary-weighted capacitor array) D crrent 0 harge-domain calibration Electrically eqivalent capacitor LS voltage*off/ (in this design, ff = 1/1024*3.3/3.3*230 ff) Small (R-2R D, switches, and a charge- storing capacitor) D crrent consmption in R-2R D (1.2 μ in this design) The otpt voltage sing charge-domain calibration (Vo) and charge-domain eqivalent capacitance (eq) can be expressed as (1). V O V (2 ) ) DD p1 p 2 eq V eq ( V V ) ref D V f DD In this scheme, the charge storing capacitor, off, is abot 200 ff, and the 10-bit R-2R D generates voltage from to in 1024 steps. Therefore, the fine calibration loop can generate an electrically eqivalent offset capacitance in the range from -110 ff to 110 ff with resoltion of ff. off ref (1) f2, as expressed in (3). The otpt signal from the SD is sampled on Φ7 phase. V V V f 1 PG ref in1 (2) in1 V V V f 2 2 S 2D ref in 2 (3). Dal range digital servo loop The proposed dal-range digital servo loop is illstrated in Fig. 5. The otpt voltage of PG is sampled in phase. In the 10-bit binary search sccessive approximation register (SR) logic, actation signal Φcal and calibration start signal is needed for calibration logic start. The shift registers (D-flip-flops) in the first row seqentially point towards the registers in the second row, which pdate the data to the comparator otpt. <9:0> R2R D off a o+δ o-δ to alibration logic 10bit DOUT<0> DOUT<9> R S D S D R LK to alibration logic 10bit DOUT<0> DOUT<9> in 2 apacitive sensing chain b S PG SD Fine calibration start oarse calibration start OMP LK OMP LK Fig. 5. The proposed dal-range digital servo loop. LK Φ8 Φ8 Φ8 Φcoarse Φfine Vin1 in1 f1 _ in2 f2 Φ pf 10 pf If the inpt capacitance offset is 10 pf oarse calibration operation example in2 f2 Φ7 to LPF apacitance offset 10.6 pf 5 pf 2.5 pf 1.2 pf Steps Fig. 4. Programmable Gain mplifier (PG) and Single to Differential mplifier (SD) circit pf +110 ff Fine calibration operation example Fig. 4 shows the PG and SD circit. The PG and SD employ correlated doble sampling techniqe to redce the low-noise components. The and are nonoverlapping clocks. In PG, an inpt copling capacitor (in1) stores the inpt voltage signal and noise in phase, and the stored charge is dmped in a feedback capacitor in phase. The gain of PG can be adjsted from 0 d to 30 d by programming f1, as expressed in (2). SD works with the opposite phase of PG, and the differential gain of SD can be adjsted from 0 d to 36 d by programming apacitance offset 21 ff -110 ff off 2 =110 ff off 4 off 8 Fig. 6. Operation example of dal-range digital servo loop. off Steps 55

4 U 2U 4U 8U 16U 32U U 2U 4U 8U 16U 32U bridge bridge U 2U 4U 8U 16U 32U U 2U 4U 8U 16U 32U IDE Jornal of Integrated ircits and Systems, VOL 02, No.1, pril Dal ato calibration is in progress oarse Fine Sinsoidal capacitive change is applied , 2, 2, , 2, 2, (4) Otpt Voltage (V) Desired offset Time (ms) Fig. 7. Simlation reslt of the proposed circit. n operation example of dal-range digital servo loop is shown in Fig. 6. The operation principles of the circit are as follows. If the inpt offset capacitance is 10pF, the sampled voltage and are compared in the comparator. Initial vale of is set to The PG otpt voltage is compared to in Φ 4 phase. If otpt voltage of PG is lower than, the MS of is replaced with L. If otpt voltage of PG is higher than, the MS of is maintained in H. The analog otpt of R-2R D is determined by. The R-2R D generates an electrically matched offset capacitance. Sbseqently, the next lower bit of becomes H, and becomes X , where X means the reslts of the previos step. The PG otpt voltage is compared to, and the second bit of is decided by comparator otpt. For ten cycles, otpt voltage of PG is calibrated to, as shown in Fig. 7. The conventional 12-bits capacitive D is reqired for 2 12 mltiple of nit capacitor. To acqire ideal linearity in split capacitive D, the total capacitance of LS side inclding bridge capacitance ( bridge) shold be exactly matched with nit capacitance. The size of bridge capacitor is as follows in (5) x 64 64x 1 x 64 64x x x 63 ( x ) bridge The nit capacitor mst be larger than kt / noise and satisfies as expressed (6) n k T ff V fllscale y the (4), is determined to be larger than ff and has 250 ff in this circit. 2 (5) (6) LS side MS side VREFL VREFH III. RESULTS ND DISUSSION D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 VN VP + SR OMP - LOGI D0 ~ D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 VREFH LK_In VREFL Fig. 8. Implemented sccessive approximation register (SR) D circit. 12-bits sccessive approximation register (SR) D circit is shown in Fig. 8. The SR D consists of D, comparator, and SR logic to control the D. When the start of conversion signal is applied on the SR logic, flly differential analog signal is stored in both capacitive D and otpt of the comparator is seqentially pdated to DOUT<11:0> of the SR logic. The pdated DOUT<11:0> of the SR logic controls the capacitive D to track the analog signal. The D adopts a split capacitive array D to redce the capacitive array area. lthogh the split capacitive array D has a mismatched problem de to MOS fabrication variations of bridge capacitor, the sing D area is smaller than a thirtieth of conventional D array area, and the size of capacitors is as expressed in (4). Fig. 9. The micrograph of the proposed capacitive sensing. die photograph of the fabricated capacitive sensing I is shown in Fig. 9. The I is fabricated sing a 0.18 μm single-polysilicon six-metal complementary metal-oxidesemicondctor (MOS) process with an active area of 1.76 mm 2. 56

5 IDE Jornal of Integrated ircits and Systems, VOL 02, No.1, pril 2016 Fig. 10 shows the measred analog otpt waveform with the dal-range digital servo loop operation. The yellow line and ble line show the differential otpt of the low pass filter. The green line is enable signal of dal-range digital servo loop, and the dal-range digital servo loop is activated at the falling edge of enable signal. fter the operation of dal-range digital servo loop, the initial offset is removed atomatically. The reqired calibration time is lower than 6 ms with 1 khz calibration clock. ecase the dal-range digital servo loop is operated before the low pass filter, the calibration clock for dal-range digital servo loop can be faster than ct-off freqency of the low pass filter. The freqency of calibration clock and ct-off freqency of the low pass filter are also programmable. The defalt ct-off freqency of the low pass filter is abot 200 Hz. To evalate the performance of the fabricated I, the I and MEMS Z-axis capacitive accelerometer are rotated on 360 degree, as shown in Fig. 11. The detailed design and specification of the Z-axis accelerometer is described in [9]. Fig. 12. Otpt noise Measrement reslts Fig. 10. The measred analog otpt waveform with dal-range digital servo loop operation. Fig. 13. MEMS Z-axis accelerometer inpt-otpt characteristics. IV. ONLUSIONS Fig. 11. The measrement setp with capacitive accelerometer. The measrement reslts of the otpt noise are presented in Fig. 12. The inpt referred capacitance noise density, and integrated noise with 200 Hz bandwidth are 1.71 af/ Hz and 24.2 af RMS, respectively. The inpt-otpt characteristics with MEMS Z-axis accelerometer are presented in Fig. 13. The scale factor, inpt range and, nonlinearity are V/g, ±7.5 g, and 0.81 %FSO, respectively. low power capacitive interface I with atomatic parasitic calibration sing dal-range digital servo loop has been presented. The otpt offsets of the capacitive sensing chain de to the parasitic capacitances and process variations were atomatically removed sing the dal-range digital servo loop. The dal-range digital servo loop cancels offset variation by binary-search algorithm based on 10-bit SR logic and charge-domain calibration circits. The chip was implemented sing 0.18 μm 1P6M MOS process with an active area of 2.39 mm 2. The simlation reslts of the proposed I are as follows. The power consmption was 756 μw with 3.3 V spply. With the dal mode parasitic cancellation loop, the inpt parasitic capacitance in the range from pf to 10.6 pf can be cancelled with the resoltion of ff. The reqired calibration time is lower than 6 ms. The inpt referred capacitance noise density and integrated noise with 200 Hz bandwidth were 1.71 af/ Hz and 24.2 af RMS, respectively. KNOWLEDGMENT This work was spported by I Design Edcation enter (IDE) and IDE platform center (IP). 57

6 IDE Jornal of Integrated ircits and Systems, VOL 02, No.1, pril 2016 REFERENES [1] Oh, H.K.; hoi, J.; Lee, J.; Han, S.; Kim, S.; Seo, J.; Ko, H. apacitive Readot ircit for Tri-axes Microaccelerometer with Sb-fF Offset alibration. J. Semicond. Tech. Sci. 2014, 14, [2] Tez, S.; kin, T. Fabrication of a Sandwich Type Three xis apacitive MEMS ccelerometer. IEEE Sensors, altimore, MD, US, 3 6 November 2013; pp [3]. Y, H.Y.; in, M.; Hang, J..; Hang,.. MEMS apacitive Pressre Sensor ompatible with MOS Process. In Proceedings of the IEEE Sensors, Taipei, Taiwan, October 2012; pp [4]. Dobrzynska, J..; Gijs, M..M. Polymer-based flexible capacitive sensor for three-axial force measrements. J. Micromech. Microeng. 2013, 23, [5] L. altonen and K.. I. Halonen, Psedo-continostime readot circit for a 300 /s capacitive 2-axis micro-gyroscope. IEEE J. Solid-State ircits, vol. 44, no. 12, pp , Dec [6] S. S. Tan,. Y. Li, L. K. Yeh, Y. H. hi, M. S.-. L, and K. Y. J. Hs. n integrated low-noise sensing circit with efficient bias stabilization for MOS MEMS capacitive accelerometers. IEEE Trans. ircits Syst. I, Reg. Papers, vol. 58, no. 11, pp , Nov [7] Meng Zhao. low-noise switched-capacitor interface for a capacitive micro-accelerometer. ircits and Systems (ISS), 2015 IEEE International Symposim on, pp , May [8] Wong, S.; hio, U.; Zh, Y.; Sin, S.; Seng-Pan, U.; Martins, R. 2.3 mw 10-bit 170 MS/s two-step binary-search assisted time-interleaved SR D. IEEE J. Solid-State irc. 2013, 48, [9] Lee, S.; Ko, H.; hoi,.; ho, D. Optimal and robst design method for tow-chip ot-of-plane microaccelerometers. MDPI Sensors 2010, 10, Yeongjin Mn received the.s. degree in department of Electronics from hngnam National University, Daejeon, Korea, in rrently, he is prsing the M.S. degree in the Department of Electronics from hngnam National University, Daejeon, Korea. His research interests inclde design of MOS analog integrated circits. Ynjong Park received the.s. degree in department of Electronics from hngnam National University, Daejeon, Korea, in rrently, he is prsing the M.S. degree in the Department of Electronics from hngnam National University, Daejeon, Korea. His research interests inclde design of MOS analog integrated circits. Hyngsep Kim received the.s. degree in department of Electronics from hngnam National University, Daejeon, Korea, in rrently, he is prsing the M.S. degree in the Department of Electronics from hngnam National University, Daejeon, Korea. His research interests inclde design of MOS analog integrated circits. Yongwoon Ko received the.s. degree in department of Electronics from hngnam National University, Daejeon, Korea, in rrently, he is prsing the M.S. degree in the Department of Electronics from hngnam National University, Daejeon, Korea. His research interests inclde design of MOS analog integrated circits. Hyongho Ko received his S and Ph. D. degrees in the School of Electrical Engineering from Seol National University, Korea, in 2003 and 2008, respectively. He was with Samsng Electronics as a senior engineer from 2008 to In 2010, he joined the Department of Electronics, hngnam National University, Daejeon, Korea, where he is crrently assistant professor. His interests inclde MOS analog integrated circit design. 58