Test-Chip Structures for Local Random Variability Characterization in CMOS 65 nm

Transcription

1 SIM th South Symposium on Microelectronics 209 Test-Chip Structures for Local Random Variability Characterization in CMOS 65 nm 1 Felipe Correa Werle, 2 Juan Pablo Martinez Brito, 1,2 Sergio Bampi { fcwerle, juan, bampi}@inf.ufrgs.br 1 GME, Microelectronics Group Informatics Institute 2 PGMICRO, Graduate Program on Microelectronics UFRGS, Federal University of Rio Grande do Sul Abstract This paper describes the design of a 65nm technology test chip, aimed at investigating and characterizing the truly local random variations. The first structure is a matrix-style transistor array with closely spaced MOS transistors. The second structure comprises three arrays of ring oscillators with different numbers of stages and other two arrays of ring oscillators composed solely by single-type transistors. The third structure is based on a procedure to measure an array of stacked-pairs of identical MOS transistors. The design is done in 65nm CMOS bulk technology and the final chip area is 1580 x 1580 µm. 1. INTRODUCTION Process variations impose a very important challenge to future nano-scaling of VLSI technology below 32nm. For the past several years, variation in CMOS process has been a concern in the design, manufacture and accurate operation of integrated circuits. Nowadays, intradie variations (further discussion on the differences between interdie and intradie variation are in [1]) are considered as one of the limiting factors for further CMOS scaling [2] and certainly a drawback to the continuing Moore s law [3] scaling. Intradie fluctuations [4] originate mainly from the fluctuation of dopants in the channel region, which is determined by a stochastic energetic ion implantation process [5]. That is, this type of characteristics fluctuation cannot be eliminated in principle. Mismatch differences among MOSFETs are of utmost concern, since the fluctuation of their characteristics becomes significant as their physical size decreases. Therefore, to model and characterize these variations, highly accurate measurement data on local variability are needed to feed and verify transistor mismatch models [6, 7] with realistic statistical data. Thus, one of the most serious challenges in process variations for sub-100- nm technologies is the effective and reliable way to obtain statistical data from FETs within a reasonable time. To obtain meaningful variation data, special care must be taken concerning the test structure and measurement setup. Due to its statistical random nature, the local random variation effect must be characterized by measuring a large number of individual devices closely placed. A basic approach to obtain statistical data from a given process is to use arrays of identical transistors [8, 9]. Transistor arrays unavoidably occupy a large area and require sequentially long measurements, reducing the measurement throughput. Nevertheless, the attractiveness of transistor arrays as test structures has led to recent efforts [10] that aim to come up with new ways to create optimized structures for fast and semi-automatic measurement procedures. This structure relies on a multiplexed transistor array with high-density access to multiple devices by means of address decoding and access circuits comprised of CMOS transmission gates. An alternative to the first class of measurements is to convert an analog signal to a more robust measurable quantity. Doing so simplifies the requirements for the test equipment and environment. Frequency measurements using on-chip circuitry can help with signal-to-noise and bandwidth problems and provide a minimally invasive probing strategy. Ring oscillator-based approaches [11] are effective for test time and are good general-purpose indicators of process variations on digital performance. However, they typically cannot help to predict unique device variation because they tend to indicate the mean parameter strength from its frequency value. A more recent technique for variability measurement is to use a common gate series-connected MOSFET structure [12-14] suitable for process monitoring purposes. In this structure the mismatch behavior of a large number of MOSFETs pairs is promptly evaluated in a small area using simple voltage measurements. In this paper we propose a test chip designed with new structures for local random variability measurements. Design, simulation and variance simulations using Monte-Carlo were done for a 65 nm CMOS bulk process. The designed test chip has the following structures:

2 210 SIM th South Symposium on Microelectronics 1) A MOSFET matrix-style array composed of multiplexed/biased closely spaced identical MOS transistors. 2) An array of a new type of ring oscillator composed solely by single-type transistor called: NMOS-only [or PMOS-Only] ring oscillator. 3) An array of MOSFET stacked-pairs in which their gates are internally connected. 4) An array of MOSFET stacked-pairs in which the gates are externally connected, providing the possibility to evaluate layout/distance mismatch. 2. A MOSFET MATRIX The purpose of this structure is to evaluate the transistor mismatch in the traditional way (data analysis of current-voltage curves). Based on [9], Fig. 1 shows the entire diagram of the test structure. The MOSFET matrix includes: bias circuitry, level shifters and address decoding. Fig. 1 - Entire MOSFET Matrix Test Structure The transistors are arranged in individually addressable cells. The matrix contains a total of 1024 devices (512 NMOS and 512 PMOS) placed in 64 columns with 16 rows. Ten groups of ten different size transistors compose the MOSFET matrix. Table 1 summarizes the transistor sizes (60nm is the minimum channel length): Tab. 1 - Transistor Sizes # L [nm] W [nm] All transistor drains on each column are connected together. All gates and sources on each row are connected together. Figure 2 draws the connection to each Device Under Test (DUT) within the matrix. Using a row/column address decoder, only one transistor is selected. The other terminals of the nonselected transistors are clamped to respective (N-Fet or P-Fet) clamp voltages into the accumulation mode. The transmission gates connection to each DUT, the force/sense lines, and the DUT selection procedure are shown in Fig. 3.

3 SIM th South Symposium on Microelectronics 211 Fig. 2 - Transistor Connections. Fig. 3 - DUT Connection Transmission gates are composed by thick oxide transistors (I/O transistors 2.5V) to drive current of the selected device to the I/O pin. The transmission gate lies in series between the drain and the source terminal of the DUT, causing a difference between the applied pin voltage ( external voltage) and the real bias voltage applied to the device. To minimize the effects of these IR drops, a Kelvin measurement technique is used. This technique increases the pin count because a Sense pin is needed. The entire layout of this structure including the PMOS and NMOS MOSFET Matrix, the bias circuitry, level shifters, address decoding and routing is about 330 x 280 µm 2 as shown in figure 4: Fig. 4 - MOSFET Matrix Layout 3. RING OSCILATOR The frequency of a traditional CMOS ring oscillator (RO) is typically sensitive to many process parameters, e.g., transistor gate length and width, threshold voltage, oxide thickness, etc. For equally designed ROs (that is, same number of stages and same W and L for the inverters), the respective difference on the measured output frequency is related to process variations [11]. In our test chip, we designed three different CMOS ring oscillators with 67, 101 and 151 stages that are planned to achieve (with full supply power. 1.2V) MHz, MHz and MHz respectively. To control and avoid interferences in our measurement the last stage of each ring oscillator is controlled by a Tristate inverter, thus only one oscillator oscillates at time. By now one group of oscillator was measured in a temporary test platform. The definitive setup is being planned. The measurement was made in appropriated voltage range to show variations between the oscillators. Tab. 2 Voltage and frequency of oscillation. VDD OSC 67 Mean Freq. Variation khz 15% khz 14.6% khz 14.8% MHz 13.3% In our test chip, we designed a novel ring oscillator whose frequency is maximally sensitive to variations in a single type of transistors and minimally sensitive to other variation sources. For this, we introduced the use of NMOS-Only (or PMOS-Only) ring oscillators [15], with the inverter as an enhancement load/enhancement driver configuration. Figure 5 has an example of a three (3) stage NMOS-Only Ring Oscillator:

4 212 SIM th South Symposium on Microelectronics Fig. 5 - Three (3) stages NMOS-Only Ring Oscillator Usually, the variation in transistor threshold voltage is the strongest contributor to the measured fluctuations in the frequency of ring oscillators. Since this type of ring oscillator contains only NMOS or PMOS transistors, the output frequency variation will be only dependent respectively on NMOS or PMOS threshold voltage variation. In 65 nm technology, this circuit consists of a pull-up device (M2) that must be sized considerably more resistive than the pull-down device (M1). Consequently, for this circuit the sizes shown in Table 3 for M1 and M2 were chosen: Tab. 3 - transistor size M1 M2 W [ nm ] L W 1 =20000 W 2 =200 L 1 =100 L 2 =10000 The oscillation frequency of this type of RO is typically low (~20MHz), due to the large load and large size transistors. In Fig. 6, an example of the output waveform from the output inverter nodes for an asymmetric supply, e. g. VDD=1V e VSS=-0.2V: Fig. 6 - Output of a 3 stage RO extracted simulation Fig. 7 - Ring Oscillators layout The entire test structure includes 320 (5 x 64) Ring Oscillators of which: 64 NMOS-Only 3 stage ring oscillators, 64 PMOS-Only 3 stage ring oscillators, 64 CMOS 67-stage ring oscillators, 64 CMOS 101-stage ring oscillators, 64 CMOS 151-stage ring oscillators. Each group of oscillators has its individual supply pin. The layout of this structure including all types of ring oscillators and appropriate buffering measures 200 x 480 µm 2 as shown in Fig TEST CHIP OVERVIEW The design size of this test-chip (Fig. 8) is 1.58 mm x 1.58 mm (with pads, without scribe lines), or 1mm x 1mm core size, under 65 nm CMOS design rules. An array of 44 Pads for packaging is needed to access the internal test structures previously described.

5 SIM th South Symposium on Microelectronics 213 Fig. 8 - Complete layout of the test chip and photography of the chip Tab. 4 - Shows the area of all blocks included in the test chip, including the pads (which were obtained from the foundry library): Circuit Area [µm x µm] MOSFET Matrix 330 x 280 Ring Oscillator 200 x 480 Stacked-Pair Matrix version x 320 Stacked-Pair Matrix version x 155 µprobe Test Structures 2 x (930 x 280) 5. CONCLUSIONS The test structures that we developed for the local random variations characterization are composed of transistor arrays of identical size MOSFETs, ring oscillators and stacked-pair transistors. The simulations were done to verify the sensitivity of each structure to random local variations. Electrical measurements are indispensable for the complete validation of the test structures proposed in this chip. The measurements in our test vehicle are multiplexed for thousands of test transistors and pairs, using only 44 pads. The first measurements show variations between the frequency of ring oscillator with the same number of stages and same power supply. Currently the test platform and setup is being developed to allow an automatic measurement of all structures that are implemented on the chip.

6 214 SIM th South Symposium on Microelectronics 6. REFERENCES [1] Gary S. May,Costas J. Spanos. Fundamentals of semiconductor manufacturing and process control. John Wiley & Sons, Inc [2] Wilson R.; The dirty little secret: Engineers at design forum vexed by rise in process variations at the die level, EE Times, p. 1, Mar. 25, Web: [3] Kuhn, K. et al. Managing Process Variation in Intel s 45nm CMOS Technology. Intel Technology Journal, [S.l.], [4] S. Springer et al., Modeling of Variation in Submicrometer CMOS ULSI Technologies, IEEE Transactions on Electron Devices, vol. 53, Issue 9, pp , September [5] Asenov, A.; Brown, A.R.; Davies, J.H.; Kaya, S.; Slavcheva, G., "Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs," Electron Devices, IEEE Transactions on, vol.50, no.9, pp , Sept [6] Galup-Montoro, C.; Schneider, M.C.; Klimach, H.; Arnaud, A., "A compact model of MOSFET mismatch for circuit design," Solid-State Circuits, IEEE Journal of, vol.40, no.8, pp , Aug [7] Chung-Hsun Lin; Dunga, M.V.; Darsen Lu; Niknejad, A.M.; Chenming Hu, "Statistical Compact Modeling of Variations in Nano MOSFETs," VLSI Technology, Systems and Applications, VLSI-TSA International Symposium on, vol., no., pp , April [8] Wang, V.; Shepard, K.L., "On-chip transistor characterization arrays for variability analysis," Electronics Letters, vol.43, no.15, pp , July [9] Agarwal, K.; Liu, F.; McDowell, C.; Nassif, S.; Nowka, K.; Palmer, M.; Acharyya, D.; Plusquellic, J., "A Test Structure for Characterizing Local Device Mismatches," VLSI Circuits, Digest of Technical Papers Symposium on, vol., no., pp.67-68, [10] Agarwal, K.; Hayes, J.; Nassif, S., "Fast Characterization of Threshold Voltage Fluctuation in MOS Devices," Semiconductor Manufacturing, IEEE Transactions on, vol.21, no.4, pp , Nov [11] Bhushan, M.; Ketchen, M.B.; Polonsky, S.; Gattiker, A., "Ring oscillator based technique for measuring variability statistics," Microelectronic Test Structures, ICMTS IEEE International Conference on, vol., no., pp , 6-9 March [12] Rahul Rao; Jenkins, K.A.; Jae-Joon Kim, "A Completely Digital On-Chip Circuit for Local-Random- Variability Measurement," Solid-State Circuits Conference, ISSCC Digest of Technical Papers. IEEE International, vol., no., pp , 3-7 Feb [13] Wils, N.; Tuinhout, H.P.; Meijer, M., "Characterization of STI Edge Effects on CMOS Variability," Semiconductor Manufacturing, IEEE Transactions on, vol.22, no.1, pp.59-65, Feb [14] Test Circuit for Evaluating Characteristics Mismatch in Metal Oxide Semiconductor Field-Effect Transistor Pairs by Estimating Conductance Variation through Voltage Measurement Mamoru Terauchi and Kazuo Terada Jpn. J. Appl. Phys. 47 (2008) Gonzalez, Christopher J. (Shelburne, VT, US), Ramadurai, Vinod (Burlington, VT, US), Rohrer, Norman J. (Underhill, VT, US) 2008 Circuit and method to measure threshold voltage distributions in SRAM devices United States International Business Machines Corpo