SMPS MOSFET. V DSS R DS(on) max I D

Transcription

1 PD A SMPS MOSFET IRFR3N5DPbF IRFU3N5DPbF HEXFET Power MOSFET Appications High frequency DC-DC converters Lead-Free V DSS R DS(on) max I D 50V 8Ω 4A Benefits Low Gate-to-Drain Charge to Reduce Switching Losses Fuy Characterized Capacitance Incuding Effective C OSS to Simpify Design, (See App. Note AN0) Fuy Characterized Avaanche Votage and Current D-Pak IRFR3N5D I-Pak IRFU3N5D Absoute Maximum Ratings Parameter Max. Units I T C = 25 C Continuous Drain Current, V V 4 I T C = 0 C Continuous Drain Current, V V 9.8 A I DM Pused Drain Current 56 P C = 25 C Power Dissipation 86 W Linear Derating Factor 0.57 W/ C V GS Gate-to-Source Votage ± 30 V dv/dt Peak Diode Recovery dv/dt ƒ 3.8 V/ns T J Operating Junction and -55 to 75 T STG Storage Temperature Range Sodering Temperature, for seconds 300 (.6mm from case ) C Typica SMPS Topoogies Teecom 48V input Active Camp Forward Converter Notes through are on page 2/9/04

2 T J = 25 C (uness otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Votage 50 V V GS = 0V, I D = 250µA V (BR)DSS / T J Breakdown Votage Temp. Coefficient 7 V/ C Reference to 25 C, I D = ma R DS(on) Static Drain-to-Source On-Resistance 8 Ω V GS = V, I D = 8.3A V GS(th) Gate Threshod Votage V V DS = V GS, I D = 250µA I DSS Drain-to-Source Leakage Current 25 V µa DS = 50V, V GS = 0V 250 V DS = 20V, V GS = 0V, T J = 50 C I GSS Gate-to-Source Forward Leakage 0 V GS = 30V na Gate-to-Source Reverse Leakage -0 V GS = -30V T J = 25 C (uness otherwise specified) Parameter Min. Typ. Max. Units Conditions g fs Forward Transconductance 5.0 S V DS = 50V, I D = 8.3A Q g Tota Gate Charge 9 29 I D = 8.3A Q gs Gate-to-Source Charge nc V DS = 20V Q gd Gate-to-Drain ("Mier") Charge V GS = V, t d(on) Turn-On Deay Time 8.0 V DD = 75V t r Rise Time 26 ns I D = 8.3A t d(off) Turn-Off Deay Time 2 R G = Ω t f Fa Time V GS = V C iss Input Capacitance 620 V GS = 0V C oss Output Capacitance 30 V DS = 25V C rss Reverse Transfer Capacitance 38 pf ƒ =.0MHz C oss Output Capacitance 780 V GS = 0V, V DS =.0V, ƒ =.0MHz C oss Output Capacitance 62 V GS = 0V, V DS = 20V, ƒ =.0MHz C oss eff. Effective Output Capacitance V GS = 0V, V DS = 0V to 20V Avaanche Characteristics Parameter Typ. Max. Units E AS Singe Puse Avaanche Energy 30 mj I AR Avaanche Current 8.3 A E AR Repetitive Avaanche Energy 8.6 mj Therma Resistance Parameter Typ. Max. Units R θjc Junction-to-Case.75 R θja Junction-to-Ambient (PCB mount)* 50 C/W R θja Junction-to-Ambient Diode Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbo 4 (Body Diode) showing the A G I SM Pused Source Current integra reverse 56 (Body Diode) p-n junction diode. S V SD Diode Forward Votage.3 V T J = 25 C, I S = 8.3A, V GS = 0V t rr Reverse Recovery Time ns T J = 25 C, I F = 8.3A Q rr Reverse RecoveryCharge 520 nc di/dt = 0A/µs t on Forward Turn-On Time Intrinsic turn-on time is negigibe (turn-on is dominated by L S L D ) 2

3 I D, Drain-to-Source Current (A) 0 VGS TOP 5V 2V V 8.0V 7.0V 6.0V 5.5V BOTTOM 5.0V 5.0V I D, Drain-to-Source Current (A) 0 VGS TOP 5V 2V V 8.0V 7.0V 6.0V 5.5V BOTTOM 5.0V 5.0V 20µs PULSE WIDTH T J = 25 C V DS, Drain-to-Source Votage (V) 20µs PULSE WIDTH T J = 75 C 0 V DS, Drain-to-Source Votage (V) Fig. Typica Output Characteristics Fig 2. Typica Output Characteristics I D, Drain-to-Source Current (A) 0 T J = 75 C T J = 25 C V DS= 50V 20µs PULSE WIDTH V GS, Gate-to-Source Votage (V) R DS(on), Drain-to-Source On Resistance (Normaized) 3.0 I D = 4A V GS = V T J, Junction Temperature ( C) Fig 4. Normaized On-Resistance Fig 3. Typica Transfer Characteristics Vs. Temperature 3

4 C, Capacitance(pF) IRFR/U3N5DPbF V GS = 0V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd Ciss Coss Crss 0 00 V DS, Drain-to-Source Votage (V) V GS, Gate-to-Source Votage (V) I = D 8.3A V DS = 20V V DS = 75V V DS = 30V FOR TEST CIRCUIT SEE FIGURE Q G, Tota Gate Charge (nc) Fig 5. Typica Capacitance Vs. Drain-to-Source Votage Fig 6. Typica Gate Charge Vs. Gate-to-Source Votage I SD, Reverse Drain Current (A) 0 T J = 75 C T J = 25 C V GS = 0 V V SD,Source-to-Drain Votage (V) I D, Drain Current (A) 00 0 OPERATION IN THIS AREA LIMITED BY R DS(on) us 0us ms ms TC = 25 C TJ = 75 C Singe Puse 0 00 V DS, Drain-to-Source Votage (V) Fig 7. Typica Source-Drain Diode Forward Votage Fig 8. Maximum Safe Operating Area 4

5 4 V DS R D I D, Drain Current (A) R G V GS V GS Puse Width µs Duty Factor % D.U.T. Fig a. Switching Time Test Circuit - V DD T C, Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature V DS 90% % V GS t d(on) t r t d(off) t f Fig b. Switching Time Waveforms Therma Response (Z thjc ) D = SINGLE PULSE (THERMAL RESPONSE) Notes:. Duty factor D = t / t 2 2. Peak T J = P DM x Z thjc TC t, Rectanguar Puse Duration (sec) PDM t t2 Fig. Maximum Effective Transient Therma Impedance, Junction-to-Case 5

6 5V V DS L DRIVER R G D.U.T I AS - V DD A 20V tp 0.0Ω Fig 2a. Uncamped Inductive Test Circuit V (BR)DSS tp E AS, Singe Puse Avaanche Energy (mj) TOP BOTTOM I D 3.4A 5.9A 8.3A Starting T, Junction Temperature ( J C) Fig 2c. Maximum Avaanche Energy Vs. Drain Current I AS Fig 2b. Uncamped Inductive Waveforms Current Reguator Same Type as D.U.T. Q G 50KΩ Q GS Q GD 2V.2µF.3µF D.U.T. V - DS V G V GS 3mA Charge I G I D Current Samping Resistors Fig 3a. Basic Gate Charge Waveform Fig 3b. Gate Charge Test Circuit 6

7 Peak Diode Recovery dv/dt Test Circuit D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Pane Low Leakage Inductance Current Transformer - - R G dv/dt controed by R G Driver same type as D.U.T. I SD controed by Duty Factor "D" D.U.T. - Device Under Test - V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-Appied Votage Inductor Curent Body Diode Forward Drop Rippe 5% I SD * V GS = 5V for Logic Leve Devices Fig 4. For N-Channe HEXFET Power MOSFETs 7

8 D-Pak (TO-252AA) Package Outine Dimensions are shown in miimeters (inches) D-Pak (TO-252AA) Part Marking Information EXAMPLE: THIS IS AN IRFR20 WITH ASSEMBLY LOT CODE 234 ASSEMBLED ON WW 6, 999 IN THE ASSEMBLY LINE "A" Note: "P" in assemby ine position indicates "Lead-Free" INTERNATIONAL RECTIFIER LOGO AS S E MBL Y LOT CODE IRFU20 96A 2 34 PART NUMBER DATE CODE YEAR 9 = 999 WEEK 6 LINE A OR INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE IRFU PART NUMBER DATE CODE P = DESIGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR 9 = 999 WEEK 6 A = ASSEMBLY SITE CODE 8

9 I-Pak (TO-25AA) Package Outine Dimensions are shown in miimeters (inches) IRFR/U3N5DPbF I-Pak (TO-25AA) Part Marking Information EXAMPLE: THIS IS AN IRFU20 WITH ASSEMBLY LOT CODE 5678 ASSEMBLED ON WW 9, 999 IN THE ASSEMBLY LINE "A" Note: "P" in assemby ine position indicates "Lead-Free" INTERNATIONAL RECTIFIER LOGO AS S E MB LY LOT CODE IRFU20 99A PART NUMBER DATE CODE YEAR 9 = 999 WEEK 9 LINE A OR INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE IRFU PART NUMBER DATE CODE P = DES IGNAT E S LEAD-F RE E PRODUCT (OPTIONAL) YEAR 9 = 999 WEEK 9 A = ASSEMBLY SITE CODE 9

10 D-Pak (TO-252AA) Tape & Ree Information Dimensions are shown in miimeters (inches) TR TRR TRL 6.3 (.64 ) 5.7 (.69 ) 6.3 (.64 ) 5.7 (.69 ) 2. (.476 ).9 (.469 ) FEED DIRECTION 8. (.38 ) 7.9 (.32 ) FEED DIRECTION NOTES :. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-48 & EIA INCH NOTES :. OUTLINE CONFORMS TO EIA mm Notes: Repetitive rating; puse width imited by max. junction temperature. Starting T J = 25 C, L = 3.8mH R G = 25Ω, I AS = 8.3A. ƒ I SD 8.3A, di/dt 280A/µs, V DD V (BR)DSS, T J 75 C Puse width 300µs; duty cyce 2%. C oss eff. is a fixed capacitance that gives the same charging time as C oss whie V DS is rising from 0 to 80% V DSS * When mounted on " square PCB (FR-4 or G- Materia). For recommended footprint and sodering techniques refer to appication note #AN-994. Data and specifications subject to change without notice. IR WORLD HEADQUARTERS: 233 Kansas St., E Segundo, Caifornia 90245, USA Te: (3) TAC Fax: (3) Visit us at for saes contact information.2/04

11 Note: For the most current drawings pease refer to the IR website at: