Fast Characterization of PBTI and NBTI Induced Frequency Shifts under a Realistic Recovery Bias Using a Ring Oscillator Based Circuit
|
|
- August Stewart
- 5 years ago
- Views:
Transcription
1 Fast Characterization of PBTI and NBTI Induced Frequency Shifts under a Realistic Recovery Bias Using a Ring Oscillator Based Circuit 1,2 Xiaofei Wang, 1 Seung-hwan Song, 1 Ayan Paul and 1 Chris H. Kim 1 University of Minnesota, Minneapolis, MN 2 Now at Intel Corporation xiaofei.wang@intel.com
2 Purpose Separately characterize impact of PBTI and NBTI on frequency under DC and AC Design an on-chip monitor to support realistic recovery condition and precise and fast measurement 2/21
3 Outline NBTI and PBTI Monitoring in HKMG Process and Prior Arts NBTI and PBTI Aging Monitor Design Results from HKMG Test Chip Summary 3/21
4 PBTI and NBTI in HKMG NBTI and PBTI have different magnitude and behavior due to different mechanism and trap location The difference between NBTI and PBTI is highly dependent on the technology NBTI and PBTI need to be characterized separately 4/21
5 Previous Work on PBTI/NBTI Monitoring J. Kim, et al., ICICDT, 2008 J. Kim, et al., VLSI, 2011 For both designs: In stress:v gs =-V DD, V ds =0 In recovery: V gs =0, V ds =0 During operation, most transistor recovery with V ds =V DD Easy to apply stress bias, but hard to turn the transistor off while keeping V ds at V STR 5/21
6 Proposed Ring Oscillator in Stress Mode NBTI Stress Mode PBTI Stress Mode AC Stress ON ON OFF OFF V Str / 0 0 / V Str V Str / V Str -V T V Str / 0 V Str / 0 0 / V T 0 / V Str AC Stress OFF OFF ON ON 0 / V Str : NBTI : PBTI Stress / Recovery V Str : V_Stress Use pass gate and tri-state inverter to isolate stress During NBTI stress mode, NMOS source and gate are shorted Realistic AC stress (i.e. V ds ~V DD ) can be provided 6/21
7 Proposed Ring Oscillator in Meas. Mode Additional inverters and pass gates are all turned off, and the loop is closed to initiate the oscillation The impact of additional load of the auxiliary circuits on main path delay can be calibrated out 7/21
8 Calibration to Plain ROSC Degradation Schematic Measurable Relationship β R h R f R p R x R n C 1 ( Δf f ) Δf PBTI, ( f ) NBTI Δf Δf f = β f C 2 C 3 R p C 1 Δf f R n C L [( ) Δf PBTI + ( f ) NBTI ] 1 [(R (R h +R f )(C 2 +C 3 ) h +R f )(C 1 +C 2 +C 3 ) + (R h +R p +R f +R n )(C 2 +C 3 )+R g C 3 ] Frequency shift (%) C, 1.8V, 200MHz AC stress Δf f Δf Δf = β [( ) f PBTI + ( ) f NBTI ] PBTI NBTI Plain Stress time (s) The delay induced by the additional switches are not dependent on aging, proven by simulation Test results can be calibrated using one point calibration 8/21
9 Comparison on PBTI/NBTI Monitoring ICICDT 2008 VLSI 2011 This work ROSC Stage Diagram (NBTI Stress Mode Shown) V STR GND GND V STR V STR GND V STR V DD -VN V DD GND V DD GND V DD GND V STR GND V STR GND V STR GND Stress Capability DC No AC data DC Unrealistic AC (i.e. V ds =0) DC Realistic AC (i.e. V ds =~V STR ) Meas. Scheme Simple counter Simple counter Beat frequency scheme with phase alignment *Meas. Time for 0.01% Resolution 10,000 ROSC periods 10,000 ROSC periods 100 ROSC periods (<1μs) Neither of the previous designs can provide realistic recovery bias (i.e. V ds =V DD ) Simple counter based scheme results in unwanted recovery 9/21
10 Silicon Odometer Beat Frequency Scheme T. Kim, et al., JSSC, 2008 Beat frequency of two free running ROSCs measured by DFF and edge detector Benefits of beat frequency detection system Achieve ps resolution with μs measurement interrupt Insensitive to common mode noise such as temperature drifts Fully digital, scan based interface, easy to implement 10/21
11 Use Beat Frequency to Detect Aging Stressed ROSC Reference ROSC A B Phase Comp. Beat Frequency Counter f str : 0.99GHz A B f ref : 1.00GHz Phase comparator is used to generate the beat frequency At time zero the stressed ROSC is trimmed to be slightly slower than the reference ROSC 11/21
12 Use Beat Frequency to Detect Aging Stressed ROSC Reference ROSC A B Phase Comp. C PC_OUT (f beat = f ref - f stress ) Beat Frequency Counter Couter: N=100 B C A Phase comparator output: f beat = f ref -f stress The counter counts the number of reference cycle in one period of the beat signal N = [(f str -f ref )/f ref ] 12/21
13 Use Beat Frequency to Detect Aging f Stress (GHz): 0.99 Stressed ROSC Reference ROSC f ref : 1.00GHz A B Phase Comp. C PC_OUT (f beat = f ref - f stress ) Beat Frequency Counter Counter: N= N=50 1% frequency difference before stress N=100 2% frequency difference after stress N=50 Δf or ΔT sensing resolution is 0.01% 13/21
14 HKMG Test Chip Die Photo and Features 14/21
15 DC Stress Results for PBTI and NBTI Both NBTI and PBTI induced frequency shift show power law dependence with stress time Magnitude of PBTI is 5X to 10X larger than that of NBTI Time exponent n is lower than reported value 15/21
16 Impact of Measurement Interruption Time Frequency shift (%) Meas. Time / n 25 C, 1.4V, DC stress 400ns / µs / µs / µs / µs / µs / Longer measurement interrupt Stress time (s) Time exponent n C, 1.4V, DC stress Due to unwanted recovery during measurement 400ns meas. interrupt Measurement time (s) Degradation decreases with longer measurement time Time exponent n increases with longer measurement interruption due to the recovery effect during measurement 16/21
17 Impact of Realistic Recovery Bias STR HfO 2 HfO 2 SiO 2 p-si SiO 2 p-si V ds bias gives stronger recovery rate when the transistor is off compared to zero V ds The de-trapping process is accelerated due to the reduced potential barrier 17/21
18 DC and AC Stress at 25 C and 110 C Frequency shift (%) PBTI NBTI 1.4V, DC stress n=0.12 n=0.09 n=0.14 n=0.22 : 25 C : 110 C PBTI 1.4V, 200MHz AC stress n=0.10 n=0.05 NBTI n=0.14 n= Stress time (s) NBTI is more sensitive to the temperature compared to PBTI The time slope dependence is more significant for AC stress 18/21
19 Long-Term Recovery Results versus Stress Voltage Frequency shift (%) C for 1000s 25 C, 0V PBTI V stress : : 1.8V : 1.4V 0.6 NBTI ln(t) ln(t) ln(t) ln(t) Frequency shift (%) Recovery time (s) Recovery time (s) Both PBTI and NBTI recovery follows a -log(t) dependency The magnitude and the log slope increases with stress voltage before recovery 19/21
20 Temperature Dependence of Recovery Frequency shift (%) PBTI -0.02ln(x) ln(x) V for 1000s 0V : 110 C : C ln(x) ln(x) Recovery time (s) Recovery time (s) Recovery magnitude and time slope show small difference at high temp. versus low temp. Both PBTI and NBTI recovery shows a weak dependence on temperature Frequency shift (%) NBTI 20/21
21 Summary A ring oscillator based circuit separately monitor PBTI and NBTI impact on frequency >0.01% resolution with measurement time down to >400ns Supports realistic recovery bias condition Realistic power law time exponent measured using fast measurements Experimental data confirms that realistic recovery bias (i.e. V ds ~V DD ) indeed accelerates recovery compared to power down situation (i.e. V ds =0V) 21/21
SRAM Read Performance Degradation under Asymmetric NBTI and PBTI Stress: Characterization Vehicle and Statistical Aging
SRAM Read Performance Degradation under Asymmetric NBTI and PBTI Stress: Characterization Vehicle and Statistical Aging Xiaofei Wang,2 Weichao Xu 2 and Chris H. Kim 2 Intel Corporation, Hillsboro 2 University
More informationImpact of Interconnect Length on. Degradation
Impact of Interconnect Length on BTI and HCI Induced Frequency Degradation Xiaofei Wang, Pulkit Jain, Dong Jiao and Chris H. Kim University of Minnesota, Minneapolis, MN xfwang@umn.edu www.umn.edu/~chriskim/
More informationSilicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits
Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits Tae-Hyoung Kim, Randy Persaud and Chris H. Kim Department of Electrical and Computer Engineering
More informationRTN Induced Frequency Shift Measurements Using a Ring Oscillator Based Circuit
RTN Induced Frequency Shift Measurements Using a Ring Oscillator Based Circuit Qianying Tang 1, Xiaofei Wang 1, John Keane 2, and Chris H. Kim 1 1 University of Minnesota, Minneapolis, MN 2 Intel Corporation,
More informationDuty-Cycle Shift under Asymmetric BTI Aging: A Simple Characterization Method and its Application to SRAM Timing
Duty-Cycle Shift under Asymmetric BTI Aging: A Simple Characterization Method and its Application to SRAM Timing 1 Xiaofei Wang, 2 John Keane, 2 Pulkit Jain, 3 Vijay Reddy and 1 Chris H. Kim 1 University
More informationImpact of Interconnect Length on BTI and HCI Induced Frequency Degradation
Impact of Interconnect Length on BTI and HCI Induced Frequency Degradation Xiaofei Wang Pulkit Jain Dong Jiao Chris H. Kim Department of Electrical & Computer Engineering University of Minnesota 200 Union
More informationDuty-Cycle Shift under Asymmetric BTI Aging: A Simple Characterization Method and its Application to SRAM Timing 1 Xiaofei Wang
Duty-Cycle Shift under Asymmetric BTI Aging: A Simple Characterization Method and its Application to SRAM Timing 1 Xiaofei Wang Abstract the effect of DC BTI stress on the clock signal's dutycycle has
More informationIEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 4, APRIL
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 4, APRIL 2010 817 An All-In-One Silicon Odometer for Separately Monitoring HCI, BTI, and TDDB John Keane, Student Member, IEEE, Xiaofei Wang, Student
More informationAn Array-Based Circuit for Characterizing Latent Plasma-Induced Damage
An Array-Based Circuit for Characterizing Latent Plasma-Induced Damage Won Ho Choi, Pulkit Jain and Chris H. Kim University of Minnesota, Minneapolis, MN choi0444@umn.edu www.umn.edu/~chriskim/ Purpose
More informationAll-Digital PLL Frequency and Phase Noise Degradation Measurements Using Simple On-Chip Monitoring Circuits
All-Digital PLL Frequency and Noise Degradation Measurements Using Simple On-Chip Monitoring Circuits Gyusung Park, Minsu Kim and Chris H. Kim Department of Electrical and Computer Engineering University
More informationOn-Chip Silicon Odometers and their Potential Use in Medical Electronics
On-Chip Silicon Odometers and their Potential Use in Medical Electronics John Keane 1 and Chris H. Kim 1. Intel Corporation, Technology and Manufacturing Group, Hillsboro, OR, USA. University of Minnesota,
More informationSILICON ODOMETERS:COMPACT IN SITU AGING SENSORS FOR ROBUST SYSTEM DESIGN
... SILICON ODOMETERS:COMPACT IN SITU AGING SENSORS FOR ROBUST SYSTEM DESIGN... THIS ARTICLE REVIEWS SEVERAL TEST-CHIP DESIGNS THAT DEMONSTRATE THE BENEFITS Xiaofei Wang University of Minnesota John Keane
More informationTrue Random Number Generator Circuits Based on Single- and Multi- Phase Beat Frequency Detection
True Random Number Generator Circuits Based on Single- and Multi- Phase Beat Frequency Detection Qianying Tang, Bongjin Kim, Yingjie Lao, Keshab K. Parhi, and Chris H. Kim University of Minnesota, Minneapolis,
More informationDefect-Oriented Degradations in Recent VLSIs: Random Telegraph Noise, Bias Temperature Instability and Total Ionizing Dose
Defect-Oriented Degradations in Recent VLSIs: Random Telegraph Noise, Bias Temperature Instability and Total Ionizing Dose Kazutoshi Kobayashi Kyoto Institute of Technology Kyoto, Japan kazutoshi.kobayashi@kit.ac.jp
More informationA Methodology for Measuring Transistor Ageing Effects Towards Accurate Reliability Simulation
A Methodology for Measuring Transistor Ageing Effects Towards Accurate Reliability Simulation Elie Maricau and Georges Gielen ESAT-MICAS KULeuven Heverlee-Leuven, Belgium 3001 Email: elie.maricau@esat.kuleuven.be
More informationMicroelectronics Reliability
Microelectronics Reliability 50 (2010) 1039 1053 Contents lists available at ScienceDirect Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel Introductory Invited Paper On-chip
More informationAn On-Chip NBTI Sensor for Measuring PMOS Threshold Voltage Degradation
An On-Chip NBTI Sensor for Measuring PMOS Threshold Voltage Degradation John Keane Tae-Hyoung Kim Chris H. Kim Department of Electrical Engineering University of Minnesota, Minneapolis, MN {jkeane, thkim,
More informationRANDOM telegraph noise (RTN) has become an increasing
IEEE JOURNAL OF SOLID-STATE CIRCUITS 1 Characterizing the Impact of RTN on Logic and SRAM Operation Using a Dual Ring Oscillator Array Circuit Qianying Tang, Student Member, IEEE, andchrish.kim,senior
More informationEffect of Aging on Power Integrity of Digital Integrated Circuits
Effect of Aging on Power Integrity of Digital Integrated Circuits A. Boyer, S. Ben Dhia Alexandre.boyer@laas.fr Sonia.bendhia@laas.fr 1 May 14 th, 2013 Introduction and context Long time operation Harsh
More informationA mm 2 /Channel Time-Based Beat Frequency ADC in 65nm CMOS for Intra-Electrode Neural Recording
A 0.0094mm 2 /Channel Time-Based Beat Frequency ADC in 65nm CMOS for Intra-Electrode Neural Recording Luke Everson 1, Somnath Kundu 1, Gang Chen 2, Zhi Yang 3, Timothy J. Ebner 2, and Chris H. Kim 1 1
More informationA Clock Generating System for USB 2.0 with a High-PSR Bandgap Reference Generator
ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY Volume 14, Number 4, 2011, 380 391 A Clock Generating System for USB 2.0 with a High-PSR Bandgap Reference Generator Seok KIM 1, Seung-Taek YOO 1,2,
More informationAn Array-Based Odometer System for Statistically Significant Circuit Aging Characterization
2374 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 10, OCTOBER 2011 An Array-Based Odometer System for Statistically Significant Circuit Aging Characterization John Keane, Member, IEEE, Wei Zhang,
More informationA Robust Oscillator for Embedded System without External Crystal
Appl. Math. Inf. Sci. 9, No. 1L, 73-80 (2015) 73 Applied Mathematics & Information Sciences An International Journal http://dx.doi.org/10.12785/amis/091l09 A Robust Oscillator for Embedded System without
More informationA 0.2-to-1.45GHz Subsampling Fractional-N All-Digital MDLL with Zero-Offset Aperture PD-Based Spur Cancellation and In-Situ Timing Mismatch Detection
A 0.2-to-1.45GHz Subsampling Fractional-N All-Digital MDLL with Zero-Offset Aperture PD-Based Spur Cancellation and In-Situ Timing Mismatch Detection Somnath Kundu 1, Bongjin Kim 1,2, Chris H. Kim 1 1
More informationEstimation of Instantaneous Frequency Fluctuation in a Fast DVFS Environment Using an Empirical BTI Stress- Relaxation Model
Estimation of Instantaneous Frequency Fluctuation in a Fast DVFS Environment Using an Empirical BTI Stress- Relaxation Model Chen Zhou Xiaofei Wang Weichao Xu *Yuhao Zhu *Vijay Janapa Reddi Chris H. Kim
More informationChapter 6 DIFFERENT TYPES OF LOGIC GATES
Chapter 6 DIFFERENT TYPES OF LOGIC GATES Lesson 8 NMOS gates Ch06L8-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 2 Outline NMOS (n-channel based MOSFETs based circuit) NMOS Features
More informationIntroducing Pulsing into Reliability Tests for Advanced CMOS Technologies
WHITE PAPER Introducing Pulsing into Reliability Tests for Advanced CMOS Technologies Pete Hulbert, Industry Consultant Yuegang Zhao, Lead Applications Engineer Keithley Instruments, Inc. AC, or pulsed,
More informationLecture 160 Examples of CDR Circuits in CMOS (09/04/03) Page 160-1
Lecture 160 Examples of CDR Circuits in CMOS (09/04/03) Page 160-1 LECTURE 160 CDR EXAMPLES INTRODUCTION Objective The objective of this presentation is: 1.) Show two examples of clock and data recovery
More informationSemiconductor Process Reliability SVTW 2012 Esko Mikkola, Ph.D. & Andrew Levy
Semiconductor Process Reliability SVTW 2012 Esko Mikkola, Ph.D. & Andrew Levy 1 IC Failure Modes Affecting Reliability Via/metallization failure mechanisms Electro migration Stress migration Transistor
More informationMOS Transistor Theory
MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 MOS Transistor Theory Study conducting channel between
More informationA 10Gb/s 10mm On-Chip Serial Link in 65nm CMOS Featuring a Half-Rate Time-Based Decision Feedback Equalizer
A 10Gb/s 10mm On-Chip Serial Link in 65nm CMOS Featuring a Half-Rate Time-Based Decision Feedback Equalizer Po-Wei Chiu, Somnath Kundu, Qianying Tang, and Chris H. Kim University of Minnesota, Minneapolis,
More information20 GHz Low Power QVCO and De-skew Techniques in 0.13µm Digital CMOS. Masum Hossain & Tony Chan Carusone University of Toronto
20 GHz Low Power QVCO and De-skew Techniques in 0.13µm Digital CMOS Masum Hossain & Tony Chan Carusone University of Toronto masum@eecg.utoronto.ca Motivation Data Rx3 Rx2 D-FF D-FF Rx1 D-FF Clock Clock
More informationA 0.7 V-to-1.0 V 10.1 dbm-to-13.2 dbm 60-GHz Power Amplifier Using Digitally- Assisted LDO Considering HCI Issues
A 0.7 V-to-1.0 V 10.1 dbm-to-13.2 dbm 60-GHz Power Amplifier Using Digitally- Assisted LDO Considering HCI Issues Rui Wu, Yuuki Tsukui, Ryo Minami, Kenichi Okada, and Akira Matsuzawa Tokyo Institute of
More informationSession 10: Solid State Physics MOSFET
Session 10: Solid State Physics MOSFET 1 Outline A B C D E F G H I J 2 MOSCap MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor: Al (metal) SiO2 (oxide) High k ~0.1 ~5 A SiO2 A n+ n+ p-type Si (bulk)
More informationAnalyzing Combined Impacts of Parameter Variations and BTI in Nano-scale Logical Gates
Analyzing Combined Impacts of Parameter Variations and BTI in Nano-scale Logical Gates Seyab Khan Said Hamdioui Abstract Bias Temperature Instability (BTI) and parameter variations are threats to reliability
More informationUniversity of Minnesota, Minneapolis, MN 2. Intel Corporation, Hillsboro, OR 3. Los Alamos National Laboratory, Los Alamos, NM
Statistical Characterization of Radiation- Induced Pulse Waveforms and Flip-Flop Soft Errors in 14nm Tri-Gate CMOS Using a Back- Sampling Chain (BSC) Technique Saurabh Kumar 1, M. Cho 2, L. Everson 1,
More informationHomework Assignment 07
Homework Assignment 07 Question 1 (Short Takes). 2 points each unless otherwise noted. 1. A single-pole op-amp has an open-loop low-frequency gain of A = 10 5 and an open loop, 3-dB frequency of 4 Hz.
More informationOn-silicon Instrumentation
On-silicon Instrumentation An approach to alleviate the variability problem Peter Y. K. Cheung Department of Electrical and Electronic Engineering 18 th March 2014 U. of York How we started (in 2006)!
More informationA Multi-phase VCO Quantizer based Adaptive Digital LDO in 65nm CMOS Technology
A Multi-phase VCO Quantizer based Adaptive Digital LDO in 65nm CMOS Technology Somnath Kundu and Chris H. Kim University of Minnesota Dept. of ECE 1 Presentation Outline Analog vs. digital Low DropOut
More informationTechnical Paper FA 10.3
Technical Paper A 0.9V 150MHz 10mW 4mm 2 2-D Discrete Cosine Transform Core Processor with Variable-Threshold-Voltage Scheme Tadahiro Kuroda, Tetsuya Fujita, Shinji Mita, Tetsu Nagamatu, Shinichi Yoshioka,
More informationSpintronics-Based Mixed-Signal Circuits
CMOS Reliability Characterization Techniques and Spintronics-Based Mixed-Signal Circuits A DISSERTATION SUBMITTED TO THE FACULTY OF THE GRADUATE SCHOOL OF THE UNIVERSITY OF MINNESOTA BY Won Ho Choi IN
More informationDLL Based Frequency Multiplier
DLL Based Frequency Multiplier Final Project Report VLSI Chip Design Project Project Group 4 Version 1.0 Status Reviewed Approved Ameya Bhide Ameya Bhide TSEK06 VLSI Design Project 1 of 29 Group 4 PROJECT
More informationLOW CURRENT REFERENCES WITH SUPPLY INSENSITIVE BIASING
Annals of the Academy of Romanian Scientists Series on Science and Technology of Information ISSN 2066-8562 Volume 3, Number 2/2010 7 LOW CURRENT REFERENCES WITH SUPPLY INSENSITIVE BIASING Vlad ANGHEL
More informationTransistor Network Restructuring Against NBTI Degradation. P. F. Butzen a, V. Dal Bem a, A. I. Reis b, R. P. Ribas b.
Transistor Network Restructuring Against NBTI Degradation. P. F. Butzen a, V. Dal Bem a, A. I. Reis b, R. P. Ribas b. a PGMICRO, Federal University of Rio Grande do Sul, Porto Alegre, Brazil b Institute
More information/$ IEEE
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 53, NO. 11, NOVEMBER 2006 1205 A Low-Phase Noise, Anti-Harmonic Programmable DLL Frequency Multiplier With Period Error Compensation for
More informationUMAINE ECE Morse Code ROM and Transmitter at ISM Band Frequency
UMAINE ECE Morse Code ROM and Transmitter at ISM Band Frequency Jamie E. Reinhold December 15, 2011 Abstract The design, simulation and layout of a UMAINE ECE Morse code Read Only Memory and transmitter
More informationA VCO-Based ADC Employing a Multi- Phase Noise-Shaping Beat Frequency Quantizer for Direct Sampling of Sub-1mV Input Signals
A VCO-Based ADC Employing a Multi- Phase Noise-Shaping Beat Frequency Quantizer for Direct Sampling of Sub-1mV Input Signals Bongjin Kim, Somnath Kundu, Seokkyun Ko and Chris H. Kim University of Minnesota,
More informationNOVEMBER 28, 2016 COURSE PROJECT: CMOS SWITCHING POWER SUPPLY EE 421 DIGITAL ELECTRONICS ERIC MONAHAN
NOVEMBER 28, 2016 COURSE PROJECT: CMOS SWITCHING POWER SUPPLY EE 421 DIGITAL ELECTRONICS ERIC MONAHAN 1.Introduction: CMOS Switching Power Supply The course design project for EE 421 Digital Engineering
More informationA Variable-Frequency Parallel I/O Interface with Adaptive Power Supply Regulation
WA 17.6: A Variable-Frequency Parallel I/O Interface with Adaptive Power Supply Regulation Gu-Yeon Wei, Jaeha Kim, Dean Liu, Stefanos Sidiropoulos 1, Mark Horowitz 1 Computer Systems Laboratory, Stanford
More informationUnlocking the Power of GaN PSMA Semiconductor Committee Industry Session
Unlocking the Power of GaN PSMA Semiconductor Committee Industry Session March 24 th 2016 Dan Kinzer, COO/CTO dan.kinzer@navitassemi.com 1 Mobility (cm 2 /Vs) EBR Field (MV/cm) GaN vs. Si WBG GaN material
More informationComparison of 32nm High-k Metal Gate Predictive Technology Model CMOS and MOSFET-Like CNFET compact Model Based Domino logic Circuits
Comparison of 32nm High-k Metal Gate Predictive Technology Model CMOS and MOSFET-Like CNFET compact Model Based Domino logic Circuits Saravana Maruthamuthu, Wireless Group Infineon Technologies India Private
More informationA gate sizing and transistor fingering strategy for
LETTER IEICE Electronics Express, Vol.9, No.19, 1550 1555 A gate sizing and transistor fingering strategy for subthreshold CMOS circuits Morteza Nabavi a) and Maitham Shams b) Department of Electronics,
More informationA Digital Clock Multiplier for Globally Asynchronous Locally Synchronous Designs
A Digital Clock Multiplier for Globally Asynchronous Locally Synchronous Designs Thomas Olsson, Peter Nilsson, and Mats Torkelson. Dept of Applied Electronics, Lund University. P.O. Box 118, SE-22100,
More informationECEN689: Special Topics in Optical Interconnects Circuits and Systems Spring 2016
ECEN689: Special Topics in Optical Interconnects Circuits and Systems Spring 2016 Lecture 10: Electroabsorption Modulator Transmitters Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements
More informationIntroduction to VLSI ASIC Design and Technology
Introduction to VLSI ASIC Design and Technology Paulo Moreira CERN - Geneva, Switzerland Paulo Moreira Introduction 1 Outline Introduction Is there a limit? Transistors CMOS building blocks Parasitics
More informationChannel Engineering for Submicron N-Channel MOSFET Based on TCAD Simulation
Australian Journal of Basic and Applied Sciences, 2(3): 406-411, 2008 ISSN 1991-8178 Channel Engineering for Submicron N-Channel MOSFET Based on TCAD Simulation 1 2 3 R. Muanghlua, N. Vittayakorn and A.
More informationECE 340 Lecture 40 : MOSFET I
ECE 340 Lecture 40 : MOSFET I Class Outline: MOS Capacitance-Voltage Analysis MOSFET - Output Characteristics MOSFET - Transfer Characteristics Things you should know when you leave Key Questions How do
More informationWHITE PAPER CIRCUIT LEVEL AGING SIMULATIONS PREDICT THE LONG-TERM BEHAVIOR OF ICS
WHITE PAPER CIRCUIT LEVEL AGING SIMULATIONS PREDICT THE LONG-TERM BEHAVIOR OF ICS HOW TO MINIMIZE DESIGN MARGINS WITH ACCURATE ADVANCED TRANSISTOR DEGRADATION MODELS Reliability is a major criterion for
More informationA fully synthesizable injection-locked PLL with feedback current output DAC in 28 nm FDSOI
LETTER IEICE Electronics Express, Vol.1, No.15, 1 11 A fully synthesizable injection-locked PLL with feedback current output DAC in 8 nm FDSOI Dongsheng Yang a), Wei Deng, Aravind Tharayil Narayanan, Rui
More informationA Novel Multiplier Design using Adaptive Hold Logic to Mitigate BTI Effect
GRD Journals Global Research and Development Journal for Engineering International Conference on Innovations in Engineering and Technology (ICIET) - 2016 July 2016 e-issn: 2455-5703 A Novel Multiplier
More informationPERSPECTIVES FOR DISRUPTIVE 200MM/8-INCH GAN POWER DEVICE AND GAN-IC TECHNOLOGY DR. DENIS MARCON SR. BUSINESS DEVELOPMENT MANAGER
PERSPECTIVES FOR DISRUPTIVE 200MM/8-INCH GAN POWER DEVICE AND GAN-IC TECHNOLOGY DR. DENIS MARCON SR. BUSINESS DEVELOPMENT MANAGER What I will show you today 200mm/8-inch GaN-on-Si e-mode/normally-off technology
More informationLM1292 Video PLL System for Continuous-Sync Monitors
LM1292 Video PLL System for Continuous-Sync Monitors General Description The LM1292 is a very low jitter, integrated horizontal time base solution specifically designed to operate in high performance,
More informationComputer-Based Project on VLSI Design Co 3/7
Computer-Based Project on VLSI Design Co 3/7 Electrical Characterisation of CMOS Ring Oscillator This pamphlet describes a laboratory activity based on an integrated circuit originally designed and tested
More informationSiNANO-NEREID Workshop:
SiNANO-NEREID Workshop: Towards a new NanoElectronics Roadmap for Europe Leuven, September 11 th, 2017 WP3/Task 3.2 Connectivity RF and mmw Design Outline Connectivity, what connectivity? High data rates
More informationAnalog Circuit Reliability in Sub-32 Nanometer CMOS: Analysis and Mitigation
Analog Circuit Reliability in Sub-32 Nanometer CMOS: Analysis and Mitigation Georges Gielen, Elie Maricau and Pieter De Wit ESAT-MICAS, K.U.Leuven, Belgium Abstract The paper discusses reliability threats
More informationComputer-Based Project on VLSI Design Co 3/8
Computer-Based Project on VLSI Design Co 3/8 This pamphlet describes a laboratory activity based on a former third year EIST experiment. Its purpose is the measurement of the switching speed of some CMOS
More information2009 Spring CS211 Digital Systems & Lab 1 CHAPTER 3: TECHNOLOGY (PART 2)
1 CHAPTER 3: IMPLEMENTATION TECHNOLOGY (PART 2) Whatwillwelearninthischapter? we learn in this 2 How transistors operate and form simple switches CMOS logic gates IC technology FPGAs and other PLDs Basic
More informationNew Generation Reliability Model
New Generation Reliability Model S.-Y. Liao, C. Huang, T. Guo, A. Chen, Jushan Xie, Cadence Design Systems, Inc. S. Guo, R. Wang, Z. Yu, P. Hao, P. Ren, Y. Wang, R. Huang, Peking University Dec. 5th, 2016
More informationA CMOS CURRENT CONTROLLED RING OSCILLATOR WITH WIDE AND LINEAR TUNING RANGE
A CMOS CURRENT CONTROLLED RING OSCILLATOR WI WIDE AND LINEAR TUNING RANGE Abstract Ekachai Leelarasmee 1 1 Electrical Engineering Department, Chulalongkorn University, Bangkok 10330, Thailand Tel./Fax.
More informationEECS 427 Lecture 13: Leakage Power Reduction Readings: 6.4.2, CBF Ch.3. EECS 427 F09 Lecture Reminders
EECS 427 Lecture 13: Leakage Power Reduction Readings: 6.4.2, CBF Ch.3 [Partly adapted from Irwin and Narayanan, and Nikolic] 1 Reminders CAD assignments Please submit CAD5 by tomorrow noon CAD6 is due
More informationD f ref. Low V dd (~ 1.8V) f in = D f ref
A 5.3 GHz Programmable Divider for HiPerLAN in 0.25µm CMOS N. Krishnapura 1 & P. Kinget 2 Lucent Technologies, Bell Laboratories, USA. 1 Currently at Columbia University, New York, NY, 10027, USA. 2 Currently
More informationDelay-based clock generator with edge transmission and reset
LETTER IEICE Electronics Express, Vol.11, No.15, 1 8 Delay-based clock generator with edge transmission and reset Hyunsun Mo and Daejeong Kim a) Department of Electronics Engineering, Graduate School,
More informationLow Power Realization of Subthreshold Digital Logic Circuits using Body Bias Technique
Indian Journal of Science and Technology, Vol 9(5), DOI: 1017485/ijst/2016/v9i5/87178, Februaru 2016 ISSN (Print) : 0974-6846 ISSN (Online) : 0974-5645 Low Power Realization of Subthreshold Digital Logic
More informationA 400 MHz 4.5 nw 63.8 dbm Sensitivity Wake-up Receiver Employing an Active Pseudo-Balun Envelope Detector
A 400 MHz 4.5 nw 63.8 dbm Sensitivity Wake-up Receiver Employing an Active Pseudo-Balun Envelope Detector Po-Han Peter Wang, Haowei Jiang, Li Gao, Pinar Sen, Young-Han Kim, Gabriel M. Rebeiz, Patrick P.
More informationREDUCING power consumption and enhancing energy
548 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 63, NO. 6, JUNE 2016 A Low-Voltage PLL With a Supply-Noise Compensated Feedforward Ring VCO Sung-Geun Kim, Jinsoo Rhim, Student Member,
More informationIOLTS th IEEE International On-Line Testing Symposium
IOLTS 2018 24th IEEE International On-Line Testing Symposium Exp. comparison and analysis of the sensitivity to laser fault injection of CMOS FD-SOI and CMOS bulk technologies J.M. Dutertre 1, V. Beroulle
More informationECE520 VLSI Design. Lecture 2: Basic MOS Physics. Payman Zarkesh-Ha
ECE520 VLSI Design Lecture 2: Basic MOS Physics Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Wednesday 2:00-3:00PM or by appointment E-mail: pzarkesh@unm.edu Slide: 1 Review of Last Lecture Semiconductor
More informationDevelopment of a sampling ASIC for fast detector signals
Development of a sampling ASIC for fast detector signals Hervé Grabas Work done in collaboration with Henry Frisch, Jean-François Genat, Eric Oberla, Gary Varner, Eric Delagnes, Dominique Breton. Signal
More informationMP 4.3 Monolithic CMOS Distributed Amplifier and Oscillator
MP 4.3 Monolithic CMOS Distributed Amplifier and Oscillator Bendik Kleveland, Carlos H. Diaz 1 *, Dieter Vook 1, Liam Madden 2, Thomas H. Lee, S. Simon Wong Stanford University, Stanford, CA 1 Hewlett-Packard
More informationRELIABILITY ANALYSIS OF DYNAMIC LOGIC CIRCUITS UNDER TRANSISTOR AGING EFFECTS IN NANOTECHNOLOGY
RELIABILITY ANALYSIS OF DYNAMIC LOGIC CIRCUITS UNDER TRANSISTOR AGING EFFECTS IN NANOTECHNOLOGY A thesis work submitted to the faculty of San Francisco State University In partial fulfillment of The Requirements
More informationSynchronous Mirror Delays. ECG 721 Memory Circuit Design Kevin Buck
Synchronous Mirror Delays ECG 721 Memory Circuit Design Kevin Buck 11/25/2015 Introduction A synchronous mirror delay (SMD) is a type of clock generation circuit Unlike DLLs and PLLs an SMD is an open
More information8. Characteristics of Field Effect Transistor (MOSFET)
1 8. Characteristics of Field Effect Transistor (MOSFET) 8.1. Objectives The purpose of this experiment is to measure input and output characteristics of n-channel and p- channel field effect transistors
More information5.5: A 3.2 to 4GHz, 0.25µm CMOS Frequency Synthesizer for IEEE a/b/g WLAN
5.5: A 3.2 to 4GHz, 0.25µm CMOS Frequency Synthesizer for IEEE 802.11a/b/g WLAN Manolis Terrovitis, Michael Mack, Kalwant Singh, and Masoud Zargari 1 Atheros Communications, Sunnyvale, California 1 Atheros
More informationLaser attacks on integrated circuits: from CMOS to FD-SOI
DTIS 2014 9 th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Laser attacks on integrated circuits: from CMOS to FD-SOI J.-M. Dutertre 1, S. De Castro 1, A. Sarafianos
More informationAn 8-bit Analog-to-Digital Converter based on the Voltage-Dependent Switching Probability of a Magnetic Tunnel Junction
An 8-bit Analog-to-Digital Converter based on the Voltage-Dependent Switching Probability of a Magnetic Tunnel Junction Won Ho Choi*, Yang Lv*, Hoonki Kim, Jian-Ping Wang, and Chris H. Kim *equal contribution
More informationElectronic Circuits EE359A
Electronic Circuits EE359A Bruce McNair B206 bmcnair@stevens.edu 201-216-5549 1 Memory and Advanced Digital Circuits - 2 Chapter 11 2 Figure 11.1 (a) Basic latch. (b) The latch with the feedback loop opened.
More informationDesign of Sub-10-Picoseconds On-Chip Time Measurement Circuit
Design of Sub-0-Picoseconds On-Chip Time Measurement Circuit M.A.Abas, G.Russell, D.J.Kinniment Dept. of Electrical and Electronic Eng., University of Newcastle Upon Tyne, UK Abstract The rapid pace of
More informationphotonique et laser (COPL) Department of Electrical and Computer Engineering, Université Laval
-based noise suppression in spectrum sliced PONs: impact of bit rate and gain recovery time F. Vacondio, W.Mathlouthi,, P. Lemieux and L. A. Rusch Centre d optique d photonique et laser (COPL) Department
More informationThe Effect of Substrate Noise on VCO Performance
(RTU4A-1) The Effect of Substrate Noise on VCO Performance Nisha Checka, David D. Wentzloff, Anantha Chandrakasan, Rafael Reif Microsystems Technology Laboratory, MIT 60 Vassar St. Rm. 39-625 Cambridge,
More informationECEN 720 High-Speed Links: Circuits and Systems. Lab3 Transmitter Circuits. Objective. Introduction. Transmitter Automatic Termination Adjustment
1 ECEN 720 High-Speed Links: Circuits and Systems Lab3 Transmitter Circuits Objective To learn fundamentals of transmitter and receiver circuits. Introduction Transmitters are used to pass data stream
More informationCPE/EE 427, CPE 527 VLSI Design I CMOS Inverter. CMOS Inverter: A First Look
CPE/EE 427, CPE 527 VLSI Design I CMOS Inverter Department of Electrical and Computer Engineering University of Alabama in Huntsville Aleksandar Milenkovic CMOS Inverter: A First Look C L 9/11/26 VLSI
More informationA Study on the Characteristics of a Temperature Sensor with an Improved Ring Oscillator
Proceedings of the World Congress on Electrical Engineering and Computer Systems and Science (EECSS 2015) Barcelona, Spain July 13-14, 2015 Paper No. 137 A Study on the Characteristics of a Temperature
More informationMeasuring the degradation of microprocessors is tricky. Doing it better would unleash more processing power By JOHN KEANE, CHRIS H.
Page 1 of 5 SEMICONDUCTORS / PROCESSORS FEATURE Transistor Aging Measuring the degradation of microprocessors is tricky. Doing it better would unleash more processing power By JOHN KEANE, CHRIS H. KIM
More informationOptimization of Digitally Controlled Oscillator with Low Power
IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 5, Issue 6, Ver. I (Nov -Dec. 2015), PP 52-57 e-issn: 2319 4200, p-issn No. : 2319 4197 www.iosrjournals.org Optimization of Digitally Controlled
More informationOBSOLETE. High Performance, BiFET Operational Amplifiers AD542/AD544/AD547 REV. B
a FEATURES Ultralow Drift: 1 V/ C (AD547L) Low Offset Voltage: 0.25 mv (AD547L) Low Input Bias Currents: 25 pa max Low Quiescent Current: 1.5 ma Low Noise: 2 V p-p High Open Loop Gain: 110 db High Slew
More informationPicture. Parameter Unit Minimum Typical Maximum. Fin and Ref Input Frequency Range MHz 5 25 Input Power Level dbm
eatures requency Range: 5 to 25MHz Input Power: -3 to +17dBm Integrated Loop ilter Directly Interface to PS Series Directly Interface to VCO Series DC Power: 12V SMA Connector Picture is a Phase/requency
More informationf o Fig ECE 6440 Frequency Synthesizers P.E. Allen Frequency Magnitude Spectral impurity Frequency Fig010-03
Lecture 010 Introduction to Synthesizers (5/5/03) Page 010-1 LECTURE 010 INTRODUCTION TO FREQUENCY SYNTHESIZERS (References: [1,5,9,10]) What is a Synthesizer? A frequency synthesizer is the means by which
More informationSGM V Step-Up LED Driver
GENERAL DESCRIPTION The SGM3725 is a versatile constant current LED driver with a high efficiency step-up converter architecture. Unique technology and high 1.35A current limit allow SGM3725 to drive up
More informationModeling and Simulation Tools for Aging Effects in Scaled CMOS Design. Ketul Sutaria
Modeling and Simulation Tools for Aging Effects in Scaled CMOS Design by Ketul Sutaria A Dissertation Presented in Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy Approved December
More informationShort Channel Bandgap Voltage Reference
Short Channel Bandgap Voltage Reference EE-584 Final Report Authors: Thymour Legba Yugu Yang Chris Magruder Steve Dominick Table of Contents Table of Figures... 3 Abstract... 4 Introduction... 5 Theory
More information