Using a Wideband Digital Gain Control Amplifier with Linearity Improvement Technique for a Digital TV Tuner

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1 ISSN : 3-79 (Online) ISSN : (Print) Abstract A wideband digital gain control amplifier with linearity improvement technique for a digital TV tuner is presented herein. A linear optimization technique using two g3 parallel auxiliary tubes (the second derivatives of trans-conductance) to offset the g3 of the main amplifier circuit was proposed and the g3 of the entire circuit was reduced to a smaller value to effectively improve the linearity of the circuit. The single-ended differential circuit used in improving linearity was also analyzed. The digital control broadband amplifier implements a novel gain control method to achieve both a high dynamic gain control range and a high precision control step. The digital gain control amplifier achieved a high dynamic range of 55dB with a gain step of.8db. The noise figure was below 5.6dB throughout the entire control range, while the overall power consumption was less than 8.5mA. The die area was 8umx6um. Keywords Digital gain control amplifier, Linearity improvement technique, Derivative superposition method, Single-ended differential circuit I. Introduction With increasing demand for personal multimedia services, mobile digital TV applications are becoming increasingly popular [9]. There are a variety of mobile digital TV (DTV) standards, for example, China Mobile Multimedia Broadcasting (CMMB), South Korean digital multimedia broadcasting (DMB), Japan s Integrated Services Digital Broad-casting (ISDB-T) and the European Digital Video Broadcasting (DVB-H). The application of these standards makes it possible to watch TV in a mobile environment. Since different countries use different mobile terrestrial standards, there are various frequencies ranging from 7 to 87 MHz. To simplify the requirements of system design and be compatible with a variety of systems, a compatible low-cost UV-band RF receiver chip is extremely necessary. For the coverage range to extend to the UV bands at the interference signal, (which may be greater than the signal strength of the original signal) the RF front-end must be easily compatible with the system. Interference UV signals come from both the outside and inside of the signal band. While the interference outside the signal band can be filtered out using a RF SAW filter, the interference inside the signal band cannot be filtered out. The traditional method consists of using the channel selection filter [], (which is has a central frequency and is already aligned to receive the signal channel) so that the interference outside the signal channel can be filtered out. However, this requires a complex channel-select filter, which is quite complicated in mobile digital TV systems. A new approach to using the RF automatic gain control circuits [8] has become popular, in which the system automatically reduces gain on the front end to prevent signal block at the RF front-end. This allows the interference signal to be filtered out by the IF filter. IJECT Vo l., Is s u e 4, Oc t. - De c. Using a Wideband Digital Gain Control Amplifier with Linearity Improvement Technique for a Digital TV Tuner Xiaofeng He, Taishan Mo, 3 Chengyan Ma, 4 Tianchun Ye,4 Institute of Microelectronics, Chinese Academy of Science, Beijing, China,3 Hangzhou Zhongke Microelectronics Co. Ltd, Hangzhou, China In this approach, it is important to maximize the linearity of the circuit without sacrificing the noise figure. Many techniques for improving linearity have been suggested in technology. The feed-forward distortion cancellation was proposed to achieve a high IIP3 [-]. This technique requires accurate scaling between the input signals of the main and auxiliary gain stages. The post linearization technique improves the IIP3 by using the IMD sinker consisting of a PMOS. However, this method results in degradation of gain and extra power consumption [3]. To reduce the gain degradation and bias sensitivity, a derivative superposition method was proposed [4]. This method uses two or more parallel FETs of different widths and gate biases to achieve composite dc transfer characteristics, of which the third-order derivative is close to zero. However, previous linearity improvement techniques which utilized the derivative superposition method, described in [5] and [8], were only relevant for single-ended topology and underperformed during common-mode noise rejection. In this paper, we propose a RF digital gain amplifier for various terrestrial D-TV standards as a part of the direct conversion tuner IC shown in fig., in which the derivative superposition (DS) method was utilized. It employs multiple gated parallel (auxiliary) FETs of different widths and gate biases to achieve a composite DC transfer characteristic with an extended range in which the third order derivative is close to zero. This paper is organized as follows. Section I describes the system architecture of the proposed RF digital gain control amplifier. Section II presents the design of the circuits and section III reports the experimental results. Finally, section IV concludes the paper. In t e r n a t i o n a l Jo u r n a l o f El e c t r o n i c s & Co m m u n i c a t i o n Te c h n o l o g y 7 Vband 74~45 Uband Di gi t al cont r ol gai n ampl i f i er RF Power Detector 9 R F A G C c ont r ol L P F DCOC DCOC RF RSSI Fig. : Block diagram of the DTV system receiver B B - A G C II. System architecture Fig., shows the overall block diagram of the RF digital gain control amplifier including a single-ended differential circuit, a linearity improved amplifier and a buffer amplifier all configured by a switch. The input of the single-ended differential circuit connects with the output of the dual band LNA and this output connects the linearity improved amplifier whose output connects the buffer amplifier. The single-ended differential circuit covers a 4dB gain control range with 4- db steps. The linearity improved amplifier is divided into two parts, one achieves a db gain control range with 4-dB steps and the other achieves a 4.5dB gain control range with.5- db steps. The third stage buffer amplifier circuits provide a IP IN Q P Q N

2 IJECT Vo l., Is s u e 4, Oc t. - De c..6db gain control range with.8db steps. To insure that the gain step has full coverage, without risk of compression during processing /temperature variations, the dynamic range of the post circuit is larger than the minimum step of the pre-circuit. single-ended differential circuit L R6 V DD L R7 The linearity improved amplifier buffer amplifier ISSN : 3-79 (Online) ISSN : (Print) ideas of optimum biasing (which is to bias the transistor at the sweet spot of g3=) have been presented []. However, this method is very sensitive to processing and temperature variations. To reduce the IIP3 sensitivity to bias, the derivative superposition (DS) method was recommend [4]. The biggest difference between the DS method and the optimum biasing [] method is that the DS method employs auxiliary circuits parallel to the main amplifier to achieve a composite DC transfer characteristic with an extended range in which the third order derivative is close to zero. R3 x -3 x -3 R4 I (A) R Fig. : Block of the digital control RF wideband amplifier II. Circuits Design The linearity improved amplifier Main Amplifier Auxiliary Amplifier Auxiliary Amplifier 8 International Journal of Electronics & Communication Technology Vout Fig. 3: Proposed dual-auxiliary-path feed forward linearization technique A. The proposed linearity improved different circuit The CG-Amplifier inherently has less drain-to-gate feedback than the CS-Amplifier since its gate is ac grounded; therefore the CG-Amplifier usually has better linearity [6]. However, the CS-Amplifier usually applies its linearity via a differential which makes it susceptible to common-mode noise immunity [3]. Third order intermodulation mainly originates from the nonlinearity of the FET I-V characteristic. The inter-modulation can be expressed using a Taylor series expansion in tandem with a quiescent bias point as: 3 ids = gvgs + gvgs + g3vgs () Where g, and 3 are the linear gain and the second/third-order nonlinearity coefficients of the amplifier. The derivative dc I-V characteristics of a simple fully differential amplifier are shown in fig. 4, For greater linearity, a simple solution is implemented to increase Vgs in saturation. However, Vgs is limited to the vicinity of.7v when taking power consumption and gain increase into consideration. Around this voltage, the third-order coefficient g3 has a negative hump and is at its worst value. Thus, it is hard to obtain a high linearity using this topology alone. Some Fig. 4: The differential current, G, g, g3 change with differing voltage in the traditional differential circuit In this paper, a novel derivative superposition method (shown in fig. 3) is proposed, which implements dual auxiliary circuits parallel to the main amplifier. The first auxiliary circuit is the pseudo-differential amplifier in which the MOS is biased in subthreshold region. The g3 in the pseudo-differential amplifier is positive, which means that this feature can be used to offset the negative g3 in the main amplifier. The differential currents, g, g, and g3 of the traditional differential amplifier and those of the pseudo-differential amplifier are shown in fig. 5, from which we can see that the g3 can be improved slightly. However, weakinversion transistors being turned on and off at large voltage swings add higher-order harmonic components to the circuit and make it hard to suppress the g3 of the main amplifier to a significant value. I (A) x Fig. 5: How the differential currents, g, g, g3 change with differing voltages in the differential circuit when adding a pseudo-differential amplifier

3 ISSN : 3-79 (Online) ISSN : (Print) IJECT Vo l., Is s u e 4, Oc t. - De c. To overcome the pseudo-differential amplifier deficiency, the cascade differential amplifier works in the triode region to exploit the power amplifier [3]. The whole circuit is shown in fig. 6, and the gain is altered by changing the main input via FET Ma and Mb. Vb R Ma VDD R Mb The mai n ampl i f i er Vb GM 3 (AV ) GM 3 (AV ) GM 3 (AV ) Ibias M Vb M5 M6 M Voutp Voutn Vb Vip Vip The Auxi l i ar y ampl i f i er The Auxi l i ar y ampl i f i er Fig. 8: The comparison of g3 changing with differing input voltage in three different circuits When drain voltage swing is small at a low load resistance, trans-conductance is the dominant nonlinear source. At a high load resistance, however, the output conductance is another important contribution to the nonlinear function []. To have different output conductance impacts the circuit performance, so the output third-order intercept point (OIP3) and power gain for a source resistance were calculated. The results are depicted in fig. 9. Because the IIP3 does not change linearly with output load, the best linearity is achieved at a load resistance of 4, while the power gain is low. In order to reach a compromise between power gain and IIP3, we chose a load resistance of 6. Vb Vb M3 M4 Vip Fig. 6: Entire proposed linearity improved differential circuit As shown in fig.6, biasing the FET M, M, M3 and M4 with the same voltage (which is also the bias voltage of the main amplifier s FET), the FET M may be forced into the triode region. To better understand the combination of the three circuits, the differential current and g, g, and g3 of the whole circuit are shown in fig. 7. Comparison between the original values in fig. 5, and the g3 values of fig. 7, is shown in the fig. 8. From this comparison, we can see that the g3 is much closer to zero while the gand the gain does not change. Although a dual auxiliary amplifier is introduced, it consumes less extra power in this case. I (A) x db (db) Ω Load Res ( ) Fig. 9: Gain and the db compression point change during load resistance IV. Single-ended differential circuits Single-ended differential circuits are configured using a switch and consist of three resistor attenuation circuits. These three circuits turn four identical single-ended differential amplifiers. To cover the dynamic range of 4dB with 4-dB steps, the gain can be configured by pre-setting R3, R4, and R5 resistor values to achieve a different attenuation. The multiple amplifiers use the same amplifier for each cell as shown in fig.. GAIN (db) Fig. 7: The differential current, g, g, and g3 change with differing input voltage in the proposed differential circuit In t e r n a t i o n a l Jo u r n a l o f El e c t r o n i c s & Co m m u n i c a t i o n Te c h n o l o g y 9

4 IJECT Vo l., Is s u e 4, Oc t. - De c. ISSN : 3-79 (Online) ISSN : (Print) VDD V DD L L VINP C M SW M SW M3 SW3 M4 VOUTN R3 R4 VOUTP Bias R R R3 R4 VOUTP Bias R M M Bias M5 Bias VIN C M3 R C Fig. : Block of the basic signal to a different circuit This single amplifier combines a common source (CS) and common gate (CG) configuration of the amplifier and can convert single or differential systems without using off-chip balun. Also, CG configuration can provide wideband input matching impedance. To extend the bandwidth, inductive shunt peaking [9] is applied. The most important reason to choose this configuration is that nonlinearity is canceled out by this configuration. To better understand this approach, the drain source current i ds is modeled. 3 4 i = gv + gv + gv + gv + = gv + gh () ds gs gs 3 gs 4 gs gs Where g is the i-order nonlinearity coefficient of the amplifier i and gh contains all unwanted nonlinear terms. Also, the input voltage v in the (linear) source resistor can be modeled by the source signal; 3 4 v = gv s + gv s + gv 3 s + gv 4 s + = gv s + gh (3) The output voltage of the CG-stage (see Fig. ) and the CSstage can be written as vcg = ( vs v) RCG / RS = (( g) vs gh) RCG / R (4) S vcs = ( v) RCG / RS = ( g vs + gh) RCG / RS (5) The difference in signs between the wanted signal and the unwanted signal in (4) and (5) can be exploited; after subtraction only the linear signal remains vout = vcg vcs = vs RCG / RS (6) From the formula we have the v out which is solely related to the source voltage. The distortion currents generated by the CG-transistor can be canceled, regardless of whether they were produced due to nonlinearity of the trans-conductance or nonlinearity of the output conductance. Fig. : Block of the output drive circuit As shown in the fig., the input stage is constituted of M, M, M3 and M4, while Vbias provides the bias voltage. M5 is the FET bias to provide the tail current, whose bias voltage is Vbias. The M, M3, and M4 are selected by the switches SW, SW, and SW3. In order to achieve.8db steps accurately, the gain is determined by the ratio of the transistor s size. When M is accessible to the circuit, the gain of the circuit can be formulated as follow: // RL gm gm kw kw W W W AV = = = = // R / gm gm kw kw W W W L + g m g m W W log( ), when W >> W W W (7) Where the gm and gm refer to the trans-conductance of the M and M and RL is the load of the circuit. W and W stand for the width of the M and M respectively. From the formulator we have, the gain can be changed by differing the input tube. To realize db-linear precision, we can change the tubes in parallel with the M tube size. V. Measurement Results The wideband digital gain control amplifier circuit is fabricated during the.8um single-poly six-metal process. fig. shows the microphotograph of the fabricated chip. The singleended differential circuit, the linearity improved and the output drive circuit are enlarged in the small block diagrams. All of the testing results below are under the condition that the chip is packaged with packaging and all pins are protected by an ESD protection circuit. Single-ended differential circuit A. The output drive circuit The output drive stage should have a small output impedance to deliver output voltage effectively to the next block and to protect fine gain resolution. To ensure that the linearity of the entire circuit is not affected, the following source was chosen to produce fine gain resolution. The output drive circuit The linearity improved amplifier Fig. : The die micrograph International Journal of Electronics & Communication Technology

5 ISSN : 3-79 (Online) ISSN : (Print) The total current consumption of the wideband digital gain control amplifier is 8.5mA when the wideband digital gain control amplifier is powered by a.8v power supply. Therefore, the total power consumption is only 5.3mW. IJECT Vo l., Is s u e 4, Oc t. - De c. Fig. 4, shows the measurement result of a two-tone intermodulation test of the proposed linearity improved differential circuit. The input power is -45dBm, while the input frequencies are 53.5MHz and 533.5MHz. The difference between the fundamental wave and the third order intermodulation distortion is about 6dB. fig. 5, depicts this method using a two-tone test under input frequency of 533MHz. The IIP3 of the test results, which can be seen from the figure, can reach -4dBm, when the circuit is configured at maximum gain. The noise fig. testing result is shown in fig. 6, when the circuit is configured at its maximum gain, and compared with simulation results. As shown in the fig, compared to simulation, the noise figure in testing increased significantly due to the on-board noise and digital interference. Testing results show that the optimal noise figure at low frequencies is around 4.3dB, while the full band frequency is lower than 5.6dB. 6 Fig. 3: The S testing result at maximum gain Input return loss (S) is measured and plotted in fig. 3, while the circuit is configured at the maximum gain, from which we can see that the input return loss is below -db over the whole bandwidth. Noise figure (db) Meas ure S imulation Frequency [MHz] 6dB Fig. 6: The comparison of noise figures between testing and simulation Fig. 7, shows the circuit gain and IIP3 change with the digital control signal while the input frequency is 533MHz. The gain that can be seen from the figure changes as the digital control is reduced from 3dB to-5db and the gain dynamic range is 55dB with a step accuracy of.8db and an IIP3 change from- 4dBm to 4dBm. Fig. 4: Measurement result of the two-tone intermodulation test G ain IIP 3 POUT (db) - -4 GAIN (db) IIP3 (dbm) - IIP3=-4dBm - -6 st Order 3st Order PIN [db ] Fig. 5: The IIP3 testing result at maximum gain control counter (bit) Fig. 7: The changing input IIP3 and gain of the circuit with the digital control In t e r n a t i o n a l Jo u r n a l o f El e c t r o n i c s & Co m m u n i c a t i o n Te c h n o l o g y

6 IJECT Vo l., Is s u e 4, Oc t. - De c. The overall wideband digital gain control amplifier performance is summarized in Table. Table : the overall performance of the proposed digital gain control amplifier Parameters Specifications Units Technology.8 μm Die Area.48 mm Supply Voltage.8 V Current Consumption 8.5 ma NF 5.6 db Max gain 3 db Gain Tuning Range/step 55/.8 db IIP3-4 dbm Frequency 74~9 MHz A comparison of the proposed wideband digital gain control amplifier with designs published in the past is provided in Table. As shown in Table II the proposed wideband digital gain control amplifier uses the linearity improvement technique to significantly improve system linearity and provide -4dBm under a maximum gain of 3dB compared with the previous configuration which has a similar IIP3 but a much larger gain. Moreover, the proposed circuit consumes the least power by using the same IIP3. Table : performance comparison of the proposed and previously reported digital gain control amplifiers Ref. [5] [4] [] [7] This work Process (μm) SiGe.8 International Journal of Electronics & Communication Technology.8 IIP3(dBm) Bandwidth (MHz) Noise Figure Power (mw) Max gain(db) Dynamic Range(dB)/ gain step Die area ( mm ) (*) not found [86,96] [,9] [4,9] [47,87] [74,9] * 4/ 6/3 6/ VI. Conclusions This paper proposes a wideband digital gain control amplifier with linearity improvement technique for a digital TV tuner. A linearity improvement technique based on the derivative superposition method is used with two auxiliary amplifiers and the load resistance is optimized to enlarge the whole circuit IIP3. An IIP3 larger than -4dBm was achieved, and the maximum ISSN : 3-79 (Online) ISSN : (Print) gain was found to be greater than 3dB. Moreover, to cover a wide gain range with fine step resolution over a wide frequency range, new gain control methods were proposed and verified by measurement. The whole digital gain control amplifier achieved a 55dB dynamic range with a.8db gain step. The noise figure over the whole control range was less than 5.6dB, while the overall power consumption was less than 8.5mA with a die area of 8umx6um. References [] D. Yongwang, R. Harjani, "A +8 dbm IIP3 LNA in.35 μm ", in Solid-State Circuits Conference,. Digest of Technical Papers. ISSCC. IEEE International,, pp. 6-63, 443. [] K. Wang, Z. Wang, "A broadband noise-canceling differential LNA for 5-86MHz TV tuner", in Microwave and Millimeter Wave Technology, 8. ICMMT 8. International Conference on, 8, pp [3] W. Zhuo, et al., "A capacitor cross-coupled common-gate low-noise amplifier", Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. 5, pp , 5. [4] I. Donggu, et al., "A Active Feedback Balun-LNA With High IIP for Wideband Digital TV Receivers", Microwave Theory and Techniques, IEEE Transactions on, vol. 58, pp ,. [5] G. Retz, P. Burton, "A up-conversion receiver frontend for cable and terrestrial DTV applications", in Solid- State Circuits Conference, 3. Digest of Technical Papers. ISSCC. IEEE International, 3, pp vol.. [6] I. Umoh, T. Ogunfunmi, "Digital post-linearization of a Wideband Low Noise Amplifier for ultra-wideband wireless receivers", in Circuits and Systems (ISCAS), IEEE International Symposium,, pp [7] S. Azuma, et al., "A digital terrestrial television (ISDB-T) tuner for mobile applications", in Solid-State Circuits Conference, 4. Digest of Technical Papers. ISSCC, IEEE International, 4, pp Vol.. [8] E. Keehr, A. Hajimiri, "Equalization of IM3 Products in Wideband Direct-Conversion Receivers", in Solid-State Circuits Conference, 8. ISSCC 8. Digest of Technical Papers. IEEE International, 8, pp [9] B. Kim, et al., "Highly linear RF MMIC amplifier using multiple gated transistors and its Volterra series analysis", in Microwave Symposium Digest, IEEE MTT-S International,, pp vol.. [] K. Tae Wook, et al., "Highly linear receiver front-end adopting MOSFET transconductance linearization by multiple gated transistors", Solid-State Circuits, IEEE Journal of, vol. 39, pp. 3-9, 4. [] K. Namsoo, et al., "A Highly Linear SAW-Less Receiver Using a Mixer With Embedded Tx Filtering for CDMA", Solid-State Circuits, IEEE Journal of, vol. 44, pp. 6-37, 9. [] K. Sanghoon, et al., "Linearity analysis of for RF application", in Radio Frequency Integrated Circuits (RFIC) Symposium, IEEE, pp [3] S. Tanaka, et al., "A Linearization Technique For RF Power Amplifiers", in VLSI Circuits, 997. Digest of Technical Papers., 997 Symposium, 997, pp [4] X. Chunyu, E. Sanchez-Sinencio, "A linearization technique for RF low noise amplifier", in Circuits and Systems,

7 ISSN : 3-79 (Online) ISSN : (Print) 4. ISCAS '4. Proceedings of the 4 International Symposium, 4, pp. IV-33-6 Vol.4. [5] S. Lou, H. C. Luong, "A Linearization Technique for RF Receiver Front-End Using Second-Order-Intermodulation Injection", Solid-State Circuits, IEEE Journal of, vol. 43, pp. 44-4, 8. [6] Z. Heng, et al., "Linearization Techniques for Low Noise Amplifiers: A Tutorial", Circuits and Systems I: Regular Papers, IEEE Transactions, vol. 58, pp. -36,. [7] Z. Heng, et al., "A Low-Power, Linearized, Ultra-Wideband LNA Design Technique", Solid-State Circuits, IEEE Journal, vol. 44, pp. 3-33, 9. [8] V. Aparin, L. E. Larson, "Modified derivative superposition method for linearizing FET low noise amplifiers", in Radio Frequency Integrated Circuits (RFIC) Symposium, 4. Digest of Papers. IEEE, 4, pp [9] L. Min, et al., "A novel IP3 boosting technique using feedforward distortion cancellation method for 5 GHz LNA", in Radio Frequency Integrated Circuits (RFIC) Symposium, IEEE, 3, pp [] B. Toole, et al., "RF circuit implications of moderate inversion enhanced linear region in MOSFETs", Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 5, pp , 4. [] D. R. Huang, et al., "A 4~9MHz Broadb and Differential LNA with Gain-Control for DTV RF Tuner", in Asian Solid-State Circuits Conference,5, pp IJECT Vo l., Is s u e 4, Oc t. - De c. and mixed-signal integrated circuits and system design. Tian-chun Ye received his B.S. degree in Electronics circuits and systems from Shanghai Fu dan University, Shanghai, China, in 985. His research interests include integrated circuit design and nano-processing and manufacturing technology. Xiao-feng He received his B.S. degree in Electronic Information Science and Technology from University of Electronic Science and Technology of China, Chengdu, China, in 7, and working for the Ph.D. degree in Microelectronics and Solid State Electronics from Institute of Microelectronic of Chinese Academy of Sciences, Beijing, China. His research interests include wide band low noise amplifier and automatic gain control circuit. At present, He is engaged in high speed analog to digital circuit design. Tai-shan Mo received his B.S. degree in Microelectronics from Tianjin University, Tianjin, China, in, the M.S. degree in Microelectronics from Tianjin University, Tianjin, China, in 5, and received his Ph.D degree in Microelectronics and Solid State Electronics from Institute of Microelectronic of Chinese Academy of Sciences, Beijing, China, in 7. His research interests include new semiconductor devices research and analog circuit design. Cheng-yan Ma received his B.S. degree in Electronics circuits and systems from Shanghai Jiao Tong University, Shanghai, China, in 986, and received the M.S. degree in Microelectronics from Dalhousie University, Nova Scotia, Canada, in 4. His research interests include RF, analog In t e r n a t i o n a l Jo u r n a l o f El e c t r o n i c s & Co m m u n i c a t i o n Te c h n o l o g y 3