Int. J. Electron. Commun. (AEU)

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1 Int. J. Electron. Commun. (AEÜ) 64 (2010) Contents lists available at ScienceDirect Int. J. Electron. Commun. (AEU) journal homepage: LETTER Linearization technique using bipolar transistor at 5 GHz low noise amplifier A.I.A. Galal, R.K. Pokharel, H. Kanaya, K. Yoshida Graduate School of Information Sciences and Electrical Engineering, Kyushu University, Motooka 744, Nishi-ku, Fukuoka , Japan A R T I C L E I N F O A B S T R A C T Article history: Received 18 February 2009 Accepted 16 July 2009 Keywords: Low noise amplifier (LNA) RF integrated circuits Nonlinearity Third-order input intercept point (IIP3) High linearity A CMOS low noise amplifier (LNA) used in wireless communication systems, such as WLAN and CDMA, must have low noise figure, high linearity, and sufficient gain. Several techniques have been proposed to improve the linearity of CMOS LNA circuits. The proposed low noise amplifier achieves high third-order input intercept point (IIP3) using multi-gated configuration technique, by using two transistors, the first is the main CMOS transistor, and the second is bipolar transistor in TSMC 0.18 m technology. Bipolar transistor is used to cancel the third-order component from MOS transistor to fulfill high linearity operation. This work is designed and fabricated in TSMC 0.18 m CMOS process. At 5 GHz, the proposed LNA achieves a measurement results as 16 dbm of IIP3, 10.5 db of gain, 2.1 db of noise figure, and 8 mw of power consumption Elsevier GmbH. All rights reserved. 1. Introduction Low noise amplifier (LNA) is the first stage of a transceiver system, which has the main effects on the performance of signal to the remaining stages. The specification of LNA must be satisfied the following, high gain, low noise figure, good matching, low power consumption, low cost, and also high linearity. LNA designers always adopt two mode design strategy to achieve all of the above goals, one is high gain, low noise figure, but low linearity for small desired signal with small interference and another is low gain, high linearity but high noise figure for large desired signal with large interference [1]. Theoretically, the responsible of third-order nonlinearity in MOSFET transistor is the third-order derivative of dc transfer characteristic. The dc transfer characteristic of the thirdorder derivative changes from positive to negative in the moderate inversion region [2]. Several techniques are used to achieve highly linearity LNA depend on how to cancel the third-order derivative. Optimum biasing technique is based on bias the transistor in moderate inversion region at zero crossing point, the transistor achieves high linearity but the bias point bound to change due to process variation. The feed-forward technique is the common topology to get high linearity, and it used in different forms. In [3] the output is taken as the difference of two amplifiers whose inputs are scaled to obtain zero third-order distortion. The other type is used for amplifiers, one biased in strong inversion, and the other biased at weak inversion, the negative peak of a third-order derivative of the first Corresponding author. Tel./fax: address: Galal@yossvr3.ed.kyushu-u.ac.jp (A.I.A. Galal). amplifier is canceled by the positive peak of the second amplifier. The negative feedback technique also is popularly adopted to improve linearity, but it cannot be easily performed at RF frequency due to stability consideration. The basic idea of linearization is to use additional transistor's nonlinearity to compensate or cancel the nonlinearity of a main operation device. The conventional way involves MOS transistors working in triode or weak inversion to provide linearization. Bipolar is available in CMOS technology, it is sufficient to be in linearization [4]. In this paper, a linearization technique is derived from multi-gated linearization by using bipolar transistor and also by using NMOS transistor. Comparison between two cases is presented at the end of this paper. 2. Linearization technique The nonlinearity of a MOS transistor arises from its voltage to current characteristic, which can be described with the power series as following: I D = G m1 V gs + G m2 Vgs 2 + G m3vgs 3 + (1) where G m1 is the main trans-conductance, G m2 represents its second nonlinearity obtained by the second-order derivative, and G m3 is the third-order derivative. The input third-order intercept point of a nonlinear device is 4 IIP3 = G m1 3 G (2) m3 The value of IIP3 is maximum if the value of G m3 is minimum. Our goal is how to minimize the value of G m3 to provide high linearity /$ - see front matter 2009 Elsevier GmbH. All rights reserved. doi: /j.aeue

2 A.I.A. Galal et al. / Int. J. Electron. Commun. (AEÜ) 64 (2010) VDD V Bias2 L4 C2 R2 C3 RF Output L3 M2 RF Input L1 C1 M1 R3 R1 V Bias1 L2 Fig. 3. LNA using bipolar transistor. Fig. 1. MOSFET dc transfer characteristics. IN L1 VDD C1 C2 L3 OUT M1 M2 R1 V B1 DC V OFF DC R2 L2 Fig. 4. Microphotograph of LNA. Fig. 2. Derivative superposition method. The coefficient of (1) can given by G 1 = I D V gs, G 2 = 2 I D 2 Vgs 2, G 3 = 3 I D 6 Vgs 3 (3) From the dc transfer characteristics shown in Fig. 1 the third-order derivative of MOSFET transistor changes from positive to negative at moderate inversion region. The derivative superposition technique [5] is shown in Fig. 2 use two transistors M1 and M2. M2 is biased at strong inversion region while its G m3 is negative and M1 is biased at weak inversion region while its G m3 is positive. Prober biasing for M1 and M2 are used to

3 980 A.I.A. Galal et al. / Int. J. Electron. Commun. (AEÜ) 64 (2010) Fig. 5. Measurement of IIP3 using bipolar transistor. Fig. 8. IIP3 using NMOS. Fig. 6. Input and output return loss. Fig. 9. S parameters and noise figure using NMOS. 3. Circuit design Fig. 3 shows the circuit topology of the proposed LNA. It consists of the main operation NMOS transistor M1, and an auxiliary bipolar transistor M2. M1 is biased at strong inversion region while its G m3 given as follows: ( ) 1 μ 2 o C W ox L θ G m3 = (1 + θ(v gs0 V th )) 4 (4) where μ o is the mobility, C ox is the gate capacitance per unit area, θ is the normal field mobility degradation factor, and Vgso is the gate source dc bias voltage. The IM3 coefficient of bipolar transistor can be approximated by Fig. 7. Gain and noise figure. α 3 = I soe V BEQ / t 6 3 t (5) get maximum cancelation of third-order derivative and obtain high linearity, but this technique suffers from worse noise figure and low gain. In the proposed technique, power constrained simultaneous noise and input matching are adopted to fulfill minimum noise figure in input stage of LNA. where I so is the saturation current, and V BEQ is the base-emitter bias voltage. From (4) and (5) it appears that the sign of G m3 and α 3 is opposite. To get maximum cancelation of third-order term; the magnitude of α 3 and G m3 must be equal. The third-order term of bipolar transistor is usually more than G m3 of MOS transistor. Emitter resistance is used to optimize the value of α 3 to achieve high linearity.

4 A.I.A. Galal et al. / Int. J. Electron. Commun. (AEÜ) 64 (2010) Table 1 Comparison with other published work. Work Freq. (GHz) S11 (db) NF (db) S21 (db) Power (mw) IIP3 (dbm) Technology [8] 0.8, m CMOS [9] m CMOS [10] m CMOS This work (bipolar) m CMOS This work (NMOS) m CMOS The LNA shown in Fig. 3 was fabricated in TSMC 0.18 m CMOS technology. The microphotograph of the fabricated LNA is shown in Fig. 4. The LNA was tested for linearity by the two tone tests. The two tone frequencies were chosen as 5 and 5.01 GHz and Fig. 5 illustrates the measurement of third input intercept point IIP3 of the implemented high linearity LNA. It can be seen that the IIP3=16 dbm. Fig. 6 shows the input and output return loss as S11 is 15.9 db and S22 is 15.8 db. The gain is 10.5 db, and noise figure is 2.1 db are presented in Fig. 7. For comparison NMOS transistor is used instead of bipolar transistor for linearization. Fig. 8 shows the input third-order nonlinearity as IIP3 = 9 dbm. Gain, input matching, output matching, and noise figure are presented in Fig. 9. When using NMOS transistor to obtain linearity, one transistor is biased at weak inversion region so this transistor degrade the gain and noise figure of the LNA due to its high gate induced current noise getting added to the input [6]. Also the effect of frequency dependent second-order nonlinearity [7] degrades the linearity and less improvement is obtained. Moreover the alignment of positive and negative peaks of third-order nonlinearity is very sensitive due to process and temperature variations. High linearity amplifier circuits always dissipate large amount of power. Recently all devices go to be portable which need low power consumption to increase the battery life. The power dissipation in this technique by using bipolar transistor is only 8 mw. Therefore the linearization technique presented in this paper has high IIP3, low noise figure, sufficient gain and low power consumption. Table 1 presents comparison between using bipolar transistor as linearization device and other techniques presented in published papers. It is appeared from Table 1 that the proposed technique has high IIP3 more than other published papers except [8] has the same IIP3 but the noise figure is high and the power consumption is more than twice of the proposed technique. Acknowledgments This work was partly supported by a grant of Knowledge Cluster Initiative implemented by Ministry of Education, Culture, Sports, Science and Technology (MEXT) and KAKENHI. This work was also partly supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with CADENCE Corporation and Agilent Corporation. References [1] Lin M, Li Y, Chen H. A novel IP3 boosting technique using feedforward distortion cancellation method for 5 GHz CMOS LNA. Analog Integrated Circuits and Signal Processing 2006; [2] Ganesan S, Sanchez S, Martinez JS. A highly linear low noise amplifier. IEEE Transactions on Microwave Theory and Techniques 2006;54: [3] Ding Y, Harjani R. A+ 18 dbm IIP3 LNA in 0.35 μm CMOS. In: 2001 IEEE international solid-state circuits conference, Digest of technical papers, ISSCC, p [4] Xin C, Sinencio ES. A linearization technique for rf low noise amplifier. Proceedings of the 2004 International Symposium on Circuits and Systems, p [5] Kim T, Lee K. Highly linear receiver front-end adopting MOSFET transconductance linearization by multiple gated transistors. IEEE Journal of Solid-State Circuits 2004; [6] Aparin V, Larson L, Inc Q, San Diego C. Modified derivative superposition method for linearizing FET low-noise amplifiers. IEEE Transactions on Microwave Theory and Techniques 2005; [7] Fairbanks J, Larson L. Analysis of optimized input and output harmonic termination on the linearity of 5 GHz CMOS radio frequency amplifiers. In: Radio and wireless conference, 2003, RAWCON'03. Proceedings, p [8] Chen W, Liu G, Zdravko B, Niknejad A. A highly linear broadband CMOS LNA employing noise and distortion cancellation. IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2007; p [9] Aparin V, Brown G, Larson L, Inc Q, San Diego C. Linearization of CMOS LNA's via optimum gate biasing. In: Proceedings of the 2004 international symposium on circuits and systems, 2004, ISCAS'04, [10] Liao H, Lu Y, Deng J, Chiou H. Feed-forward correction technique for a high linearity WiMAX differential low noise amplifier. In: IEEE international workshop on radio-frequency integration technology, RFIT 007, p Ahmed I.A. Galal received the B.Sc. and M.Sc. degrees in electrical engineering from Minia University, Egypt, in 1995 and 2003, respectively. Since 2008, he has been working toward the Ph.D. degree in electronics engineering at Graduate School of Information Science and Electrical Engineering, Kyushu University, Japan. From 2003 to 2007 he was an assistant lecture in Minia University, Egypt, and from October 2007 to March 2008, he was a research student in Electronics Department, Kyushu University, Japan. His research interest is in analog RF front end transceiver for ultra-wide band systems. Ramesh K. Pokharel received the M.E. and Doctorate degrees from the University of Tokyo, Japan, in 2000 and 2003, respectively, all in electrical engineering. He had short academic and industrial experiences in Nepal before he joined the University of Tokyo in 1997 as a research student. He had been a post-doctoral research fellow with the Department of Electrical Engineering and Electronics, Aoyama Gakuin University, Japan, from April 2003 to March In April 2005, he joined the Department of Electronics, Graduate School of Information Science and Electrical Engineering, Kyushu University where he is currently an assistant professor. His current research interests include the employment of passive components such as CPW in RF CMOS system LSI, EMC and signal integrity issues of LSI, and low-noise and high linear RF front-end architectures. He is a member of the IEEE. Dr. Pokharel was a recipient of the Monbu-Kagakusho Scholarship of the Japanese Government ( ) and an excellent COE research presentation award from the University of Tokyo in Haruichi Kanaya was born in Yamaguchi, Japan, in He received the B.S. (Physics) degree from Yamaguchi University in 1990, and the M.E. (Applied Physics) and D.E. degrees from Kyushu University in 1992 and 1994, respectively. In 1994, he became a Research Fellow (PD) of the Japan Society for the Promotion of Science. In 1998, he was a visiting scholar at the Massachusetts Institute of Technology (MIT), USA. He is currently engaged in the study and design of RF CMOS system LSI and superconducting microwave devices, as an associate professor in the Department of Electronics, Graduate School of Information Science and Electrical Engineering, and also System LSI Research Center, Kyushu University. Dr. Kanaya is a member of the Institute of Electrical and Electronics Engineers (IEEE).

5 982 A.I.A. Galal et al. / Int. J. Electron. Commun. (AEÜ) 64 (2010) Keiji Yoshida was born in Fukuoka, Japan, in He received the B.E., M.E. and Dr. Eng. degrees from Kyushu University in 1971, 1973 and 1978, respectively. He is currently engaged in the study of applications of superconducting thin films to microwave and optical devices and design of RF-LSI chips for SoC, as a professor in the Department of Electronics, Graduate School of Information Science and Electrical Engineering, Kyushu University. Dr. Yoshida is a member of the Institute of Electrical and Electronics Engineers (IEEE) and the Japan Society of Applied Physics.