i.mxrt1050 Migration Guide Migrating from silicon Rev A0 to Rev A1
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1 NXP Semiconductors Document Number: AN12146 Application te Rev. 1, 05/2018 i.mxrt1050 Migration Guide Migrating from silicon Rev A0 to Rev A1 Contents 1. Introduction 1.1. Purpose This Application te is a migration guide for i.mxrt1050 users that are migrating from silicon Rev. A0 to Rev. A1. 1. Introduction Purpose Scope Reference Summary Revision history Scope This document provides differentiation from hardware and software scope. For details on A0, A1 part number and decoder, refer to Table 1. For all users, suggest to use A1 silicon for own board design. For those who are evaluating i.mxrt1050 with EVKA board, please refer to the summary table for SW and HW changes. For those who will evaluate i.mxrt1050 with EVKB board, suggest to use latest SDK with workaround listed in summary table. NXP Semiconductors 1
2 A0, A1 part number and decoder Rev A0 Rev A1 MIMXRT1052CVL5A MIMXRT1052CVL5B Part number MIMXRT1052DVL6A MIMXRT1052DVL6B MIMXRT1051CVL5A MIMXRT1051CVL5B MIMXRT1051DVL6A MIMXRT1051DVL6B Board name MIMXRT1050-EVK IMXRT1050-EVKB 1.3. Reference For RT1050 reference manual, datasheet and all support docs please refer to below link: 2. Summary Summary table Category For silicon A0: Power ERR IO: fix the issue that high POR current if NVCC_GPIO/EMC is powered ahead of VDD_SOC_IN 1. DCDC_IN need powered together or ahead of SNVS power domain. 2. DCDC_IN need to be at 2.8V~3.0V. 3. DCDC_PSWITCH not working. ERR DCDC: fix the issue that normal power up sequence may result in DCDC startup failure For silicon A1, recommend customer to modify HW board as below: 1. DCDC_IN powered together with another IO domain (IMXRT1050- EVKB: DNP R42, populate R25). NXP Semiconductors 2
3 Category Interface ERR GPIO new feature ERR DCDC: Fix the issue that unexpected DCDC reset occurs on some chips Giada bit wise set/clear/toggle function LCDIF: LUT consecutive programming may fail in case two writes are close 2. SNVS power support options: 1)SNVS power ahead of other power domains by dedicated LDO( IMXRT1050-EVKB: populate R34,DNP R354 by default). 2)SNVS power together with other power domain if SNVS mode is not necessary( IMXRT1050- EVKB: DNP R34,R38 and U5,populate R354 and R35). 3.DCDC_PSWITCH should be 1ms behind DCDC_IN( IMXRT1050- EVKB: change R32 from 0 to 30Kohm). 4.DCDC_IN change to 3.3V instead of 3.0V( IMXRT1050-EVKB: change R305 from 402K to 464K ). Release GPIO bit set/clear/toggle API Remove software workaround in SDK Memory Cache improvement SEMC FLEXSPI OCRAM SOC:OCRAM, FlexSPI, SEMC can't response CM7 cache speculative read when their clock is turned off CCM: add bit filed to control semc_exsc clock, must be enabled always CCM: add bit filed to control flexspi_exsc clock, must be enabled always CCM: add bit filed to control ocram_exsc clock, must be enabled always For A1 silicon, customer must keep below register field: SEMC:CCM_CCGR1 CG9(semc_exsc clock) need to be 2'b11 as default from reset FLEXSPI:CCM_CCGR0 CG3(flexspi_exsc clock) need to be 2'b11 as default from reset OCRAM:CCM_CCGR2 CG0(ocram_exsc clock) need to be 2'b11 as default from reset NXP Semiconductors 3
4 Category Others Chip ID Changed from 1.0 to 1.1 ERR ERR ERR ERR ERR ERR ERR ADC: ADC_ETC fails to clear the ADC_ETC request signals automatically after receiving DMA ack Chip stuck in reset when RTWOG low byte test mode is enabled SNVS: Invalid ECC check failure System Boot: SEMC NOR boot cannot support the signed image authentication under HAB closed mode System Boot: FlexSPI NOR encrypted XIP boot fails after system reset if the FAC region number is less than 2 System Boot: FlexSPI NOR encrypted XIP boot fails after system reset if the IOMUXC_GPR18 to IOMUXC_GPR21 are locked Internal BCLK is not generated if it is disabled when DIV > 0 and then enabled again Since the silicon revision is updated, user software will have to accommodate this change if this silicon revision is used DCDC Trim OTPMK Selection ROM: add DCDC trim function in ROM code SOC: blown the OTP_KEY_TO_DCP_DI SABLE fuse bit to protect to OTPMK key For A1 part, customer has to keep HAB close when encrypt XIP image by selecting OPTMK as key For A1 silicon, keep the below register field: SOC CCM:add bit field for mainclk clock gate CCM_CCGR0:CG4(sim_m or sim_main register access clock)need to be 2'b11 as default from reset NXP Semiconductors 4
5 Category CCM_CCGR4:CG0(sim_m7 register access clock)need to be 2'b11 as default from reset 3. Revision history Revision history Revision number Date Substantive changes 0 03/2018 Initial release 1 05/2018 Updated Table 2. Summary table for DCDC Trim, OTPMK Selection, and SOC. NXP Semiconductors 5
6 How to Reach Us: Home Page: nxp.com Web Support: nxp.com/support Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein. NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including typicals, must be validated for each customer application by customer s technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address: nxp.com/salestermsandconditions. NXP, the NXP logo, NXP SECURE CONNECTIONS FOR A SMARTER WORLD, Freescale, the Freescale logo, and Kinetis are trademarks of NXP B.V. All other product or service names are the property of their respective owners. Arm, Arm Powered, and Cortex are registered trademarks of Arm Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved NXP B.V. Document Number: AN12146 Rev. 1 05/2018
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