Wafer Level 3-D ICs Process Technology

Transcription

1 Wafer Level 3-D ICs Process Technology

2 Series on Integrated Circuits and Systems Series Editor: Anantha Chandrakasan Massachusetts Institute of Technology Cambridge, Massachusetts Wafer Level 3-D ICs Process Technology Chuan Seng Tan, Ronald J. Gutmann, and L. Rafael Reif (Eds.) ISBN Adaptive Techniques for Dynamic Processor Optimization: Theory and Practice Alice Wang and Samuel Naffziger (Eds.) ISBN mm-wave Silicon Technology: 60 GHz and Beyond Ali M. Niknejad and Hossein Hashemi (Eds.) ISBN Ultra Wideband: Circuits, Transceivers, and Systems Ranjit Gharpurey and Peter Kinget (Eds.) ISBN Creating Assertion-Based IP Harry D. Foster and Adam C. Krolnik ISBN Design for Manufacturability and Statistical Design: A Constructive Approach Michael Orshansky, Sani R. Nassif, and Duane Boning ISBN Low Power Methodology Manual: For System-on-Chip Design Michael Keating, David Flynn, Rob Aitken, Alan Gibbons, and Kaijian Shi ISBN Modern Circuit Placement: Best Practices and Results Gi-Joon Nam and Jason Cong ISBN CMOS Biotechnology Hakho Lee, Donhee Ham and Robert M. Westervelt ISBN SAT-Based Scalable Formal Verification Solutions Malay Ganai and Aarti Gupta ISBN , 2007 Ultra-Low Voltage Nano-Scale Memories Kiyoo Itoh, Masashi Horiguchi and Hitoshi Tanaka ISBN , 2007 Routing Congestion in VLSI Circuits: Estimation and Optimization Prashant Saxena, Rupesh S. Shelar, Sachin Sapatnekar ISBN , 2007 Continued after index

3 Chuan Seng Tan Ronald J. Gutmann L. Rafael Reif Editors Wafer Level 3-D ICs Process Technology Foreword by Scott List 123

4 Editors Chuan Seng Tan School of Electrical and Electronic Engineering Nanyang Technological University Singapore Ronald J. Gutmann Center for Integrated Electronics Rensselaer Polytechnic Institute Troy, NY USA L. Rafael Reif Department of Electrical Engineering Massachusetts Institute of Technology Cambridge, MA USA ISSN: ISBN: e-isbn: DOI: / Library of Congress Control Number: c 2008 Springer Science+Business Media, LLC All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. Printed on acid-free paper springer.com

5 Foreword Three-dimensional (3D) integration is clearly the simplest answer to most of the semiconductor industry s vexing problems: heterogeneous integration and reductions of power, form factor, delay, and even cost. Conceptually the power, latency, and form factor of a system with a fixed number of transistors all scale roughly linearly with the diameter of the smallest sphere enclosing frequently interacting devices. This clearly provides the fundamental motivation behind 3D technologies which vertically stack several strata of device and interconnect layers with high vertical interconnectivity. In addition, the ability to vertically stack strata with divergent and even incompatible process flows provides for low cost and low parasitic integration of diverse technologies such as sensors, energy scavengers, nonvolatile memory, dense memory, fast memory, processors, and RF layers. These capabilities coupled with today s trends of increasing levels of integrated functionality, lower power, smaller form factor, increasingly divergent process flows, and functional diversification would seem to make 3D technologies a natural choice for most of the semiconductor industry. Since the concept of vertical integration of different strata has been around for over 20 years, why aren t vertically stacked strata endemic to the semiconductor industry? The simple answer to this question is that in the past, the 3D advantages while interesting were not necessary due to the tremendous opportunities offered by geometric scaling. In addition, even when the global interconnect problem of high-performance single-core processors seemed insurmountable without innovations such as 3D, alternative architectural solutions such as multicores could effectively delay but not eliminate the need for 3D. Cost and risk avoidance are also major factors delaying the implementation of 3D. Geometric scaling has a fundamental 2x cost reduction per technology node while 3D from a simple wafer perspective has an additional cost of vertical wafer bonding and interconnection. It is only with recent trends toward divergent process flow integration that 3D offers the potential for substantial cost reduction. The relative immaturity of the novel 3D process flows has also delayed its adoption. So what is the future of 3D? It appears as if its time has finally come. The increasingly more difficult challenges to continued geometric scaling have made 3D the most attractive option to continue increasing the integrated functionality of chips. The trend for reduced form factor has already resulted in commercial v

6 vi Foreword implementation of through-silicon via technologies in stacked memories for cell phones. This innovation has primed the pump for related 3D technologies. The vertical integration of divergent flows with through-silicon vias will be implemented within a couple years on cell phones, and high-performance, low-power applications with higher via density are not much further out. Perhaps the greatest potential for 3D will come when more conventional applications drive the technology to sufficient maturity to enable vastly more aggressive 3D integration. Conceptually new biochips in 100- m cubes may be introduced into the body, scavenge energy, selectively attract cancer cells, sense the type of cell, turn off if the wrong cell is attracted, zap the correct cells with high current, store the event and periodically transmit a unique RF signal to an outside receiver of their identity and running cancer cell kills per specified category. Three-dimensional integration can be defined in as many different ways as there are researchers in the field. This book provides the most complete differentiation of the various 3D technologies in the literature. It also provides sufficient detail to fully understand their capabilities, limitations, and targeted applications, and closely couples the reader to a quiet revolution in the making. Intel/SRC Scott List

7 Preface Three-dimensional (3D) integration has emerged as an attractive contender as the semiconductor industry faces serious obstacles with interconnect scaling and as demand for on-chip functionality continues to increase. The advent of 3D integration is a direct result of active research in academia, research laboratories, and industry over the past several years. Today, 3D integration takes many forms depending on the application and it promises to be a viable future technology alternative. At the time of this writing, there are already commercial products featuring chip stacks vertically interconnected by through-silicon vias (TSVs). The idea of a book on 3D technology dates back to more than a year ago. There were then (and continues to be now) an increasing number of publications and conferences that focused on 3D integration. However, a reference book on this emerging field was lacking. While the initial idea was to author a book, we soon realized that such an endeavor would be extremely challenging given the many varieties of 3D integration technologies. We revisited the plan and decided to edit a book instead with contributions from experts in academia, research laboratories, and industry. After careful planning, we identified and invited chapter contribution from an impressive line-up of highly qualified researchers. It took a full 1 year for planning, writing, editing, and printing. The objective of this book is to present novel ideas in pre-packaging wafer-level 3D integration technologies. The book covers process technologies from the frontend to the backend of the line. All process technologies are carefully described and potential applications are listed. Technical challenges are also highlighted. This book is particularly beneficial to researchers or engineers who are already working or are beginning to work on 3D technology. This book would not have been possible without a team of highly qualified and dedicated people. We are particularly grateful to Carl Harris of Springer for initiating this undertaking and for providing his support. We thank Anantha Chandrakasan, the series editor, for his recommendation and view on the contents of this book. Katie Stanne worked alongside with us and provided us with the necessary editorial support. The three co-editors were funded for many years through the MARCO and DARPA funded Interconnect Focus Center (IFC) as well as the DARPA funded 3D IC Program; our 3D technology platform research, and this book, would not have been possible without this extended research support. vii

8 viii Preface C.S. Tan was also partially supported by SRC and an Applied Materials Graduate Fellowship previously. He is currently supported through a Lee Kuan Yew Postdoctoral Fellowship at the Nanyang Technological University. Last but not least, we are extremely thankful to authors who accepted our invitation and contributed chapters to this book. We hope that the readers will find this book useful in their pursuit of 3D technology. Please do not hesitate to contact us if you have any comments or suggestions. Singapore Troy, USA Cambridge, USA Chuan Seng Tan Ronald J. Gutmann L. Rafael Reif

9 Contents 1 Overview of Wafer-Level 3D ICs... 1 Chuan Seng Tan, Ronald J. Gutmann, and L. Rafael Reif 2 Monolithic 3D Integrated Circuits Christopher Petti, S. Brad Herner and Andrew Walker 3 Stacked CMOS Technologies Mansun Chan 4 Wafer-Bonding Technologies and Strategies for 3D ICs Shari Farrens 5 Through-Silicon Via Fabrication, Backgrind, and Handle Wafer Technologies Sharath Hosali, Greg Smith, Larry Smith, Susan Vitkavage, and Sitaram Arkalgud 6 Cu Wafer Bonding for 3D IC Applications Kuan-Neng Chen, Chuan Seng Tan, Andy Fan, and L. Rafael Reif 7 Cu/Sn Solid Liquid Interdiffusion Bonding A. Munding, H. Hübner, A. Kaiser, S. Penka, P. Benkart, and E. Kohn 8 An SOI-Based 3D Circuit Integration Technology James Burns, Brian Aull, Robert Berger, Nisha Checka, Chang-Lee Chen, Chenson Chen, Pascale Gouker, Craig Keast, Jeffrey Knecht, Antonio Soares, Vyshnavi Suntharalingam, Brian Tyrrell, Keith Warner, Bruce Wheeler, Peter Wyatt, and Donna Yost 9 3D Fabrication Options for High-Performance CMOS Technology Anna W. Topol, Steven J. Koester, Douglas C. La Tulipe, and Albert M. Young ix

10 x Contents 10 3D Integration Based upon Dielectric Adhesive Bonding Jian-Qiang Lu, Timothy S. Cale, and Ronald J. Gutmann 11 Direct Hybrid Bonding Bart Swinnen, Anne Jourdain, Piet De Moor, and Eric Beyne 12 3D Memory Robert S. Patti 13 Circuit Architectures for 3D Integration Nisha Checka 14 Thermal Challenges of 3D ICs Sheng-Chih Lin and Kaustav Banerjee 15 Status and Outlook Scott K. Pozder and Robert E. Jones Index...353

11 Contributors Sitaram Arkalgud SEMATECH, Austin, TX, USA, Brian Aull Kaustav Banerjee University of California, Santa Barbara, CA, USA, P. Benkart Institute of Electron Devices and Circuits, University of Ulm, Albert-Einstein-Alle 45, Ulm, Germany, Robert Berger Eric Beyne IMEC, Kapeldreef 75, B-3001 Leuven, Belgium, James Burns Timothy S. Cale Rensselaer Polytechnic Institute, Troy, NY, USA, Mansun Chan Hong Kong University of Science and Technology, Hong Kong, Nisha Checka Massachusetts Institute of Technology, Cambridge, MA, USA, Chang-Lee Chen xi

12 xii Contributors Chenson Chen Kuan-Neng Chen IBM T. J. Watson Research Center, Yorktown Heights, NY, USA, Piet De Moor IMEC, Kapeldreef 75, B-3001 Leuven, Belgium, Andy Fan Massachusetts Institute of Technology, Cambridge, MA, USA, Shari Farrens SUSS MicroTec, Waterbury Center, VT, USA, Pascale Gouker Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, MA, USA, Ronald J. Gutmann Rensselaer Polytechnic Institute, Troy, NY, USA, S. Brad Herner SanDisk Corporation, Milpitas, CA, USA, Sharath Hosali SEMATECH, Austin, TX, USA, H. Hübner Qimonda AG, Gustav-Heinemann-Ring 212, Munich, Germany, Robert E. Jones Freescale Semiconductor, Inc., Austin, TX, USA, Anne Jourdain IMEC, Kapeldreef 75, B-3001 Leuven, Belgium, A. Kaiser Institute of Electron Devices and Circuits, University of Ulm, Albert-Einstein-Alle 45, Ulm, Germany, Craig Keast Jeffrey Knecht

13 Contributors xiii Steven J. Koester IBM T. J. Watson Research Center, Yorktown Heights, NY, USA, E. Kohn Institute of Electron Devices and Circuits, University of Ulm, Albert-Einstein- Alle 45, Ulm, Germany, Douglas C. La Tulipe IBM T. J. Watson Research Center, Yorktown Heights, NY, USA, Sheng-Chih Lin University of California, Santa Barbara, CA, USA, Jian-Qiang Lu Rensselaer Polytechnic Institute, Troy, NY, USA, A. Munding Institute of Electron Devices and Circuits, University of Ulm, Albert-Einstein-Alle 45, Ulm, Germany, Robert S. Patti CTO, Tezzaron Semiconductor, Naperville, IL, USA, S. Penka Infineon Technologies AG, Otto-Hahn-Ring 6, Munich, Germany, Christopher Petti SanDisk Corporation, Milpitas, CA, USA, Scott K. Pozder Freescale Semiconductor, Inc., Austin, TX, USA, L. Rafael Reif Massachusetts Institute of Technology, Cambridge, MA, USA, Greg Smith SEMATECH, Austin, TX, USA, Larry Smith SEMATECH, Austin, TX, USA, Antonio Soares Vyshnavi Suntharalingam

14 xiv Contributors Bart Swinnen IMEC, Kapeldreef 75, B-3001 Leuven, Belgium, Chuan Seng Tan Nanyang Technological University, Singapore, Anna W. Topol IBM T. J. Watson Research Center, Yorktown Heights, NY, USA, Brian Tyrrell Susan Vitkavage SEMATECH, Austin, TX, USA, Andrew Walker Schiltron Corporation, Mountain View, CA, USA, Keith Warner Bruce Wheeler Peter Wyatt Donna Yost Albert M. Young IBM T. J. Watson Research Center, Yorktown Heights, NY, USA,