Integrated Circuits and Systems

Transcription

1 Integrated Circuits and Systems Series Editor Anantha Chandrakasan, Massachusetts Institute of Technology Cambridge, Massachusetts For other titles published in this series, go to

2 Yuan Xie Jason Cong Sachin Sapatnekar Editors Three-Dimensional Integrated Circuit Design EDA, Design and Microarchitectures 123

3 Editors Yuan Xie Department of Computer Science and Engineering Pennsylvania State University Jason Cong Department of Computer Science University of California, Los Angeles Sachin Sapatnekar Department of Electrical and Computer Engineering University of Minnesota ISBN e-isbn DOI / Springer New York Dordrecht Heidelberg London Library of Congress Control Number: Springer Science+Business Media, LLC 2010 All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. Printed on acid-free paper Springer is part of Springer Science+Business Media (

4 Foreword We live in a time of great change. In the electronics world, the last several decades have seen unprecedented growth and advancement, described by Moore s law. This observation stated that transistor density in integrated circuits doubles every years. This came with the simultaneous improvement of individual device performance as well as the reduction of device power such that the total power of the resulting ICs remained under control. No trend remains constant forever, and this is unfortunately the case with Moore s law. The trouble began a number of years ago when CMOS devices were no longer able to proceed along the classical scaling trends. Key device parameters such as gate oxide thickness were simply no longer able to scale. As a result, device offstate currents began to creep up at an alarming rate. These continuing problems with classical scaling have led to a leveling off of IC clock speeds to the range of several GHz. Of course, chips can be clocked higher but the thermal issues become unmanageable. This has led to the recent trend toward microprocessors with multiple cores, each running at a few GHz at the most. The goal is to continue improving performance via parallelism by adding more and more cores instead of increasing speed. The challenge here is to ensure that general purpose codes can be efficiently parallelized. There is another potential solution to the problem of how to improve CMOS technology performance: three-dimensional integrated circuits (3D ICs). By moving to a technology with multiple active tiers in the vertical direction, a number of significant benefits can be realized. Global wires become much shorter, interconnect bandwidth can be greatly increased, and latencies can be significantly decreased. Large amounts of low-latency cache memory can be utilized and intelligent physical design can help mitigate thermal and power delivery hotspots. Three-dimensional IC technology offers a realistic path for maintaining the progress defined by Moore s Law without requiring classical scaling. This is a critical opportunity for the future. The Defense Advanced Research Project Agency (DARPA) has recognized the significance of 3D IC technology a number of years ago and began carefully targeted investments in this area based on the potential for military relevance and applications. There are also many potential commercial benefits from such a technology. The Microsystems Technology Office at DARPA has launched a number of 3D IC-based Programs in recent years targeting areas such as intelligent imagers, v

5 vi Foreword heterogeneously integrated 3D stacks, and digital performance enhancement. The research results in a number of the chapters in this book were made possible by DARPA-sponsored programs in the field of 3D IC. Three-dimensional IC technology is currently at an early stage, with several processes just becoming available and more in the early development stage. Still, its potential is so great that a dedicated community has already begun to seriously study the EDA, design, and architecture issues associated with 3D IC, which are well summarized in this book. Chapter 1 provides a good introduction to this field by an expert from IBM well versed in both design and technology aspects. Chapter 2 provides an excellent overview of key 3D IC technology issues by process technology researchersfrom IBM and can be beneficial to any designer or architect. Chapters 3 6 cover important 3D IC electronic design automation (EDA) issues by researchers from the University of California, Los Angeles and the University of Minnesota. Key issues covered in these chapters include methods for managing the thermal, electrical, and layout challenges of a multi-tier electronic stack during the modeling and physical design processes. Chapters 7 9 deal with 3D design issues, including the 3D processor design by authors from the Georgia Institute of Technology, a 3D network-on-chip (NoC) architecture by authors from Pennsylvania State University, and a 3D architectural approach to energy efficient server designs by authors from the University of Michigan and Intel. The book concludes with a system level analysis of the potential cost advantages of 3D IC technology by researchers at Pennsylvania State University. As I mentioned in the beginning we live at a time of great change. Such change can be viewed as frightening, as long-held assumptions and paradigms, such as Moore s Law, lose relevance. Challenging times are also important opportunities to try new ideas. Three-dimensional IC technology is such a new idea and this book will play an important and pioneering role in ushering in this new technology to the research community and the IC industry. DARPA Microsystems Technology Office Arlington, Virginia March 2009 Michael Fritze, Ph.D.

6 Preface To the observer, it would appear that New York city has a special place in the hearts of integrated circuit (IC) designers. Manhattan geometries, which mimic the blocks and streets of the eponymous borough, are routinely used in physical design: under this paradigm, all shapes can be decomposed into rectangles, and each wire is either parallel and perpendicular to any other. The advent of 3D circuits extends the analogy to another prominent feature of Manhattan namely, its skyscrapers as ICs are being built upward, with stacks of active devices placed on top of each other. More precisely, unlike conventional 2D IC technologies that employ a single tier with one layer of active devices and several layers of interconnect above this layer, 3D ICs stack multiple tiers above each other. This enables the enhanced use of silicon real estate and the use of efficient communication structures (analogous to elevators in a skyscraper) within a stack. Going from the prevalent 2D paradigm to 3D is certainly not a small step: in more ways than one, this change adds a new dimension to IC design. Three-dimensional design requires novel process and manufacturing technologies to reliably, scalably, and economically stack multiple tiers of circuitry, design methods from the circuit level to the architectural level to exploit the promise of 3D, and computer-aided design (CAD) techniques that facilitate circuit analysis and optimization at all stages of design. In the past few years, as process technologies for 3D have neared maturity and 3D circuits have become a reality, this field has seen a flurry of research effort. The objective of this book is to capture the current state of the art and to provide the readers with a comprehensive introduction to the underlying manufacturing technology, design methods, and computer-aided design (CAD) techniques. This collection consists of contributions from some of the most prominent research groups in this area, providing detailed insights into the challenges and opportunities of designing 3D circuits. The history of 3D circuits goes back many years, and some of its roots can be traced to a major government-funded program in Japan from a couple of decades ago. It is only in the past few years that the idea of 3D has gained major traction, so that it is considered a realistic option today. Today, most major players in the semiconductor industry have dedicated significant resources and effort to this area. As a result, 3D technology is at a stage where it is poised to make a major leap. The context and motivation for this technology are provided in Chapter 1. vii

7 viii Preface The domain of 3D circuits is diverse, and various 3D technologies available today provide a wide range of tradeoffs between cost and performance. These include silicon-carrier-like technologies with multiple dies mounted on a substrate, wafer stacking with intertier spacings of the order of hundreds of microns, and thinned die/wafer stacks with intertier distances of the order of ten microns. The former two have the advantage of providing compact packaging and higher levels of integration but often involve significant performance overheads in communications from one tier to another. The last, with small intertier distances, not only provides increased levels of integration but also facilitates new architectures that can actually improve significantly upon an equivalent 2D implementation. Such advanced technologies are the primary focus of this book, and a cutting-edge example within this class is described in detail in Chapter 2. In building 3D structures, there are significant issues that must be addressed by CAD tools and design techniques. The change from 2D to 3D is fundamentally topological, and therefore it is important to build floorplanning, placement, and routing tools for 3D chips. Moreover, 3D chips see a higher amount of current per unit footprint than their 2D counterparts, resulting in severe thermal and power delivery bottlenecks. Any physical design system for 3D must incorporate thermal considerations and must pay careful attention to constructing power delivery networks. All of these issues are addressed in Chapters 3 6. At the system level, 3D architectures can be used to build new architectures. For sensor chips, sensors may be placed in the top tier, with analog amplifier circuits in the next layer, and digital signal processing circuitry in the layers below: such ideas have been demonstrated at the concept or implementation level for image sensors and antenna arrays. For processor design, 3D architectures allow memories to be stacked above processors, allowing for fast communication between the two and thereby removing one of the most significant performance bottlenecks in such systems. Several system design examples are discussed in Chapters 7 9. Finally, Chapter 10 presents a methodology for cost analysis of 3D circuits. It is our hope that the book will provide the readers with a comprehensive view of the current state of 3D IC design and insights into the future of this technology. Sachin Sapatnekar

8 Contents 1 Introduction... 1 Kerry Bernstein 2 3D Process Technology Considerations Albert M. Young and Steven J. Koester 3 Thermal and Power Delivery Challenges in 3D ICs Pulkit Jain, Pingqiang Zhou, Chris H. Kim, and Sachin S. Sapatnekar 4 Thermal-Aware 3D Floorplan Jason Cong and Yuchun Ma 5 Thermal-Aware 3D Placement Jason Cong and Guojie Luo 6 Thermal Via Insertion and Thermally Aware Routing in 3D ICs Sachin S. Sapatnekar 7 Three-Dimensional Microprocessor Design Gabriel H. Loh 8 Three-Dimensional Network-on-Chip Architecture Yuan Xie, Narayanan Vijaykrishnan, and Chita Das 9 PicoServer: Using 3D Stacking Technology to Build Energy Efficient Servers Taeho Kgil, David Roberts, and Trevor Mudge 10 System-Level 3D IC Cost Analysis and Design Exploration Xiangyu Dong and Yuan Xie Index ix

9 Contributors Kerry Bernstein Applied Research Associates, Inc., Burlington, VT, Jason Cong Department of Computer Science, University of California; California NanoSystems Institute, Los Angeles, CA 90095, USA, Chita Das Pennsylvania State University, University Park, PA 16801, USA, Xiangyu Dong Pennsylvania State University, University Park, PA 16801, USA Pulkit Jain Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455, USA, Taeho Kgil Intel, Hillsboro, OR 97124, USA, Chris H. Kim Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455, USA, Steven J. Koester IBM Thomas J. Watson Research Center, Yorktown Heights, NY 10598, USA, Gabriel H. Loh College of Computing, Georgia Institute of Technology, Atlanta, GA, USA, Guojie Luo Department of Computer Science, University of California, Los Angeles, CA 90095, USA, Yuchun Ma Department of Computer Science and Technology, Tsinghua University, Beijing, P.R.China , Trevor Mudge University of Michigan, Ann Arbor, MI 48109, USA, David Roberts University of Michigan, Ann Arbor, MI 48109, USA, xi

10 xii Contributors Sachin S. Sapatnekar Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455, USA, Narayanan Vijaykrishnan Pennsylvania State University, University Park, PA 16801, USA, Yuan Xie Pennsylvania State University, University Park, PA 16801, USA, Albert M. Young IBM Thomas J. Watson Research Center, Yorktown Heights, NY 10598, USA, Pingqiang Zhou Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455, USA,