SMPS MOSFET. V DSS Rds(on) max I D

Transcription

1 pplications l Switch Mode Power Supply ( SMPS ) l Uninterruptable Power Supply l High speed power switching SMPS MOSFET PD 9809B IRFBN50 HEXFET Power MOSFET V DSS Rds(on) max I D 500V 0.52Ω Benefits l Low Gate Charge Qg results in Simple Drive Requirement l Improved Gate, valanche and dynamic dv/dt Ruggedness l Fully Characterized Capacitance and valanche Voltage and Current TO220B G D S bsolute Maximum Ratings Parameter Max. Units I T C = 25 C Continuous Drain Current, V V I T C = 0 C Continuous Drain Current, V V 7.0 I DM Pulsed Drain Current 44 P C = 25 C Power Dissipation 70 W Linear Derating Factor.3 W/ C V GS GatetoSource Voltage ± 30 V dv/dt Peak Diode Recovery dv/dt ƒ 6.9 V/ns T J Operating Junction and 55 to 50 T STG Storage Temperature Range C Soldering Temperature, for seconds 300 (.6mm from case ) Mounting torqe, 632 or M3 screw lbf in (.N m) pplicable Off Line SMPS Topologies: l Two Transistor Forward l Half & Full Bridge l Power Factor Correction Boost Notes through are on page 8 3/30/99

2 IRFBN5O T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS DraintoSource Breakdown Voltage 500 V V GS = 0V, I D = 250µ R DS(on) Static DraintoSource OnResistance 0.52 Ω V GS = V, I D = 6.6 V GS(th) Gate Threshold Voltage V V DS = V GS, I D = 250µ I DSS DraintoSource Leakage Current 25 V µ DS = 500V, V GS = 0V 250 V DS = 400V, V GS = 0V, T J = 50 C I GSS GatetoSource Forward Leakage 0 V GS = 30V n GatetoSource Reverse Leakage 0 V GS = 30V T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions g fs Forward Transconductance 6. S V DS = 50V, I D = 6.6 Q g Total Gate Charge 52 I D = Q gs GatetoSource Charge 3 nc V DS = 400V Q gd GatetoDrain ("Miller") Charge 8 V GS = V, See Fig. 6 and 3 t d(on) TurnOn Delay Time 4 V DD = 250V t r Rise Time 35 ns I D = t d(off) TurnOff Delay Time 32 R G = 9.Ω t f Fall Time 28 R D = 22Ω,See Fig. C iss Input Capacitance 423 V GS = 0V C oss Output Capacitance 208 V DS = 25V C rss Reverse Transfer Capacitance 8. pf ƒ =.0MHz, See Fig. 5 C oss Output Capacitance 2000 V GS = 0V, V DS =.0V, ƒ =.0MHz C oss Output Capacitance 55 V GS = 0V, V DS = 400V, ƒ =.0MHz C oss eff. Effective Output Capacitance 97 V GS = 0V, V DS = 0V to 400V valanche Characteristics Parameter Typ. Max. Units E S Single Pulse valanche Energy 275 mj I R valanche Current E R Repetitive valanche Energy 7 mj Thermal Resistance Parameter Typ. Max. Units R θjc JunctiontoCase 0.75 R θcs CasetoSink, Flat, Greased Surface 0.50 C/W R θj Junctiontombient 62 Diode Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol (Body Diode) showing the G I SM Pulsed Source Current integral reverse 44 (Body Diode) pn junction diode. S V SD Diode Forward Voltage.5 V T J = 25 C, I S =, V GS = 0V t rr Reverse Recovery Time ns T J = 25 C, I F = Q rr Reverse RecoveryCharge µc di/dt = 0/µs t on Forward TurnOn Time Intrinsic turnon time is negligible (turnon is dominated by L S L D ) 2

3 IRFBN50 I D, DraintoSource Current () 0 VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V I D, DraintoSource Current () 0 VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V 20µs PULSE WIDTH T J = 25 C V DS, DraintoSource Voltage (V) 20µs PULSE WIDTH 4.5V T J = 50 C 0 V DS, DraintoSource Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics I D, DraintoSource Current () 0 T J = 50 C T J = 25 C V DS= 50V 20µs PULSE WIDTH V GS, GatetoSource Voltage (V) R DS(on), DraintoSource On Resistance (Normalized) 3.0 I D = V GS = V T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized OnResistance Vs. Temperature 3

4 IRFBN5O C, Capacitance (pf) C iss C oss C rss V GS = 0V, f = MHz C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd V DS, DraintoSource Voltage (V) V GS, GatetoSource Voltage (V) I = D 6.6 V DS = 400V V DS = 250V V DS = 0V FOR TEST CIRCUIT SEE FIGURE Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. DraintoSource Voltage Fig 6. Typical Gate Charge Vs. GatetoSource Voltage 0 00 OPERTION IN THIS RE LIMITED BY R DS(on) I SD, Reverse Drain Current () T J = 50 C T J = 25 C V GS = 0 V V SD,SourcetoDrain Voltage (V) I D, Drain Current () 0 us 0us ms ms TC = 25 C TJ = 50 C Single Pulse V DS, DraintoSource Voltage (V) Fig 7. Typical SourceDrain Diode Forward Voltage Fig 8. Maximum Safe Operating rea 4

5 IRFBN50 2 V DS R D I D, Drain Current () R G V GS V Pulse Width µs Duty Factor 0. % D.U.T. Fig a. Switching Time Test Circuit V DD 2 V DS 90% T C, Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature % V GS t d(on) t r t d(off) t f Fig b. Switching Time Waveforms Thermal Response (Z thjc ) 0. D = PDM 0.05 t 0.02 SINGLE PULSE t2 0.0 (THERML RESPONSE) Notes:. Duty factor D = t / t 2 2. Peak T J = P DM x Z thjc TC t, Rectangular Pulse Duration (sec) Fig. Maximum Effective Transient Thermal Impedance, JunctiontoCase 5

6 IRFBN5O Fig 2a. Unclamped Inductive Test Circuit I S R G V DS 20V tp tp L D.U.T I S 0.0Ω V (BR)DSS Fig 2b. Unclamped Inductive Waveforms Q G 5V DRIVER V DD E S, Single Pulse valanche Energy (mj) TOP BOTTOM I D Starting T, Junction Temperature ( J C) Fig 2c. Maximum valanche Energy Vs. Drain Current V Q GS Q GD 660 V G 2V V GS Current Regulator Same Type as D.U.T..2µF 50KΩ 3m.3µF Charge Fig 3a. Basic Gate Charge Waveform D.U.T. V DS V DSav, valanche Voltage (V) I av, valanche Current () I G I D Current Sampling Resistors Fig 2d. Typical DraintoSource Voltage Fig 3b. Gate Charge Test Circuit Vs. valanche Current 6

7 IRFBN50 Peak Diode Recovery dv/dt Test Circuit D.U.T ƒ Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. Device Under Test V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Repplied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 4. For NChannel HEXFETS 7

8 IRFBN5O Package Outline TO220B Outline Dimensions are shown in millimeters (inches) 2.87 (.3) 2.62 (.3).54 (.45).29 (.405) 3.78 (.49) 3.54 (.39) 4.69 (.85) 4.20 (.65) B.32 (.052).22 (.048) 5.24 (.600) 4.84 (.584) (.255) 6. (.240) (.045) MIN LED SSIGNMENTS G TE 2 D R IN 3 S OU RC E 4 D R IN 4.09 (.555) 3.47 (.530) 4.06 (.60) 3.55 (.40).40 (.055) 3X.5 (.045) 2.54 (.0) 2X Part Marking Information TO220B EXMPLE : 3X 0.93 (.037) 0.69 (.027) 0.36 (.04) M B M 0.55 (.022) 3X 0.46 (.08) 2.92 (.5) 2.64 (.4) NOTES: D IMEN SION IN G & TOLE R N CING P E R NS I Y 4.5M, OU TLINE CO NF OR MS T O JEDE C OUT LINE T O220B. 2 C ON TR OLLING DIME NS IO N : INC H 4 H E TS IN K & LE D ME S UR EM EN TS D O N OT INCLUDE BURRS. THIS IS N IRF W ITH SSEMBLY LOT CODE 9BM INTERNTIONL RECTIFIER LOGO SSEMBLY LOT CODE IRF B M PRT NUMBER DTE CODE (YYWW ) YY = YER W W = W EEK Notes: Repetitive rating; pulse width limited by max. junction temperature. ( See fig. ) Starting T J = 25 C, L = 4.5mH R G = 25Ω, I S =. (See Figure 2) ƒ I SD, di/dt 40/µs, V DD V (BR)DSS, T J 50 C Pulse width 300µs; duty cycle 2%. C oss eff. is a fixed capacitance that gives the same charging time as C oss while V DS is rising from 0 to 80% V DSS WORLD HEDQURTERS: 233 Kansas St., El Segundo, California 90245, Tel: (3) IR GRET BRITIN: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: IR CND: 5 Lincoln Court, Brampton, Ontario L6T3Z2, Tel: (905) IR GERMNY: Saalburgstrasse 57, 6350 Bad Homburg Tel: IR ITLY: Via Liguria 49, 07 Borgaro, Torino Tel: IR FR EST: K&H Bldg., 2F, 304 NishiIkebukuro 3Chome, ToshimaKu, Tokyo Japan 7 Tel: IR SOUTHEST SI: Kim Seng Promenade, Great World City West Tower, 3, Singapore Tel: IR TIWN:6 Fl. Suite D. 207, Sec. 2, Tun Haw South Road, Taipei, 673, Taiwan Tel: Data and specifications subject to change without notice 3/99 8