Storage Temperature Range Soldering Temperature, for 10 seconds 300 (1.6mm from case )

Transcription

1 l Logic-Level Gate Drive l Ultra Low On-Resistance l Surface Mount (IRLR33) l Straight Lead (IRLU33) l dvanced Process Technology l Fast Switching l Fully valanche Rated Description Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve the lowest possible on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient device for use in a wide variety of applications. The D-PK is designed for surface mounting using vapor phase, infrared, or wave soldering techniques. The straight lead version (IRFU series) is for throughhole mounting applications. Power dissipation levels up to 1.5 watts are possible in typical surface mount applications. G IRLR/U33 HEXFET Power MOSFET D S D-PK TO-252 V DSS = 30V R DS(on) = 0.019Ω I-PK TO-251 PD E I D = 55 bsolute Maximum Ratings Parameter Max. Units I T C = 25 C Continuous Drain Current, V V 55 I T C = 0 C Continuous Drain Current, V V 39 I DM Pulsed Drain Current 220 P C = 25 C Power Dissipation 7 W Linear Derating Factor 0.71 W/ C V GS Gate-to-Source Voltage ± 16 V E S Single Pulse valanche Energy 240 mj I R valanche Current 34 E R Repetitive valanche Energy 11 mj dv/dt Peak Diode Recovery dv/dt ƒ 5.0 V/ns T J Operating Junction and -55 to 175 T STG Storage Temperature Range Soldering Temperature, for seconds 300 (1.6mm from case ) C Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case 1.4 R θj Junction-to-mbient (PCB mount) ** 50 C/W R θj Junction-to-mbient /11/98

2 Electrical T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 30 V V GS = 0V, I D = 250µ V (BR)DSS / T J Breakdown Voltage Temp. Coefficient V/ C Reference to 25 C, I D = 1m R DS(on) Static Drain-to-Source On-Resistance V GS = V, I D = 33 Ω V GS = 4.5V, I D = 25 V GS(th) Gate Threshold Voltage 1.0 V V DS = V GS, I D = 250µ g fs Forward Transconductance 23 S V DS = 25V, I D = 34 I DSS Drain-to-Source Leakage Current 25 V DS = 30V, V GS = 0V µ 250 V DS = 18V, V GS = 0V, T J = 150 C I GSS Gate-to-Source Forward Leakage 0 V GS = 16V n Gate-to-Source Reverse Leakage -0 V GS = -16V Q g Total Gate Charge 50 I D = 34 Q gs Gate-to-Source Charge 14 nc V DS = 24V Q gd Gate-to-Drain ("Miller") Charge 28 V GS = 4.5V, See Fig. 6 and 13 t d(on) Turn-On Delay Time 9.0 V DD = 15V t r Rise Time 2 I ns D = 34 t d(off) Turn-Off Delay Time 20 R G = 3.4Ω, V GS = 4.5V t f Fall Time 54 R D = 0.43Ω, See Fig. L D Internal Drain Inductance 4.5 nh Between lead, 6mm (0.25in.) L S Internal Source Inductance 7.5 G from package and center of die contact C iss Input Capacitance 1600 V GS = 0V C oss Output Capacitance 640 pf V DS = 25V C rss Reverse Transfer Capacitance 320 ƒ = 1.0MHz, See Fig. 5 Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions I D S Continuous Source Current MOSFET symbol 55 (Body Diode) showing the I SM Pulsed Source Current integral reverse G 220 (Body Diode) p-n junction diode. S V SD Diode Forward Voltage 1.3 V T J = 25 C, I S = 28, V GS = 0V t rr Reverse Recovery Time ns T J = 25 C, I F = 34 Q rr Reverse RecoveryCharge 2 3 nc di/dt = 0/µs t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S L D ) D S Notes: Repetitive rating; pulse width limited by max. junction temperature. ( See fig. 11 ) V DD = 15V, starting T J = 25 C, L = 300µH R G = 25Ω, I S = 34. (See Figure 12) ƒ I SD 34, di/dt 140/µs, V DD V (BR)DSS, T J 175 C Pulse width 300µs; duty cycle 2% Calculated continuous current based on maximum allowable junction temperature; Package limitation current = 20 This is applied for I-PK, L S of D-PK is measured between lead and center of die contact Uses IRL33 data and test conditions ** When mounted on 1" square PCB (FR-4 or G- Material ). For recommended footprint and soldering techniques refer to application note #N

3 I D, Drain-to-Source Current () 00 0 VGS TOP 15V 12V V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V 2.5V 20µs PULSE W IDTH 1 T J = 25 C V DS, Drain-to-Source Voltage (V) I D, Drain-to-Source Current () 00 0 VGS TOP 15V 12V V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V 2.5V 20µs PULSE W IDTH 1 T J = 175 C V DS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics I D, Drain-to-Source Current () 00 0 T = 25 C J V DS = 15V 20µs PULSE W IDTH V GS T = 175 C J, Gate-to-Source Voltage (V) Fig 3. Typical Transfer Characteristics R DS(on), Drain-to-Source On Resistance (Normalized) V GS = V Fig 4. Normalized On-Resistance Vs. Temperature I D = 56 T J, Junction Temperature ( C)

4 C, Capacitance (pf) C iss C oss C rss V GS = 0V, f = 1MHz C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd V DS, Drain-to-Source Voltage (V) V GS, Gate-to-Source Voltage (V) I D = 34 V DS = 24V V DS = 15V FOR TEST CIRCUIT SEE FIGURE Q, Total Gate Charge (nc) G Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage I SD, Reverse Drain Current () 00 0 T = 175 C J T = 25 C J V GS = 0V V SD, Source-to-Drain Voltage (V) I D, Drain Current () 00 OPERTION IN THIS RE LIMITED BY R DS(on) µs 0 0µs 1ms ms T C = 25 C T J = 175 C Single Pulse V DS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating rea 4

5 60 LIMITED BY PCKGE V DS R D I D, Drain Current () R G V GS 5.0V Pulse Width 1 µs Duty Factor 0.1 % D.U.T. Fig a. Switching Time Test Circuit - V DD T C, Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature V DS 90% % V GS t d(on) t r t d(off) t f Fig b. Switching Time Waveforms Thermal Response (Z thjc ) D = SINGLE PULSE (THERML RESPONSE) Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thjc TC t 1, Rectangular Pulse Duration (sec) PDM t1 t2 Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case 5

6 R G V DS V tp I S L D.U.T 0.01Ω Fig 12a. Unclamped Inductive Test Circuit tp 15V DRIVER - V (BR)DSS V DD E S, Single Pulse valanche Energy (mj) TOP BOTTOM ID V DD = 15V Starting T J, Junction Temperature ( C) Fig 12c. Maximum valanche Energy Vs. Drain Current I S Fig 12b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50KΩ Q G 12V.2µF.3µF 5.0 V Q GS Q GD D.U.T. V - DS V GS V G 3m Charge I G I D Current Sampling Resistors Fig 13a. Basic Gate Charge Waveform Fig 13b. Gate Charge Test Circuit 6

7 Peak Diode Recovery dv/dt Test Circuit D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - - R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test - V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-pplied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFETS 7

8 Package Outline TO-252 Outline Dimensions are shown in millimeters (inches) 5.46 (.215) 5.21 (.205) 6.73 (.265) 6.35 (.250) (.050) 0.88 (.035) 2.38 (.094) 2.19 (.086) 1.14 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.018) (.040) 1.64 (.025) 1.52 (.060) 1.15 (.045) 2X 1.14 (.045) 0.76 (.030) X 6.22 (.245) 5.97 (.235) - B (.035) 0.64 (.025) 0.25 (.0) M M B.42 (.4) 9.40 (.370) 6.45 (.245) 5.68 (.224) 0.51 (.020) MIN (.023) 0.46 (.018) LED SSIGNMENTS 1 - GTE 2 - DRIN 3 - SOURCE 4 - DRIN 2.28 (.090) 4.57 (.180) NOTES: 1 DIMENSIONING & TOLERNCING PER NSI Y14.5M, CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO DIMENSIONS SHOWN RE BEFORE SOLDER DIP, SOLDER DIP MX (.006). Part Marking Information TO-252 (D-PRK) EXMPLE : THIS IS N IRFR120 W ITH SSEMBLY LOT CODE 9U1P INTERNTIONL RECTIFIER LOGO IRFR 120 FIRST PORTION OF PRT NUMBER 9U 1P SSEMBLY SECOND PORTION LOT CODE OF PRT NUMBER 8

9 Package Outline TO-251 Outline Dimensions are shown in millimeters (inches) 5.46 (.215) 5.21 (.205) 1.52 (.060) 1.15 (.045) 6.73 (.265) 6.35 (.250) (.245) 5.97 (.235) 1.27 (.050) 0.88 (.035) 2.38 (.094) 2.19 (.086) 0.58 (.023) 0.46 (.018) 6.45 (.245) 5.68 (.224) LED SSIGNMENTS 1 - GTE 2 - DRIN 3 - SOURCE 4 - DRIN B (.090) 1.91 (.075) 9.65 (.380) 8.89 (.350) NOTES: 1 DIMENSIONING & TOLERNCING PER NSI Y14.5M, CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO DIMENSIONS SHOW N RE BEFORE SOLDER DIP, SOLDER DIP MX (.006). 3X 1.14 (.045) 0.76 (.030) 2.28 (.090) 2X 3X 0.89 (.035) 0.64 (.025) 0.25 (.0) M M B 1.14 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.018) Part Marking Information TO-251 (I-PRK) EXMPLE : THIS IS N IRFU120 W ITH SSEMBLY LOT CODE 9U1P INTERNTIONL RECTIFIER LOGO SSEMBLY LOT CODE IRFU 120 9U 1P FIRST PORTION OF PRT NUMBER SECOND PORTION OF PRT NUMBER 9

10 Tape & Reel Information TO-252 TR TRR TRL 16.3 (.641 ) 15.7 (.619 ) 16.3 (.641 ) 15.7 (.619 ) 12.1 (.476 ) 11.9 (.469 ) FEED DIRECTION 8.1 (.318 ) 7.9 (.312 ) FEED DIRECTION NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. LL DIMENSIONS RE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EI-481 & EI INCH NOTES : 1. OUTLINE CONFORMS TO EI mm WORLD HEDQURTERS: 233 Kansas St., El Segundo, California 90245, Tel: (3) IR GRET BRITIN: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: IR CND: 15 Lincoln Court, Brampton, Ontario L6T3Z2, Tel: (905) IR GERMNY: Saalburgstrasse 157, Bad Homburg Tel: IR ITLY: Via Liguria 49, 071 Borgaro, Torino Tel: IR FR EST: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 171 Tel: IR SOUTHEST SI: 1 Kim Seng Promenade, Great World City West Tower, 13-11, Singapore Tel: IR TIWN:16 Fl. Suite D. 207, Sec. 2, Tun Haw South Road, Taipei, 673, Taiwan Tel: Data and specifications subject to change without notice. 11/98

11 Note: For the most current drawings please refer to the IR website at: