EE140 Homework Solutions Problem Set 6 Fall for a single pole roll-off Dominant pole at output:
|
|
- Meghan Atkins
- 5 years ago
- Views:
Transcription
1 EE40 Homework Solutions Problem Set 6 Fall 2009 ) Single-stage op-amp comparison PMOS-input folded cascode Key results are shown in red. a. for a single pole roll-off Dominant pole at output: Plugging in numbers, (See the solutions for homework 3 if you don t know how to get C db or C gd.) M 2RC and M 3RC both carry 40 ua, so assuming V DS = V dsat for maximum swing, 2 So W n = 9.8 um. To give some margin on V ds > V dsat and for a reasonable value for width, W n = 9.75 um. W p = 2W n = 9.5 um. Neglecting channel length modulation, W n = 0um. Therefore,
2 b. c. Current flowing through each transistor Mtail 80 ua ML/R 40 ua M2L/R 80 ua M2CL/R 40 ua M3CL/R 40 ua M3L/R 40 ua For the total current, what we re interested is the total current flowing out of the supply (or into ground same thing). Flowing out of the supply is the current through Mtail, M3L, and M3R: = 60 ua. Flowing into ground is the current through M2L and M2R: = 60 ua. Therefore, the total current consumption of the folded cascode topology is 60 ua. d. The smallest width we re allowed is um, and in general smaller is better in a bias network, because otherwise we re just wasting power. PMOSes are twice as large as NMOSes for the same V DSAT. The first (left) branch is minimum sized, but the current is multiplied by 5 when copied to the next branch because the PMOS in the second branch is sized /5 the size of the other devices to produce an extra V DSAT across itself, with some margin for error due to body effect or mismatch. The third branch is again minimum-sized so as to not waste current. Its purpose is just to flip the mirror for the fourth branch. The size-limiting component in the fourth branch is the NMOS, which is sized down to drop an extra V DSAT just like the PMOS in the second branch. This bias network consumes 4 ua in the first branch, 0 ua in the second branch, 4 ua in the third branch, and 20 ua in the fourth branch for a total of 38 ua.
3 4 ua um VBP 2 um 0 um VBtail 2 um 0 um um 2.5 um um um VBN2 um 2.5 um um VBN
4 Telescopic Cascode Key results are shown in red. Differences in part a from folded cascode are highlighted. a. for a single pole roll-off Dominant pole at output: Plugging in numbers, Double folded cascode R o Double folded cascode A v M RC and M 2RC both carry 40 ua, so assuming V DS = V dsat for maximum swing, 2 So W n = 9.8 um. To give some margin on V ds > V dsat and for a reasonable value for width, W n = 9.75 um. W p = 2W n = 9.5 um. Neglecting channel length modulation, W n = 0um. Therefore, Half folded cascode ω p. Same ω u as folded cascode.
5 b. Vi Vt +Vdsat = Vi 0.3 V c. The two outer branches are each flowing 40 ua, and the middle branch flows ~40 ua if MCbias is sized as 2 um, /5 of the other devices (excluding the tail). Ideally it would flow 32 ua, but this estimation neglects body effect and leaves no room for mismatch. If the middle branch is resized to flow the minimum possible current while maintaining 2V dsat across it, MCbias can be as small as um and flow 6-20 ua. The total current is approximately 00 ua with this sizing. The extra 20 ua is the cost of improving the input common-mode range. d. The telescopic cascode bias network is shown below. The devices are sized identically to those in the folded cascode bias network, except that in this case there is no fourth branch. The total current in this bias network is 8 ua.
6
7 Current Mirror Cascode Op-Amp Key results are shown in red. Differences in part a from folded cascode are highlighted. a. for a single pole roll-off Dominant pole at output: Plugging in numbers, M 2RC and M 3RC both carry 40 ua, so assuming V DS = V dsat for maximum swing, 2 So W n = 9.8 um. To give some margin on V ds > V dsat and for a reasonable value for width, W n = 9.75 um. W p = 2W n = 9.5 um. Neglecting channel length modulation, W n = 0um. Therefore, Half folded cascode ω p. Same ω u as folded cascode. NOTE: This is exactly the same as for the telescopic cascode.
8 b. Output Vdd Current Mirror Cascode Op-Amp Vdd - 2Vdsat = = 2.6 V 2Vdsat = 0.4 V Input Vt + 2Vdsat = 0.9 V Vdd Vdd - Vdsat = 2.8 V (Vt+Vdsat from M2M, -Vt from M) c. This circuit has 40 ua flowing in the left branch, 80 ua flowing in the middle branch (through Mtail), and 40 ua flowing in the right branch for a total of 60 ua. d. The bias network for this circuit is drawn below. It s identical to that used to bias the folded cascode in every way. It consumes 38 ua. e. Having now examined each of the topologies, there is no clear winner overall. Each has its advantages in one area and disadvantages in another. If the target is gain then the folded cascode is probably not the way to go, but if the goal is a large swing then it probably is. The telescopic cascode is the lowest power and lowest complexity solution if those are the key metrics. The current mirror cascode op-amp has similar power consumption and a similar level of complexity to the folded cascode, but it trades off a small amount of swing for the higher gain that the folded cascode lacks. The folded cascode has the best bandwidth, but the gain-bandwidth product of the three topologies is identical, so in many cases this won t matter much.
9
10 2) OPA344 a. The input common-mode range goes from 0. V below the bottom rail to within.5 V of the top rail, so it s a fair guess that the input stage is a PMOS-input folded cascode (from the table of electrical characteristics). b. The low-frequency gain is 30 db, or 3.6e6 V/V (from the table of electrical characteristics). c. The unity gain frequency is 2 MHz, and the phase margin is about 73 degrees (from the first plot on page 5). d. The slew rate is.6 V/us (from the table of electrical characteristics),.6 MV per second. The maximum slope of a sin wave occurs at the zero crossing, so we evaluate sin 2 2 cos 2 at t = 0, and find that the maximum slope is 2 volts per second. For A = 0. V, the maximum allowable frequency is ) OPA340 a. The unity gain frequency is 5.5 MHz, and the phase margin is around 73 degrees. b. The typical offset voltage is 50 uv, and the worst case is 500 uv. c. The things to notice here are that the G m has roughly doubled compared to the standard folded cascode, the input common mode range is now rail to rail, and the total current (excluding biasing) is 3*I ref. If the current sources were non-ideal transistors as in the first problem, we would lose some output resistance to those transistors (a factor of three, using the numbers from problem ).
EE 140 HW7 SOLUTION 1. OPA334. a. From the data sheet, we see that. Vss 0.1V Vcm Vdd 1.5V
EE 140 HW7 SOLUTION 1. OPA334 a. From the data sheet, we see that Vss 0.1V Vcm Vdd 1.5V The input common mode voltage must remain at least 1.5V below vdd. The input common mode voltage can be below Vss.
More informationLow Quiescent Power CMOS Op-Amp in 0.5µm Technology
Kevin Fronczak - Low Power CMOS Op-Amp - Rochester Institute of Technology EE610 1 Low Quiescent Power CMOS Op-Amp in 0.5µm Technology Kevin C. Fronczak Abstract This paper analyzes a low quiescent power
More informationCMOS Operational-Amplifier
CMOS Operational-Amplifier 1 What will we learn in this course How to design a good OP Amp. Basic building blocks Biasing and Loading Swings and Bandwidth CH2(8) Operational Amplifier as A Black Box Copyright
More informationOperational Amplifiers
CHAPTER 9 Operational Amplifiers Analog IC Analysis and Design 9- Chih-Cheng Hsieh Outline. General Consideration. One-Stage Op Amps / Two-Stage Op Amps 3. Gain Boosting 4. Common-Mode Feedback 5. Input
More informationCMOS Operational-Amplifier
CMOS Operational-Amplifier 1 What will we learn in this course How to design a good OP Amp. Basic building blocks Biasing and Loading Swings and Bandwidth CH2(8) Operational Amplifier as A Black Box Copyright
More informationBasic Circuits. Current Mirror, Gain stage, Source Follower, Cascode, Differential Pair,
Basic Circuits Current Mirror, Gain stage, Source Follower, Cascode, Differential Pair, CCS - Basic Circuits P. Fischer, ZITI, Uni Heidelberg, Seite 1 Reminder: Effect of Transistor Sizes Very crude classification:
More informationECEN 474/704 Lab 6: Differential Pairs
ECEN 474/704 Lab 6: Differential Pairs Objective Design, simulate and layout various differential pairs used in different types of differential amplifiers such as operational transconductance amplifiers
More informationDesign and Layout of Two Stage High Bandwidth Operational Amplifier
Design and Layout of Two Stage High Bandwidth Operational Amplifier Yasir Mahmood Qureshi Abstract This paper presents the design and layout of a two stage, high speed operational amplifiers using standard
More informationd. Can you find intrinsic gain more easily by examining the equation for current? Explain.
EECS140 Final Spring 2017 Name SID 1. [8] In a vacuum tube, the plate (or anode) current is a function of the plate voltage (output) and the grid voltage (input). I P = k(v P + µv G ) 3/2 where µ is a
More informationA PSEUDO-CLASS-AB TELESCOPIC-CASCODE OPERATIONAL AMPLIFIER
A PSEUDO-CLASS-AB TELESCOPIC-CASCODE OPERATIONAL AMPLIFIER M. Taherzadeh-Sani, R. Lotfi, and O. Shoaei ABSTRACT A novel class-ab architecture for single-stage operational amplifiers is presented. The structure
More informationDesign of High-Speed Op-Amps for Signal Processing
Design of High-Speed Op-Amps for Signal Processing R. Jacob (Jake) Baker, PhD, PE Professor and Chair Boise State University 1910 University Dr. Boise, ID 83725-2075 jbaker@ieee.org Abstract - As CMOS
More informationDesign of Miller Compensated Two-Stage Operational Amplifier for Data Converter Applications
Design of Miller Compensated Two-Stage Operational Amplifier for Data Converter Applications Prema Kumar. G Shravan Kudikala Casest, School Of Physics Casest, School Of Physics University Of Hyderabad
More informationRadivoje Đurić, 2015, Analogna Integrisana Kola 1
Low power OTA 1 Two-Stage, Miller Op Amp Operating in Weak Inversion Low frequency response: gm1 gm6 Av 0 g g g g A v 0 ds2 ds4 ds6 ds7 I D m, ds D nvt g g I n GB and SR: GB 1 1 n 1 2 4 6 6 7 g 2 2 m1
More informationDesign and Simulation of Low Voltage Operational Amplifier
Design and Simulation of Low Voltage Operational Amplifier Zach Nelson Department of Electrical Engineering, University of Nevada, Las Vegas 4505 S Maryland Pkwy, Las Vegas, NV 89154 United States of America
More informationA CMOS Low-Voltage, High-Gain Op-Amp
A CMOS Low-Voltage, High-Gain Op-Amp G N Lu and G Sou LEAM, Université Pierre et Marie Curie Case 203, 4 place Jussieu, 75252 Paris Cedex 05, France Telephone: (33 1) 44 27 75 11 Fax: (33 1) 44 27 48 37
More informationMicroelectronic Circuits II. Ch 10 : Operational-Amplifier Circuits
Microelectronic Circuits II Ch 0 : Operational-Amplifier Circuits 0. The Two-stage CMOS Op Amp 0.2 The Folded-Cascode CMOS Op Amp CNU EE 0.- Operational-Amplifier Introduction - Analog ICs : operational
More informationOp-Amp Design Project EE 5333 Analog Integrated Circuits Prof. Ramesh Harjani Department of ECE University of Minnesota, Twin Cities Report prepared
Op-Amp Design Project EE 5333 Analog Integrated Circuits Prof. Ramesh Harjani Department of ECE University of Minnesota, Twin Cities Report prepared by: Nirav Desai (4280229) 1 Contents: 1. Design Specifications
More informationChapter 5. Operational Amplifiers and Source Followers. 5.1 Operational Amplifier
Chapter 5 Operational Amplifiers and Source Followers 5.1 Operational Amplifier In single ended operation the output is measured with respect to a fixed potential, usually ground, whereas in double-ended
More informationA Compact Folded-cascode Operational Amplifier with Class-AB Output Stage
A Compact Folded-cascode Operational Amplifier with Class-AB Output Stage EEE 523 Advanced Analog Integrated Circuits Project Report Fuding Ge You are an engineer who is assigned the project to design
More informationDifferential Amplifier Design
Fall - 2009 EE114 - Design Project Differential Amplifier Design Submitted by Piyush Keshri (0559 4497) Jeffrey Tu (0554 4565) On November 20th, 2009 EE114 - Design Project Stanford University Page No.
More informationLecture 240 Cascode Op Amps (3/28/10) Page 240-1
Lecture 240 Cascode Op Amps (3/28/10) Page 2401 LECTURE 240 CASCODE OP AMPS LECTURE ORGANIZATION Outline Lecture Organization Single Stage Cascode Op Amps Two Stage Cascode Op Amps Summary CMOS Analog
More informationA Unity Gain Fully-Differential 10bit and 40MSps Sample-And-Hold Amplifier in 0.18μm CMOS
A Unity Gain Fully-Differential 0bit and 40MSps Sample-And-Hold Amplifier in 0.8μm CMOS Sanaz Haddadian, and Rahele Hedayati Abstract A 0bit, 40 MSps, sample and hold, implemented in 0.8-μm CMOS technology
More informationHomework Assignment EE 435 Homework 4 Spring 2014 Due Wednesday Feb 26
Homework Assignment EE 435 Homework 4 Spring 2014 Due Wednesday Feb 26 In the following problems, if reference to a semiconductor process is needed, assume processes with the following characteristics:
More informationChapter 12 Opertational Amplifier Circuits
1 Chapter 12 Opertational Amplifier Circuits Learning Objectives 1) The design and analysis of the two basic CMOS op-amp architectures: the two-stage circuit and the single-stage, folded cascode circuit.
More informationAdvanced Operational Amplifiers
IsLab Analog Integrated Circuit Design OPA2-47 Advanced Operational Amplifiers כ Kyungpook National University IsLab Analog Integrated Circuit Design OPA2-1 Advanced Current Mirrors and Opamps Two-stage
More informationPerformance Analysis of Low Power, High Gain Operational Amplifier Using CMOS VLSI Design
RESEARCH ARTICLE OPEN ACCESS Performance Analysis of Low Power, High Gain Operational Amplifier Using CMOS VLSI Design Ankush S. Patharkar*, Dr. Shirish M. Deshmukh** *(Department of Electronics and Telecommunication,
More informationA 16Ω Audio Amplifier with 93.8 mw Peak loadpower and 1.43 quiscent power consumption
A 16Ω Audio Amplifier with 93.8 mw Peak loadpower and 1.43 quiscent power consumption IEEE Transactions on circuits and systems- Vol 59 No:3 March 2012 Abstract A class AB audio amplifier is used to drive
More informationA Compact 2.4V Power-efficient Rail-to-rail Operational Amplifier. Strong inversion operation stops a proposed compact 3V power-efficient
A Compact 2.4V Power-efficient Rail-to-rail Operational Amplifier Abstract Strong inversion operation stops a proposed compact 3V power-efficient rail-to-rail Op-Amp from a lower total supply voltage.
More informationDESIGN OF A FULLY DIFFERENTIAL HIGH-SPEED HIGH-PRECISION AMPLIFIER
DESIGN OF A FULLY DIFFERENTIAL HIGH-SPEED HIGH-PRECISION AMPLIFIER Mayank Gupta mayank@ee.ucla.edu N. V. Girish envy@ee.ucla.edu Design I. Design II. University of California, Los Angeles EE215A Term Project
More informationAnalysis and Design of Analog Integrated Circuits Lecture 8. Cascode Techniques
Analysis and Design of Analog Integrated Circuits Lecture 8 Cascode Techniques Michael H. Perrott February 15, 2012 Copyright 2012 by Michael H. Perrott All rights reserved. Review of Large Signal Analysis
More informationLecture 2, Amplifiers 1. Analog building blocks
Lecture 2, Amplifiers 1 Analog building blocks Outline of today's lecture Further work on the analog building blocks Common-source, common-drain, common-gate Active vs passive load Other "simple" analog
More informationWhat is the typical voltage gain of the basic two stage CMOS opamp we studied? (i) 20dB (ii) 40dB (iii) 80dB (iv) 100dB
Department of Electronic ELEC 5808 (ELG 6388) Signal Processing Electronics Final Examination Dec 14th, 2010 5:30PM - 7:30PM R. Mason answer all questions one 8.5 x 11 crib sheets allowed 1. (5 points)
More informationJames Lunsford HW2 2/7/2017 ECEN 607
James Lunsford HW2 2/7/2017 ECEN 607 Problem 1 Part A Figure 1: Negative Impedance Converter To find the input impedance of the above NIC, we use the following equations: V + Z N V O Z N = I in, V O kr
More informationUniversity of Michigan, EECS413 Final project. A High Speed Operational Amplifier. 1. A High Speed Operational Amplifier
University of Michigan, EECS413 Final project. A High Speed Operational Amplifier. 1 A High Speed Operational Amplifier A. Halim El-Saadi, Mohammed El-Tanani, University of Michigan Abstract This paper
More informationNOVEMBER 29, 2017 COURSE PROJECT: CMOS TRANSIMPEDANCE AMPLIFIER ECG 720 ADVANCED ANALOG IC DESIGN ERIC MONAHAN
NOVEMBER 29, 2017 COURSE PROJECT: CMOS TRANSIMPEDANCE AMPLIFIER ECG 720 ADVANCED ANALOG IC DESIGN ERIC MONAHAN 1.Introduction: CMOS Transimpedance Amplifier Avalanche photodiodes (APDs) are highly sensitive,
More informationLecture 34: Designing amplifiers, biasing, frequency response. Context
Lecture 34: Designing amplifiers, biasing, frequency response Prof J. S. Smith Context We will figure out more of the design parameters for the amplifier we looked at in the last lecture, and then we will
More informationVoltage Feedback Op Amp (VF-OpAmp)
Data Sheet Voltage Feedback Op Amp (VF-OpAmp) Features 55 db dc gain 30 ma current drive Less than 1 V head/floor room 300 V/µs slew rate Capacitive load stable 40 kω input impedance 300 MHz unity gain
More informationProblem 1. Final Exam Spring 2018 (Reposted 11p.m. on April 30)
EE 435 Final Exam Spring 2018 (Reposted 11p.m. on April 30) Name Instructions: This is an open-book, open-notes exam. It is due in the office of the course instructor by 12:00 noon on Wednesday May 2.
More informationBeta Multiplier and Bandgap Reference Design
ECE 4430 Project -1 Beta Multiplier and Bandgap Reference Design Aneesh PravinKulkarni Fall 2014 I have neither given nor received any unauthorized assistance on this project Beta Multiplier - Design Procedure
More informationHomework Assignment 06
Question 1 (2 points each unless noted otherwise) Homework Assignment 06 1. True or false: when transforming a circuit s diagram to a diagram of its small-signal model, we replace dc constant current sources
More informationYou will be asked to make the following statement and provide your signature on the top of your solutions.
1 EE 435 Name Exam 1 Spring 216 Instructions: The points allocated to each problem are as indicated. Note that the first and last problem are weighted more heavily than the rest of the problems. On those
More informationSolid State Devices & Circuits. 18. Advanced Techniques
ECE 442 Solid State Devices & Circuits 18. Advanced Techniques Jose E. Schutt-Aine Electrical l&c Computer Engineering i University of Illinois jschutt@emlab.uiuc.edu 1 Darlington Configuration - Popular
More informationTWO AND ONE STAGES OTA
TWO AND ONE STAGES OTA F. Maloberti Department of Electronics Integrated Microsystem Group University of Pavia, 7100 Pavia, Italy franco@ele.unipv.it tel. +39-38-50505; fax. +39-038-505677 474 EE Department
More informationLow voltage, low power, bulk-driven amplifier
University of Arkansas, Fayetteville ScholarWorks@UARK Electrical Engineering Undergraduate Honors Theses Electrical Engineering 5-2009 Low voltage, low power, bulk-driven amplifier Shama Huda University
More informationEE 501 Lab 4 Design of two stage op amp with miller compensation
EE 501 Lab 4 Design of two stage op amp with miller compensation Objectives: 1. Design a two stage op amp 2. Investigate how to miller compensate a two-stage operational amplifier. Tasks: 1. Build a two-stage
More informationTopology Selection: Input
Project #2: Design of an Operational Amplifier By: Adrian Ildefonso Nedeljko Karaulac I have neither given nor received any unauthorized assistance on this project. Process: Baker s 50nm CAD Tool: Cadence
More information1. The fundamental current mirror with MOS transistors
1. The fundamental current mirror with MOS transistors The test schematic (ogl-simpla-mos.asc): 1. Size the transistors in the mirror for a current gain equal to unity, a 30μA input current and V DSat
More informationEECE488: Analog CMOS Integrated Circuit Design Set 7 Opamp Design
EECE488: Analog CMOS Integrated Circuit Design Set 7 Opamp Design References: Analog Integrated Circuit Design by D. Johns and K. Martin and Design of Analog CMOS Integrated Circuits by B. Razavi All figures
More informationAnalog CMOS Interface Circuits for UMSI Chip of Environmental Monitoring Microsystem
Analog CMOS Interface Circuits for UMSI Chip of Environmental Monitoring Microsystem A report Submitted to Canopus Systems Inc. Zuhail Sainudeen and Navid Yazdi Arizona State University July 2001 1. Overview
More informationCHAPTER 3 DESIGN OF PIPELINED ADC USING SCS-CDS AND OP-AMP SHARING TECHNIQUE
CHAPTER 3 DESIGN OF PIPELINED ADC USING SCS-CDS AND OP-AMP SHARING TECHNIQUE 3.1 INTRODUCTION An ADC is a device which converts a continuous quantity into discrete digital signal. Among its types, pipelined
More informationAnalysis and Design of Analog Integrated Circuits Lecture 20. Advanced Opamp Topologies (Part II)
Analysis and Design of Analog Integrated Circuits Lecture 20 Advanced Opamp Topologies (Part II) Michael H. Perrott April 15, 2012 Copyright 2012 by Michael H. Perrott All rights reserved. Outline of Lecture
More informationRail to Rail Input Amplifier with constant G M and High Unity Gain Frequency. Arun Ramamurthy, Amit M. Jain, Anuj Gupta
1 Rail to Rail Input Amplifier with constant G M and High Frequency Arun Ramamurthy, Amit M. Jain, Anuj Gupta Abstract A rail to rail input, 2.5V CMOS input amplifier is designed that amplifies uniformly
More informationDesign of a Folded Cascode Operational Amplifier in a 1.2 Micron Silicon-Carbide CMOS Process
University of Arkansas, Fayetteville ScholarWorks@UARK Electrical Engineering Undergraduate Honors Theses Electrical Engineering 5-2017 Design of a Folded Cascode Operational Amplifier in a 1.2 Micron
More informationECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN
ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN OPAMP DESIGN AND SIMULATION Vishal Saxena OPAMP DESIGN PROJECT R 2 v out v in /2 R 1 C L v in v out V CM R L V CM C L V CM -v in /2 R 1 C L (a) (b) R 2 ECE415/EO
More informationYou will be asked to make the following statement and provide your signature on the top of your solutions.
1 EE 435 Name Exam 1 Spring 2018 Instructions: The points allocated to each problem are as indicated. Note that the first and last problem are weighted more heavily than the rest of the problems. On those
More informationHomework Assignment 06
Homework Assignment 06 Question 1 (Short Takes) One point each unless otherwise indicated. 1. Consider the current mirror below, and neglect base currents. What is? Answer: 2. In the current mirrors below,
More informationHigh Voltage Operational Amplifiers in SOI Technology
High Voltage Operational Amplifiers in SOI Technology Kishore Penmetsa, Kenneth V. Noren, Herbert L. Hess and Kevin M. Buck Department of Electrical Engineering, University of Idaho Abstract This paper
More informationDesign of Low Voltage Low Power CMOS OP-AMP
RESEARCH ARTICLE OPEN ACCESS Design of Low Voltage Low Power CMOS OP-AMP Shahid Khan, Prof. Sampath kumar V. Electronics & Communication department, JSSATE ABSTRACT Operational amplifiers are an integral
More information0.85V. 2. vs. I W / L
EE501 Lab3 Exploring Transistor Characteristics and Design Common-Source Amplifiers Lab report due on September 22, 2016 Objectives: 1. Be familiar with characteristics of MOSFET such as gain, speed, power,
More informationLecture 200 Cascode Op Amps - II (2/18/02) Page 200-1
Lecture 200 Cascode Op Amps II (2/18/02) Page 2001 LECTURE 200 CASCODE OP AMPS II (READING: GHLM 443453, AH 293309) Objective The objective of this presentation is: 1.) Develop cascode op amp architectures
More informationRevision History. Contents
Revision History Ver. # Rev. Date Rev. By Comment 0.0 9/15/2012 Initial draft 1.0 9/16/2012 Remove class A part 2.0 9/17/2012 Comments and problem 2 added 3.0 10/3/2012 cmdmprobe re-simulation, add supplement
More informationAnalog Integrated Circuits Fundamental Building Blocks
Analog Integrated Circuits Fundamental Building Blocks Basic OTA/Opamp architectures Faculty of Electronics Telecommunications and Information Technology Gabor Csipkes Bases of Electronics Department Outline
More informationRail-To-Rail Output Op-Amp Design with Negative Miller Capacitance Compensation
Rail-To-Rail Op-Amp Design with Negative Miller Capacitance Compensation Muhaned Zaidi, Ian Grout, Abu Khari bin A ain Abstract In this paper, a two-stage op-amp design is considered using both Miller
More informationA new class AB folded-cascode operational amplifier
A new class AB folded-cascode operational amplifier Mohammad Yavari a) Integrated Circuits Design Laboratory, Department of Electrical Engineering, Amirkabir University of Technology, Tehran, Iran a) myavari@aut.ac.ir
More informationA Fully Differential Transconductance Amplifier. --EE240 final project, Spring 2001
A Fully Differential Transconductance Amplifier --EE40 final project, Spring 00 Shiying Xiong (xiongsy@eecs.berkeley.edu) Min She(mshe@tft.eecs.berkeley.edu) Department of Electrical Engineering and omputer
More informationDesign and implementation of two stage operational amplifier
Design and implementation of two stage operational amplifier Priyanka T 1, Dr. H S Aravind 2, Yatheesh Hg 3 1M.Tech student, Dept, of ECE JSSATE Bengaluru 2Professor and HOD, Dept, of ECE JSSATE Bengaluru
More informationEE140: Lab 5, Project Week 2
EE140: Lab 5, Project Week 2 VGA Op-amp Introduction For this lab, you will be developing the background and circuits that you will need to get your final project to work. You should do this with your
More informationAdvanced OPAMP Design
Advanced OPAMP Design Two Stage OPAMP with Cascoding To increase the gain, the idea of cascoding can be combined with the idea of cascading. A two stage amplifier with one stage being cascode is possible.
More informationA 24 V Chopper Offset-Stabilized Operational Amplifier with Symmetrical RC Notch Filters having sub-10 µv offset and over-120db CMRR
ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY Volume 20, Number 4, 2017, 301 312 A 24 V Chopper Offset-Stabilized Operational Amplifier with Symmetrical RC Notch Filters having sub-10 µv offset
More informationLow Power and Fast Transient High Swing CMOS Telescopic Operational Amplifier
RESEARCH ARTICLE OPEN ACCESS Low Power and Fast Transient High Swing CMOS Telescopic Operational Amplifier Akshay Kumar Kansal 1, Asst Prof. Gayatri Sakya 2 Electronics and Communication Department, 1,2
More informationHomework Assignment 07
Homework Assignment 07 Question 1 (Short Takes). 2 points each unless otherwise noted. 1. A single-pole op-amp has an open-loop low-frequency gain of A = 10 5 and an open loop, 3-dB frequency of 4 Hz.
More informationA 12-bit Interpolated Pipeline ADC using Body Voltage Controlled Amplifier
A 12-bit Interpolated Pipeline ADC using Body Voltage Controlled Amplifier Hyunui Lee, Masaya Miyahara, and Akira Matsuzawa Tokyo Institute of Technology, Japan Outline Background Body voltage controlled
More informationA low voltage rail-to-rail operational amplifier with constant operation and improved process robustness
Graduate Theses and Dissertations Graduate College 2009 A low voltage rail-to-rail operational amplifier with constant operation and improved process robustness Rien Lerone Beal Iowa State University Follow
More informationA Novel Design of Low Voltage,Wilson Current Mirror based Wideband Operational Transconductance Amplifier
A Novel Design of Low Voltage,Wilson Current Mirror based Wideband Operational Transconductance Amplifier Kehul A. Shah 1, N.M.Devashrayee 2 1(Associative Prof., Department of Electronics and Communication,
More informationDifferential Amplifier Design
Differential Amplifier Design Design with ideal current source bias. Differential and common mode gain results Add finite output resistance to current source. Replace ideal current source with current
More informationHomework Assignment 07
Homework Assignment 07 Question 1 (Short Takes). 2 points each unless otherwise noted. 1. A single-pole op-amp has an open-loop low-frequency gain of A = 10 5 and an open loop, 3-dB frequency of 4 Hz.
More informationDesign of a low voltage,low drop-out (LDO) voltage cmos regulator
Design of a low,low drop-out (LDO) cmos regulator Chaithra T S Ashwini Abstract- In this paper a low, low drop-out (LDO) regulator design procedure is proposed and implemented using 0.25 micron CMOS process.
More informationAnalog Integrated Circuits. Lecture 7: OpampDesign
Analog Integrated Circuits Lecture 7: OpampDesign ELC 601 Fall 2013 Dr. Ahmed Nader Dr. Mohamed M. Aboudina anader@ieee.org maboudina@gmail.com Department of Electronics and Communications Engineering
More informationSAMPLE FINAL EXAMINATION FALL TERM
ENGINEERING SCIENCES 154 ELECTRONIC DEVICES AND CIRCUITS SAMPLE FINAL EXAMINATION FALL TERM 2001-2002 NAME Some Possible Solutions a. Please answer all of the questions in the spaces provided. If you need
More informationDesign and Simulation of an Operational Amplifier with High Gain and Bandwidth for Switched Capacitor Filters
IOSR Journal of Electrical and Electronics Engineering (IOSR-JEEE) e-issn: 2278-1676,p-ISSN: 2320-3331, Volume 11, Issue 1 Ver. II (Jan. Feb. 2016), PP 47-53 www.iosrjournals.org Design and Simulation
More informationDesign of High Gain Low Voltage CMOS Comparator
Design of High Gain Low Voltage CMOS Comparator Shahid Khan 1 1 Rustomjee Academy for Global Careers Abstract: Comparators used in most of the analog circuits like analog to digital converters, switching
More informationDesign of a Sample and Hold Circuit using Rail to Rail Low Voltage Compact Operational Amplifier and bootstrap Switching
RESEARCH ARTICLE OPEN ACCESS Design of a Sample and Hold Circuit using Rail to Rail Low Voltage Compact Operational Amplifier and bootstrap Switching Annu Saini, Prity Yadav (M.Tech. Student, Department
More informationEE 501 Lab 11 Common mode feedback (CMFB) circuit
EE 501 Lab 11 Common mode feedback (CMFB) circuit Objectives: Report due: November 17, 2016 1. Understand why CMFB circuits are needed and how they work to ensure robust operation. 2. Understand the advantages
More informationETIN25 Analogue IC Design. Laboratory Manual Lab 2
Department of Electrical and Information Technology LTH ETIN25 Analogue IC Design Laboratory Manual Lab 2 Jonas Lindstrand Martin Liliebladh Markus Törmänen September 2011 Laboratory 2: Design and Simulation
More informationECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers
ECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers Objective Design, simulate and layout various inverting amplifiers. Introduction Inverting amplifiers are fundamental building blocks of electronic
More informationBasic OpAmp Design and Compensation. Chapter 6
Basic OpAmp Design and Compensation Chapter 6 6.1 OpAmp applications Typical applications of OpAmps in analog integrated circuits: (a) Amplification and filtering (b) Biasing and regulation (c) Switched-capacitor
More informationRadivoje Đurić, 2015, Analogna Integrisana Kola 1
OTA-output buffer 1 According to the types of loads, the driving capability of the output stages differs. For switched capacitor circuits which have high impedance capacitive loads, class A output stage
More informationBasic OpAmp Design and Compensation. Chapter 6
Basic OpAmp Design and Compensation Chapter 6 6.1 OpAmp applications Typical applications of OpAmps in analog integrated circuits: (a) Amplification and filtering (b) Biasing and regulation (c) Switched-capacitor
More informationClass-AB Low-Voltage CMOS Unity-Gain Buffers
Class-AB Low-Voltage CMOS Unity-Gain Buffers Mariano Jimenez, Antonio Torralba, Ramón G. Carvajal and J. Ramírez-Angulo Abstract Class-AB circuits, which are able to deal with currents several orders of
More informationOperational Amplifier as A Black Box
Chapter 8 Operational Amplifier as A Black Box 8. General Considerations 8.2 Op-Amp-Based Circuits 8.3 Nonlinear Functions 8.4 Op-Amp Nonidealities 8.5 Design Examples Chapter Outline CH8 Operational Amplifier
More informationDesign of Rail-to-Rail Op-Amp in 90nm Technology
IJSTE - International Journal of Science Technology & Engineering Volume 1 Issue 2 August 2014 ISSN(online) : 2349-784X Design of Rail-to-Rail Op-Amp in 90nm Technology P R Pournima M.Tech Electronics
More informationHigh-Speed Serial Interface Circuits and Systems
High-Speed Serial Interface Circuits and Systems Design Exercise4 Charge Pump Charge Pump PLL ɸ ref up PFD CP LF VCO down ɸ out ɸ div Divider Converts PFD phase error pulse (digital) to charge (analog).
More informationEE140: Lab 5, Project Week 2
Introduction EE140: Lab 5, Project Week 2 VGA Op-amp Group Presentations: 4/13 and 4/14 in Lab Slide Submission: 4/15/17 (9 am) For this lab, you will be developing the background and circuits that you
More informationIJSRD - International Journal for Scientific Research & Development Vol. 4, Issue 02, 2016 ISSN (online):
IJSRD - International Journal for Scientific Research & Development Vol. 4, Issue 02, 2016 ISSN (online): 2321-0613 Design & Analysis of CMOS Telescopic Operational Transconductance Amplifier (OTA) with
More informationHOME ASSIGNMENT. Figure.Q3
HOME ASSIGNMENT 1. For the differential amplifier circuit shown below in figure.q1, let I=1 ma, V CC =5V, v CM = -2V, R C =3kΩ and β=100. Assume that the BJTs have v BE =0.7 V at i C =1 ma. Find the voltage
More informationTHE increased complexity of analog and mixed-signal IC s
134 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 2, FEBRUARY 1999 An Integrated Low-Voltage Class AB CMOS OTA Ramesh Harjani, Member, IEEE, Randy Heineke, Member, IEEE, and Feng Wang, Member, IEEE
More informationDesign of High Gain Two stage Op-Amp using 90nm Technology
Design of High Gain Two stage Op-Amp using 90nm Technology Shaik Aqeel 1, P. Krishna Deva 2, C. Mahesh Babu 3 and R.Ganesh 4 1 CVR College of Engineering/UG Student, Hyderabad, India 2 CVR College of Engineering/UG
More informationChapter 10 Feedback ECE 3120 Microelectronics II Dr. Suketu Naik
1 Chapter 10 Feedback Operational Amplifier Circuit Components 2 1. Ch 7: Current Mirrors and Biasing 2. Ch 9: Frequency Response 3. Ch 8: Active-Loaded Differential Pair 4. Ch 10: Feedback 5. Ch 11: Output
More informationCommon Gate Stage Cascode Stage. Claudio Talarico, Gonzaga University
Common Gate Stage Cascode Stage Claudio Talarico, Gonzaga University Common Gate Stage The overdrive due to V B must be consistent with the current pulled by the DC source I B careful with signs: v gs
More informationLecture 300 Low Voltage Op Amps (3/28/10) Page 300-1
Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-1 LECTURE 300 LOW VOLTAGE OP AMPS LECTURE ORGANIZATION Outline Introduction Low voltage input stages Low voltage gain stages Low voltage bias circuits
More information