An 8-bit Analog-to-Digital Converter based on the Voltage-Dependent Switching Probability of a Magnetic Tunnel Junction

Transcription

1 An 8-bit Analog-to-Digital Converter based on the Voltage-Dependent Switching Probability of a Magnetic Tunnel Junction Won Ho Choi*, Yang Lv*, Hoonki Kim, Jian-Ping Wang, and Chris H. Kim *equal contribution University of Minnesota, Minneapolis, MN Symposia on VLSI Technology and Circuits

2 Background Outline Analog-to-Digital Converter (ADC) Magnetic Tunnel Junction (MTJ) Proposed MTJ-based Probabilistic ADC Techniques for Improving Linearity and Input Voltage Range Summary Slide 1

3 Analog-to-Digital Converter (ADC) Analog Digital V IN D OUT Resolution: N bits (=2 N quantization steps) Analog Amplitude Digital Value time time ADC converts an analog input voltage to a digital code An N-bit ADC quantizes an analog voltage into 2 N discrete levels Slide 2

4 Traditional ADC Architectures Flash ADC Fast conversion rate (up to several Gs/s) High power consumption Low resolution (2 ~ 8 bit) V IN Thermometer to Binary Converter Dout Successive Approximation Register (SAR) ADC High resolution (10 ~ 16 bit) Low power consumption Slow conversion rate (1Ks/s ~ several 100Ms/s) V IN Vref 3Vref/4 V IN Vref DAC SAR logic Dout Vref/2 Vref/4 Dout: Slide 3

5 Magnetic Tunnel Junction (MTJ) Anti-parallel: High R Parallel: Low R I C e - STT switching Free layer Tunnel barrier Pinned layer e - I C STT switching Parallel Anti-parallel Basic storage element of STT-MRAM memory Spin polarized electrons rotate the magnetization of free layer using spin transfer torque Slide 4

6 Background Outline Analog-to-Digital Converter (ADC) Magnetic Tunnel Junction (MTJ) Proposed MTJ-based Probabilistic ADC Techniques for Improving Linearity and Input Voltage Range Summary Slide 5

7 Switching Probability of an MTJ Switching probability (%) P-AP switching AP-P switching t PERTURB 1000ns 500ns 100ns 50ns 10ns 5ns V MTJ (a.u.) H. Zhao, et al., TMAG, Switching probability depends on the applied analog voltage (V MTJ ) Slide 6

8 Proposed MTJ-Based Probabilistic ADC V IN Sample / hold circuit Bidirectional pulse generator Bit stream of 0's and 1's MTJ Sense Amp. Counter Count Register D OUT V REF V IN = 0.4V D OUT = : P(1) = 25% = V IN = 0.5V D OUT = : P(1) = 50% = V IN = 0.6V D OUT = = : P(1) = 75% Analog voltage random bit stream compute probability of 1 s digital code Slide 7

9 MTJ Device Used for Experiments CoFeB based in-plane MTJ device with a TMR of 88% and a thermal stability of 64 Slide 8

10 Experimental Setup Power Combiner (Picosecond TM ) Pulse Generator 1 (Agilent 81160A TM ) Perturb Pulse Generator 2 (HP 8110A TM ) Reset MTJ Bias-Tee (Picosecond TM ) Read Power Supply (Kepco BOP20-20 TM ) Kapton Heater 10kOhm Current Control ADC DAQ Board (NI USB-6343 TM ) K-type Thermocouple Cable Resistance V IN LabView TM Interface D OUT MTJ measurement setup with 1mV voltage resolution and <1 C temperature accuracy Slide 9

11 Probability (%) Measured Switching Probability Curve t PERTURB = 5ns bits / sample 2,048 bits / sample V IN (mv) C 85 C Probability (%) t PERTURB = 5ns V IN (mv) A short 5ns t PERTURB used for suppressing thermal activation switching Averaging more bits gives a smoother and more accurate probability curve (128 bits vs. 2,048 bits) Temperature sensitivity is acceptably low C 85 C Slide 10

12 ADC Non-Linearity Metrics: Differential Non-Linearity (DNL) Integral Non-Linearity (INL) Ideal ADC Real ADC Digital Output LSB Digital Output DNL+1LSB INL 000 Input range 000 Analog Input Analog Input Slide 11

13 Measured Worst Case DNL and INL Worst case DNL (LSB) C 85 C t PERTURB = 5ns 1LSB = 4mV Worst case INL (LSB) Our target 30 C 85 C t PERTURB = 5ns 1LSB = 4mV # of bits / sample # of bits / sample A 5-bit ADC resolution is assumed (i.e. 1LSB = 4mV) DNL of 1 LSB can be achieved by averaging more random bits (e.g. 2,048 bits) INL cannot be improved by simply averaging more bits Slide 12

14 Background Outline Analog-to-Digital Converter (ADC) Magnetic Tunnel Junction (MTJ) Proposed MTJ-based Probabilistic ADC Techniques for Improving Linearity and Input Voltage Range Summary Slide 13

15 One-time Digital Calibration for Improving INL Probability (%) MTJ Counter + Register DOUT Linearizer V IN D OUT_CAL V IN 1bit Accumulator + DAC MTJ-based ADC D OUT Look Up Table Moving Average Filter D OUT_CAL J. Kim, et al., TCAS-I, 2010, J. Daniels, et al., VLSI Circuits Symposium, Basic idea: Pre-calibrate MTJ transfer curve and store the inverse function in a look-up table to compensate for inherent non-linearity Slide 14

16 DNL (LSB) INL (LSB) Measured DNL and 85 C Before digital calibration DNL MAX = / INL MAX = / ,048 bits / 85ºC t PERTURB = 5ns Digital Out After digital calibration DNL MAX = / LSB INL MAX = / ,048 bits / 85ºC t PERTURB = 5ns Digital Out Target DNL / INL of 1 LSB can be met after one-time calibration ADC resolution limited to 5-bit due to narrow input voltage range Slide 15

17 Proposed Input Range Enhancement Technique Original scheme V MTJ MTJ 0V Proposed scheme V MTJ MTJ Probability (%) Probability (%) 1X Input range (V IN,DYN ) V OFFSET = 0V V OFFSET = V IN,DYN V IN V OFFSET 2X Input range (2 V IN,DYN ) V IN Slide 16

18 Implementation of Input Range Enhancement Technique V IN Sample / hold circuit Bidirectional pulse generator MTJ Sense Amp. Bit stream of 0's and 1's Counter Count Register D OUT V OFFSET V REF Analog buffer Volt. divider for 2 M V OFFSETs Input range enhancement technique A voltage divider and an analog buffer control the MTJ bottom node voltage Slide 17

19 Measured Probability and Corresponding Digital Output Probability (%) Digital Output ,048 bits / 85ºC Voffset = -384mV -256mV -128mV 0V 128mV 256mV 384mV 512mV MSB: V IN (mv) t PERTURB = 5ns 8x wider input voltage range 3 additional bits Slide 18

20 Measured DNL and 85 C DNL (LSB) INL (LSB) Before digital calibration DNL MAX = / ,048 bits / 85ºC t PERTURB = 5ns After digital calibration DNL MAX = / LSB 2,048 bits / 85ºC t PERTURB = 5ns -1 INL MAX = / INL -2 MAX = / Digital Out Digital Out Target DNL / INL of 1 LSB can be met after calibration 8-bit ADC resolution with good linearity is achieved Slide 19

21 ADC Performance Summary 2,048 bits / sample 30 ºC 85 ºC Input range DNL MAX (LSB) INL MAX (LSB) Bits DNL MAX (LSB) INL MAX (LSB) Bits Original MTJ-based ADC 128mV (X1) Digital calibration 128mV (X1) Digital calibration + Input range enhancement 1024mV (X8) ADC resolution (=8 bit) was limited by the minimum voltage step (=1mV) of pulse generator. Actual resolution could be as high as 14 bits. Slide 20

22 Summary An 8-bit resolution MTJ-based ADC with excellent linearity demonstrated for the first time 2,048 bits averaged to generate one ADC sample Insensitive to temperature using a 5ns pulse width Digital calibration and input range enhancement techniques Acknowledgement This work was supported in part by C-SPIN, one of six centers of STARnet, a Semiconductor Research Corporation program, sponsored by MARCO and DARPA Slide 21