Data Converters. Lecture Fall2013 Page 1

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1 Data Converters Lecture Fall2013 Page 1

2 Lecture Fall2013 Page 2 Representing Real Numbers Limited # of Bits Many physically-based values are best represented with realnumbers as opposed to a discrete number of values. However, in computers we are practically limited in the number of distinct values we can represent. So, how can we represent real numbers? -> We create a mapping of codes to physical values such as the following.

3 Lecture Fall2013 Page 3 Choosing Quantization Levels Can only pick 8 real-valued points called quantization levels

4 Lecture Fall2013 Page 4 Digital Code to Real Value Mapping Quantization: "rounding" of real number to one of a limited set realnumbered quantization levels Quantization error is the difference between a desired real number and its quantized value Coding: mapping of set of real numbers to a digital code

5 Comparison to binary number representation Common binary coding uses POWERS OF 2 for bit weightings: The A/D coding just described uses realvalued weightings instead, increased by powers of two: The step size between quantization levels corresponds to the real-value weighting of the LSB: Lets represent the voltage range [0 V, 10 V) with a three bit code Value Vref/ Vref/ Vref/ Vref/ Vref/ Vref/ Vref/ Vref/8 Lecture Fall2013 Page 5

6 Lecture Fall2013 Page 6 A Digital to Analog Converters (DAC) A common circuit provides binary-weighted contributions: relies on digital outputs matching voltages requires many different precise, accurate resistances

7 R-2-R Ladder DAC Only 2 precise resistor values are required, value doesn't matter as much matching among them The error of each resistor spread across codes more than previous Monolithic implementations available (constrains errors to guarantee that increasing code always corresponds to a higher value...important for some feedback and control applications) Lecture Fall2013 Page 7

8 Lecture Fall2013 Page 8 Current-Output DACs Output is current instead of voltage Common for high-speed converters Voltage can be set using a resistor or by a user-selected external high-speed active current-to-voltage converter

9 Lecture Fall2013 Page 9 PWM-based DAC A cheap DAC can be built using digital driver and a lowpass filter. The duty cycle of the digital signal sets the analog output level.

Lecture Fall2013 Page 10 ADC An analog-to-digital conversion (abbreviated ADC, A/D or A to D) is a process that converts a continuous quantity (continuous in time and possible values ) to

10 Lecture Fall2013 Page 10 ADC An analog-to-digital conversion (abbreviated ADC, A/D or A to D) is a process that converts a continuous quantity (continuous in time and possible values ) to a discrete-time, discrete value (digital) representation ADC is: Mapping to discrete values Updating/defining value at discrete times* *discrete value continuous-time converters are possible

11 Lecture Fall2013 Page 11 Analog Waveform to Digital Waveform Mapping Continuous Voltage to Digital Codes...together make a discrete-valued signal with updates at discrete times Discrete Time Measurements

12 Lecture Fall2013 Page 12 ADC ADCs may use Single or parallel stages Single conversion step or successive approximation steps One or multiple clock cycles The various architectures trade off the performance metrics discussed, as well as cost, power, size, etc...

13 Lecture Fall2013 Page 13 Common ADC Architectures Trends Flash Pipelined Successive-Approximation Sigma-Delta Flash: uses parallel stages for speed, precision/accuracy is sacrificed by needing many so many parts matched Pipelined: uses multiple stages to resolve signal, good throughput but larger latency Successive Approximation and Algorithmic: uses multiple iterations to resolve signal, slow Algorithmic: uses multiple iterations to resolve signal, slow Sigma-Delta: performs fast conversion on signal changes but effectively slow sensing/detections of total signal/large changes

14 Lecture Fall2013 Page 14 Performance Metrics Sample rate/ throughput: number of measurements of amplitude per second. Higher sampling rates are better but increase data-rates, power, cost, etc... How fast is fast enough? The commonly-cited value is 2-times the frequency of the highest frequency component into the ADC, (this allows perfect reconstruction of the continuous waveform). Often an analog low-pass filter is used before the ADC to limit the required sampling frequency. Sometimes a technique call oversampling is used: it involves sample faster than needed and digitally averaging results to remove some noise. For AVR, see application note Latency: time between sampling a voltage and getting the corresponding value

15 Lecture Fall2013 Page 15 Performance Metrics Bit depth :determines number of discrete values that can be represented, sets bound on combination of precision and range of each measurement of amplitude. Precision vs Accuracy: If the offset of the measured value from the true value maters, you care about accuracy. If you care how small of a voltage step you can resolve you care about precision. Often these ideas are combined under the umbrella term "accuracy" (Look up INL/DNL: integral and differential error to find formal metrics used for converters.) Monolithic: means that digital codes strictly increase when analog voltage increases

16 Lecture Fall2013 Page 16 Differential and Pseudo-differential Input Differential input is useful when the potential to be measured is not referenced to ground. It is also useful for rejecting noise on ground or differences between grounds <- Noise between grounds -> Pseudo-differential is like differential but Vin- pin must be close in terms of voltage to ground. (~.7) and is used only for noise rejection.

17 Lecture Fall2013 Page 17 Sample-and-Hold A Sample and Hold (S/H) is required to hold an analog signal while a (initial) conversion can complete The most basic S/H is a switch and a capacitor. Hold

18 Lecture Fall2013 Page 18 Sample and Hold - Driving Sampling Capacitor For fast operation, a driver must be able to set the capacitor quickly and accurately. For fast settling a small RC is required, i.e. a low output resistance is required by the driver. For this purpose, the ADC datasheet may specify a maximum output impedance for the driver along with a minimum current drive ability. Some ADCs include a internal "Track and Hold" buffer to drive the sample capacitance

19 Lecture Fall2013 Page 19 Sample and Hold - Droop A Sample-and-Hold is required to Hold the signal while a conversion can start/complete The switch is implemented with FET that unfortunately leaks current and causes droop during hold. So, hold times can not be indefinite and thus ADC's often require a minimum clock rate to ensure processing happens quickly enough

20 Common Analog to Digital (ADC) Architectures Lecture Fall2013 Page 20

21 N-bit Flash ADC Lecture Fall2013 Page 21

22 Lecture Fall2013 Page 22 Digital Ramp ADC An analog approximation "guess" is made by increasing a digital code to a DAC. Once the analog approximation crosses the input, waveform is reached, the digital code is saved

23 Lecture Fall2013 Page 23 Tracking ADC An analog approximation "guess" is made by stepping the previous digital code up or down each cycle. This is fast and works well if the analog input waveform doesn't move too quickly.

24 Lecture Fall2013 Page 24 Integrating Reference Ramp ADC An analog approximation is made in the analog domain by integrating a constant current onto a capacitor. A digital timer determines the analog value by the time needed for the approximation to reach the analog input.

25 Lecture Fall2013 Page 25 Dual-Slope ADC Measures time to discharge a capacitor based on input signal Very precise, but slow Value based on one R and one C (Assuming amplifier gain is large), but can be calibrated

26 Lecture Fall2013 Page 26 Pipelined-ADC breaks conversion up into several stages Has inherent latency

27 Lecture Fall2013 Page 27 Algorithmic ADC -multiplies residual error rather than rather than converting successively smaller signals

28 Lecture Fall2013 Page 28 Successive-Approximation ADC slower than flash, takes several iterations accuracy determined by DAC & Comparator

29 Lecture Fall2013 Page 29 Sigma-Delta ADC Idea: sample signal and sense only changes and do it so fast that only small changes need to be digitized using lowresolution components sigma-delta.pdf

30 Lecture Fall2013 Page 30 Sigma-Delta DAC basically swap digital and analog parts

31 Lecture Fall2013 Page 31 ADC of Atmega169P 10-bit Resolution 0 - VCC ADC Input Voltage Range ADC clock can be 50KHz to 1MHz Full resolution (10 bits) frequency range 50KHz- 200KHz Up to 15 ksps at to get Maximum Resolution (200 khz ADC clock) NOTE the 200 khz ADC clock and compared to the 15 ksps spec.

32 Lecture Fall2013 Page 32

33 Lecture Fall2013 Page 33 Conversion Timing Each conversion takes 13 clocks, So, ADC clock = 200KHz----> 200KHZ/13HZ ~15K sample (15ksps) More Info: Characterization and Calibration of the ADC on an AVR 9.pdf

Outline. Analog/Digital Conversion

Outline. Analog/Digital Conversion Analog/Digital Conversion The real world is analog. Interfacing a microprocessor-based system to real-world devices often requires conversion between the microprocessor s digital representation of values