Testing report for MOSIS Educational Program (Research) Integrated Circuit for Implantable Sensor

Transcription

1 Testing report or MOSIS Educational Program (esearch) Project Title Integrated Circuit or Implantable Sensor Prepared by: F.C. Jain, Mo Zhang, and S.K. Islam Institution: Department o Electrical and Computer Engineering, Uniersity o Connecticut, Storrs, CT 0669 Department o Electrical and Computer Engineering, Uniersity o Tennessee, Knoxille, TN Date o Submission: /0/00 Mosis Fab-ID: TZAT

2 Project Description Two main issues or implantable sensors are long-term biocompatibility and power management. Electronic circuit using CMOS technology is one o the best candidates or designing the signal processing part due to its low power consumption and small size. The power will be transerred through inductie coupled links, thereore wire connections are eliminated and long-term stability o the deice is signiicantly enhanced. In igure, we present a generic implantable sensor that transorms the signals in biology enironments in term current leels. The electronic circuit integrated with the chemical part o the sensor will conert the sensed current to oltage, which can be transmitted outside the body through a F (radio requency) link. To be powered up by wireless connections, the most important requirement o the electronic part is capability o operating with ery low power consumption in order o microwatt or smaller. 0.mm CMOS Chip Mount Sensor Part 0 mm Figure. Simpliication o an implantable sensor Fabrication Process We chose CMOS TSMC 0.3µm process or this design because o its capability to implement low oltage supply, low power and reasonable cost designs. In this submit, we will include the light power source using Silicon solar cells and the design (except the sensor) in the same chip. The chip is designed in TSMC 0.3 µm process and is targeted or May 00 run. Simulation and Layout Plans The circuits are simulated using Synopsys Hspice and Cadence s Spectre. Hspice is used or most o the time domain simulations. Layout is done using Cadence Virtuoso and the LVS clean layout is extracted with resistie and capacitie parasitics. The extracted netlist is simulated and compared with the simulation results rom the schematic netlist. Both the schematic and post-layout simulations are done across all process corners and a temperature range o -0 to 0 degree C. A brie description o the schematics, simulation waeorms and perormance is gien below. Implantable sensor

3 The block diagram o implantable sensor is shown in igure and the simulation results are gien in igure 3. This circuit is designed to be powered by itsel and send ASK signal, which can be receied and demodulated by a commercial radio. The sensor current is generated by the implantable chemical sensor part. The current leel is about 0.-µA. The requency out o the current sensor block is proportional to the sensor current. The square wae signal out o the carrier requency generator is about MHz. The NAND gate will modulate the current sensor signal with the carrier requency to create the ASK signal. A drier will be used to drie the antenna. Since the whole circuit is powered by on-chip solar cell. Eery component is designed to consume ery small power. A oltage regulator is designed to supply a stable V DD or the circuit. Which is ery important to create stable requency or both current sensor block and carrier requency generator, with a gien sensor current. Solar cell Voltage regulator Supply VDD or the whole circuit Sensor current Current Sensor block Signal requency Schmitt trigger Carrier requency nand Output Buer Schmitt trigger Output ASK signal Carrier requency generator Figure --- Implantable sensor design Figure 3--- Simulation results or the implantable glucose sensor 3

4 W W=Working =eerence C= Counter 0.7V C.Electrode Electrodes Work.E l e.el 0 U U U U eerenc 0k 0k Voltag e e GND Instrumentatio n ampliier Chemical Solution with the three electrodes orming the sensor Figure --- Schematic o potentiostat circuit Figure shows the schematic o potentiostat circuit. It will generate the current that need to be processed by the other part o the sensor. The oltage dierence between Working electrode and eerence electrode should always be about 0.7V. The current leel out o the Counter electrode will be transerred to the requency o the square wae output o the sensor circuit. Test esults The abricated chip will be tested in the Analog VLSI and Deices Laboratory. Tektronix TDS two-channel digital real-time oscilloscope are used to test the glucose sensor circuit. Both potentiostat and sensor work. The oltage between re_el and work_el is about 0.6V. The sensor's squarewae output requency is proportional to the current lows between re_el and work_el o the potentiostat. There are two kinds o sensor circuit. Both o them work. Channel B only creates square wae output. Channel A consumes less power with low VDD and send out ASK signal, which has carrier requency o MHz. The power consumption o channel A can be about mw. Channel B s power consumption is about mw.

5 Figure ----Channel B, resistor between work_el and e_el is 3k ohm. Square wae output requency is 3.9kHz. Figure 6----Channel B, resistor between work_el and e_el is 70k ohm. Square wae output requency is.0khz. V I 3kΩ 70kΩ work _ el V 3.9kHz =.0kHz e _ el, so we should hae 70kΩ 70k =.6, = =. 06 3k 3kΩ =

6 Figure 7----Channel A, resistor between work_el and e_el is 3k ohm. Square wae output requency is /00us=.kHz. Output requency has been diided by 3 with an on-chip programmable requency diider. ASK signal s carrier requency is about MHz. Figure 8----Channel A, resistor between work_el and e_el is 70k ohm. Square wae output requency is /83us=.kHz. Output requency has been diided by 3 with an on-chip programmable requency diider. ASK signal s carrier requency is about MHz. 3kΩ 70kΩ.kHz =.khz 70kΩ 70k =.08, = =. 06 3k 3kΩ 6