Basic Symbols for Register Transfers. Symbol Description Examples

Size: px
Start display at page:

Download "Basic Symbols for Register Transfers. Symbol Description Examples"

Transcription

1 T-58 Basic Symbols for Register Trasfers TABLE 7- Basic Symbols for Register Trasfers Symbol Descriptio Examples Letters Deotes a register AR, R2, DR, IR (ad umerals) Paretheses Deotes a part of a register R2(), R2(7:), AR(L) Arrow Deotes trasfer of data R R2 Comma Separates simultaeous trasfers R R2, R2 R Square brackets Specifies a address for memory DR M[ AR] 997 by Pretice-Hall, Ic. Simo & Schuster / A Viacom Compay Mao & Kime Upper Saddle River, New Jersey 7458

2 T-59 Arithmetic Microoperatios TABLE 7-2 Arithmetic Microoperatios Symbolic desigatio R R R2 R2 R2 R2 R2 R R R2 R R R R Descriptio Cotets of R plus R2 trasferred to R Complemet of the cotets of R2 ( s complemet) 2 s complemet of the cotets of R2 R plus 2 s complemet of R2 trasferred to R (subtractio) Icremet the cotets of R (cout up) Decremet the cotets of R (cout dow) 997 by Pretice-Hall, Ic. Simo & Schuster / A Viacom Compay Mao & Kime Upper Saddle River, New Jersey 7458

3 T-6 Logic Microoperatios TABLE 7-3 Logic Microoperatios Symbolic desigatio R R R R R2 R R R2 R R R2 Descriptio Logical bitwise NOT ( s complemet) Logical bitwise AND (clears bits) Logical bitwise OR (sets bits) Logical bitwise XOR (complemets bits) 997 by Pretice-Hall, Ic. Simo & Schuster / A Viacom Compay Mao & Kime Upper Saddle River, New Jersey 7458

4 T-6 Fuctio Table for Arithmetic Circuit TABLE 7-6 Fuctio Table for Arithmetic Circuit Select Iput G A Y C i S S Y C i C i all s G A (trasfer) G A (icremet) B G A B (add) G A B B G A B G A B (subtract) all s G A (decremet) G A (trasfer) 997 by Pretice-Hall, Ic. Simo & Schuster / A Viacom Compay Mao & Kime Upper Saddle River, New Jersey 7458

5 T-62 Fuctio Table for ALU TABLE 7-7 Fuctio Table for ALU Operatio Select S 2 S S C i Operatio Fuctio G A Trasfer A G A Icremet A G A B Additio G A B Add with carry iput of G A B A plus s complemet of B G A B Subtractio G A Decremet A G A Trasfer A X G A B AND X G A B OR X G A B XOR X G A NOT ( s complemet) 997 by Pretice-Hall, Ic. Simo & Schuster / A Viacom Compay Mao & Kime Upper Saddle River, New Jersey 7458

6 T-63 Fuctio Table for 4-Bit Barrel Shifter TABLE 7-8 Fuctio Table for 4-Bit Barrel Shifter Select Output S S Y 3 Y 2 Y Y Operatio D 3 D 2 D D No rotatio D 2 D D D 3 Rotate oe positio D D D 3 D 2 Rotate two positios D D 3 D 2 D Rotate three positios 997 by Pretice-Hall, Ic. Simo & Schuster / A Viacom Compay Mao & Kime Upper Saddle River, New Jersey 7458

7 T-64 G Select, H Select, ad MF Select Codes Defied i Terms of FS Codes G Select, H Select, ad MF Select Codes Defied i Terms of FS Codes FS MF Select G Select H Select Microoperatio F A F A F A B F A B F A B F A B F A F A F A B F A B F A B F A F sr A F sl A 997 by Pretice-Hall, Ic. Simo & Schuster / A Viacom Compay Mao & Kime Upper Saddle River, New Jersey 7458

8 T-65 Ecodig of Cotrol Word for the Datapath TABLE 7- Ecodig of Cotrol Word for the Datapath DA, AA, BA MB FS MD RW Fuctio Code Fuctio Code Fuctio Code Fuctio Code Fuctio Code R Register F A Fuctio No write R Costat F A Data I Write R2 F A B R3 F A B R4 F A B R5 F A B R6 F A R7 F A F A B F A B F A B F A F sr A F sl A 997 by Pretice-Hall, Ic. Simo & Schuster / A Viacom Compay Mao & Kime Upper Saddle River, New Jersey 7458

9 T-66 Examples of Microoperatios for the Datapath Usig Symbolic Notatio TABLE 7- Examples of Microoperatios for the Datapath, Usig Symbolic Notatio Microoperatio DA AA BA MB FS MD RW R R2 R3 R R2 R3 Register F A B Fuctio Write R4 sl R6 R4 R6 Register F sl A Fuctio Write R7 R7 R7 R7 Register F A Fuctio Write R R 2 R Costat F A B Fuctio Write Data out R3 R3 Register No Write R4 Data i R4 Data i Write R5 R5 R R Register F A B Fuctio Write 997 by Pretice-Hall, Ic. Simo & Schuster / A Viacom Compay Mao & Kime Upper Saddle River, New Jersey 7458

10 T-67 Examples of Microoperatios from Table 7-, Usig Biary Cotrol Words TABLE 7-2 Examples of Microoperatios from Table 7-, Usig Biary Cotrol Words Microoperatio DA AA BA MB FS MD RW R R2 R3 R4 sl R6 R7 R7 R R 2 Data out R3 R4 Data i R5 997 by Pretice-Hall, Ic. Simo & Schuster / A Viacom Compay Mao & Kime Upper Saddle River, New Jersey 7458

11 T-68 Iteractio betwee Datapath ad Cotrol Uit Cotrol sigals Cotrol iputs Cotrol uit Status sigals Datapath Data outputs Cotrol outputs Data iputs 997 by Pretice-Hall, Ic. Simo & Schuster / A Viacom Compay Mao & Kime Upper Saddle River, New Jersey 7458

12 T-69 Block Diagrams of Registers R (a) Register R 5 (b) Idividual bits of 8-bit register R2 PC(H) PC(L) (c) Numberig of 6-bit register (d) Two-part 6-bit register 997 by Pretice-Hall, Ic. Simo & Schuster / A Viacom Compay Mao & Kime Upper Saddle River, New Jersey 7458

13 T-7 Trasfer from R to R2 whe K = K Load Trasfer occurs here t t + R R2 Clock Clock K 997 by Pretice-Hall, Ic. Simo & Schuster / A Viacom Compay Mao & Kime Upper Saddle River, New Jersey 7458

14 T-7 Implemetatio of Add ad Subtract Microoperatios R2 C C Adder-Subtractor Select (S) X V C R Load K 997 by Pretice-Hall, Ic. Simo & Schuster / A Viacom Compay Mao & Kime Upper Saddle River, New Jersey 7458

15 T-72 Use of Multiplexers to Select betwee Two Registers R2 4 K2 K S MUX 4 Load R R 4 (a) Block diagram K2 K R2 REGISTER LOAD C 2 to MUX S R REGISTER LOAD D D D 2 D 3 R Q Q Q 2 Q 3 REGISTER LOAD A A A 2 A 3 Y Y B B B 2 B 3 Y 2 Y 3 D D D 2 D 3 C Q Q Q 2 Q 3 Clock C D D D 2 D 3 Q Q Q 2 Q 3 (b) Detailed logic 997 by Pretice-Hall, Ic. Simo & Schuster / A Viacom Compay MANO & KIME Upper Saddle River, New Jersey 7458

16 T-73 Sigle Bus versus Dedicated Multiplexers Select SSS2 Load LLL2 Load LLL2 S 2 to MUX R R Select S 2 to MUX R S S 3 to MUX 2 Bus R S 2 to MUX R2 R2 (a) Dedicated multiplexers (b) Sigle Bus 997 by Pretice-Hall, Ic. Simo & Schuster / A Viacom Compay MANO & KIME Upper Saddle River, New Jersey 7458

17 T-74 Three-State Bus versus Multiplexer Bus Load LLL2 Load L2LL Eable E2EE Load LOAD R Select 2 R R E Bus E 3 to MUX Bus R R Load E R E R2 R2 E (a) Register with bidirectioal iput-output lies ad symbol (b) Multiplexer bus (c) Three-state bus usig registers with bidirectioal lies 997 by Pretice-Hall, Ic. Simo & Schuster / A Viacom Compay Mao & Kime Upper Saddle River, New Jersey 7458

18 T-75 Memory Uit Coected to Address ad Data Buses Address bus decoder Timig ad cotrol Data bus destiatio decoder 2 3 Load 2 Eable Data bus source decoder 2 3 Eable A A A2 D2 D D k Address bus Data bus Read Write Memory 2 k x 997 by Pretice-Hall, Ic. Simo & Schuster / A Viacom Compay MANO & KIME Upper Saddle River, New Jersey 7458

19 T-76 Block Diagram of a Datapath Load eable A select B select D data Write A address B address Load R 2 2 Load R Load R2 2 3 MUX 2 3 MUX 2 3 Decoder Load R3 Register file 2 D address Costat i A data B data Destiatio select MB select S MUX B A Bus A B Bus B Address Out Data Out G select 4 A S 2: &C i B H select S A V C N Z Zero Detect MF select Arithmetic/logic uit (ALU) G MUX F F Shifter H Fuctio uit Data I MD select Bus D MUX D 997 by Pretice-Hall, Ic. Simo & Schuster / A Viacom Compay MANO & KIME Upper Saddle River, New Jersey 7458

20 T-77 Block Diagram of -Bit ALU A Data iput A Data iput B A A B B B -bit arithmetic/ logic uit (ALU) G G G Data output G Carry iput Operatio select { C i S S C out Carry output Mode select S by Pretice-Hall, Ic. Simo & Schuster / A Viacom Compay MANO & KIME Upper Saddle River, New Jersey 7458

21 T-78 Block Diagram of a Arithmetic Circuit C i A X B S B iput logic Y -bit parallel adder G = X + Y + C i S C out 997 by Pretice-Hall, Ic. Simo & Schuster / A Viacom Compay Mao & Kime Upper Saddle River, New Jersey 7458

22 T-79 B Iput Logic for Oe Stage of Arithmetic Circuit Iputs Output S S B i Y i Y i = Y i = B i Y i = B i S S Y i = B i (a) Truth table (b) Map Simplificatio: Y i = B i S + B i S 997 by Pretice-Hall, Ic. Simo & Schuster / A Viacom Compay Mao & Kime Upper Saddle River, New Jersey 7458

23 T-8 Logic Diagram of a 4-bit Arithmetic Circuit C i S S C A B X Y FA C G A B X Y FA C 2 G A 2 B 2 X 2 Y 2 FA C 3 G 2 A 3 B 3 X 3 FA G 3 Y 3 C 4 C out 997 by Pretice-Hall, Ic. Simo & Schuster / A Viacom Compay MANO & KIME Upper Saddle River, New Jersey 7458

24 T-8 Oe Stage of Logic Circuit S S S S 4 to MUX A i B i 2 G i S S Output G = A B ^ G = A B ^ G = A B G = A Operatio AND OR XOR NOT 3 (b) Fuctio Table (a) Logic Diagram 997 by Pretice-Hall, Ic. Simo & Schuster / A Viacom Compay Mao & Kime Upper Saddle River, New Jersey 7458

25 T-82 Oe Stage of ALU C i C i + A i B i Oe stage of arithmetic circuit 2 to MUX S G i S S S 2 Oe stage of logic circuit 997 by Pretice-Hall, Ic. Simo & Schuster / A Viacom Compay Mao & Kime Upper Saddle River, New Jersey 7458

26 T-83 4-Bit Basic Shifter A 3 A 2 A A Serial output L Serial output R I R I L S M U X S M U X S M U X S M U X S H 3 H 2 H H 997 by Pretice-Hall, Ic. Simo & Schuster / A Viacom Compay Mao & Kime Upper Saddle River, New Jersey 7458

27 T-84 4-Bit Barrel Shifter D 3 D 2 D D S S 3 2 S S M U X 3 2 S S M U X 3 2 S S M U X 3 2 S S M U X Y 3 Y 2 Y Y 997 by Pretice-Hall, Ic. Simo & Schuster / A Viacom Compay Mao & Kime Upper Saddle River, New Jersey 7458

28 T-85 Block Diagram of Datapath Usig the Register File ad Fuctio Uit m m Write D address A address D data 2 m x Register file B address m A data B data Costat i MB select MUX B Bus A Bus B Address out Data out FS 5 A B V C N Fuctio uit Z F Data i MD select MUX D 997 by Pretice-Hall, Ic. Simo & Schuster / A Viacom Compay MANO & KIME Upper Saddle River, New Jersey 7458

29 T-86 Datapath with Cotrol Variables RW Write D data DA D address 8 x Register file AA 3 2 A address A data B address B data 9 8 BA Costat i MB 7 Bus A MUX B Bus B Address out Data out A B V C N Z Fuctio uit FS 3 2 Data i MD MUX D Bus D (a) Block Diagram DA AA BA M B FS M D R W (b) Cotrol word 997 by Pretice-Hall, Ic. Simo & Schuster / A Viacom Compay MANO & KIME Upper Saddle River, New Jersey 7458

30 T-87 Simulatio of the Microoperatio Sequece i Table 7-2 Clock DA AA BA MB RW Costat i FS Data i MD R R R2 R3 R4 R5 R6 R7 Status bits Address out Data out C 8 FF C by Pretice-Hall, Ic. Simo & Schuster / A Viacom Compay MANO & KIME Upper Saddle River, New Jersey 7458

31 T-88 Covetioal ad Pipelied Datapaths Clock 3 s 3 3 s Register file Clock WB OF Register file 3 s 3 s MUX B s MUX B s OF EX s Fuctio uit 4 s 2 Fuctio uit 4 s MUX D s EX WB s 3 MUX D s (a) Covetioal (b) Pipelied 997 by Pretice-Hall, Ic. Simo & Schuster / A Viacom Compay MANO & KIME Upper Saddle River, New Jersey 7458

32 T-89 Assembly Lie Aalogy to Datapath Pipelie 997 by Pretice-Hall, Ic. Simo & Schuster / A Viacom Compay Mao & Kime Upper Saddle River, New Jersey 7458

33 T-9 Block Diagram of Pipelied Datapath OF Operad Fetch (OF) AA Costat i Register file A data B data BA MUX B MB OF EX Address out Data out 2 Execute (EX) FS V C N Z A Fuctio uit F B Data i EX WB 3 Write-back (WB) WB RW DA MD MUX D D data Register file (same as above) 997 by Pretice-Hall, Ic. Simo & Schuster / A Viacom Compay MANO & KIME Upper Saddle River, New Jersey 7458

34 T-9 Pipelie Executio Patter for Microoperatio Sequece i Table 7-2 Clock cycle R R2 R3 R4 sl R6 2 R7 R7 + 3 R R Data out R3 5 R4 Data i 6 R5 7 Microoperatio OF EX WB OF EX WB OF EX WB OF EX WB OF EX WB OF EX WB OF EX WB 997 by Pretice-Hall, Ic. Simo & Schuster / A Viacom Compay Mao & Kime Upper Saddle River, New Jersey 7458

ELEC 204 Digital Systems Design

ELEC 204 Digital Systems Design Fall 2013, Koç Uiversity ELEC 204 Digital Systems Desig Egi Erzi College of Egieerig Koç Uiversity,Istabul,Turkey eerzi@ku.edu.tr KU College of Egieerig Elec 204: Digital Systems Desig 1 Today: Datapaths

More information

Computer Hardware. Pipeline

Computer Hardware. Pipeline Computer Hardware Pipeline Conventional Datapath 2.4 ns is required to perform a single operation (i.e. 416.7 MHz). Register file MUX B 0.6 ns Clock 0.6 ns 0.2 ns Function unit 0.8 ns MUX D 0.2 ns c. Production

More information

RISC Central Processing Unit

RISC Central Processing Unit RISC Central Processing Unit Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Spring, 2014 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/

More information

Technical Explanation for Counters

Technical Explanation for Counters Techical Explaatio for ers CSM_er_TG_E Itroductio What Is a er? A er is a device that couts the umber of objects or the umber of operatios. It is called a er because it couts the umber of ON/OFF sigals

More information

Design of FPGA- Based SPWM Single Phase Full-Bridge Inverter

Design of FPGA- Based SPWM Single Phase Full-Bridge Inverter Desig of FPGA- Based SPWM Sigle Phase Full-Bridge Iverter Afarulrazi Abu Bakar 1, *,Md Zarafi Ahmad 1 ad Farrah Salwai Abdullah 1 1 Faculty of Electrical ad Electroic Egieerig, UTHM *Email:afarul@uthm.edu.my

More information

TMCM BLDC MODULE. Reference and Programming Manual

TMCM BLDC MODULE. Reference and Programming Manual TMCM BLDC MODULE Referece ad Programmig Maual (modules: TMCM-160, TMCM-163) Versio 1.09 August 10 th, 2007 Triamic Motio Cotrol GmbH & Co. KG Sterstraße 67 D 20357 Hamburg, Germay http:www.triamic.com

More information

Design of FPGA Based SPWM Single Phase Inverter

Design of FPGA Based SPWM Single Phase Inverter Proceedigs of MUCEET2009 Malaysia Techical Uiversities Coferece o Egieerig ad Techology Jue 20-22, 2009, MS Garde,Kuata, Pahag, Malaysia MUCEET2009 Desig of FPGA Based SPWM Sigle Phase Iverter Afarulrazi

More information

Subscriber Pulse Metering (SPM) Detection

Subscriber Pulse Metering (SPM) Detection Subscriber Pulse Meterig () Detectio Versatile telephoe call-charge ad security fuctios for PBX, Payphoe ad Pair-Gai applicatios - employig CML s family of 12kHz ad 16kHz ICs INNOVATIONS INV/Telecom//1

More information

TABLE 3-2 Truth Table for Code Converter Example

TABLE 3-2 Truth Table for Code Converter Example 997 by Prentice-Hall, Inc. Mano & Kime Upper Saddle River, New Jersey 7458 T-28 TABLE 3-2 Truth Table for Code Converter Example Decimal Digit Input BCD Output Excess-3 A B C D W Y Z 2 3 4 5 6 7 8 9 Truth

More information

Project Part 1 A. The task was to design a 4 to 1 multiplexer that uses 8 bit buses on the inputs with an output of a single 8 bit bus.

Project Part 1 A. The task was to design a 4 to 1 multiplexer that uses 8 bit buses on the inputs with an output of a single 8 bit bus. Project Part 1 A Circuit Description and Diagrams: The task was to design a 4 to 1 multiplexer that uses 8 bit buses on the inputs with an output of a single 8 bit bus. Shown below is a jpeg screenshot

More information

A Novel Three Value Logic for Computing Purposes

A Novel Three Value Logic for Computing Purposes Iteratioal Joural o Iormatio ad Electroics Egieerig, Vol. 3, No. 4, July 23 A Novel Three Value Logic or Computig Purposes Ali Soltai ad Saeed Mohammadi Abstract The aim o this article is to suggest a

More information

Chapter 3 Digital Logic Structures

Chapter 3 Digital Logic Structures Copyright The McGraw-HillCompaies, Ic. Permissio required for reproductio or display. Computig Layers Chapter 3 Digital Logic Structures Problems Algorithms Laguage Istructio Set Architecture Microarchitecture

More information

CP 405/EC 422 MODEL TEST PAPER - 1 PULSE & DIGITAL CIRCUITS. Time: Three Hours Maximum Marks: 100

CP 405/EC 422 MODEL TEST PAPER - 1 PULSE & DIGITAL CIRCUITS. Time: Three Hours Maximum Marks: 100 PULSE & DIGITAL CIRCUITS Time: Three Hours Maximum Marks: 0 Aswer five questios, takig ANY TWO from Group A, ay two from Group B ad all from Group C. All parts of a questio (a, b, etc. ) should be aswered

More information

Datapath Components. Control vs. Datapath, Registers, Adders (Binary Addition) Copyright (c) 2012 Sean Key

Datapath Components. Control vs. Datapath, Registers, Adders (Binary Addition) Copyright (c) 2012 Sean Key atapath Components Control vs. atapath, Registers, Adders (Binary Addition) Copyright (c) 2012 ean Key ata vs. Control Most digital circuits can be divided into two parts Control Circuitry to control the

More information

Delta- Sigma Modulator with Signal Dependant Feedback Gain

Delta- Sigma Modulator with Signal Dependant Feedback Gain Delta- Sigma Modulator with Sigal Depedat Feedback Gai K.Diwakar #1 ad V.Vioth Kumar *2 # Departmet of Electroics ad Commuicatio Egieerig * Departmet of Electroics ad Istrumetatio Egieerig Vel Tech Uiversity,Cheai,

More information

Zonerich AB-T88. MINI Thermal Printer COMMAND SPECIFICATION. Zonerich Computer Equipments Co.,Ltd MANUAL REVISION EN 1.

Zonerich AB-T88. MINI Thermal Printer COMMAND SPECIFICATION. Zonerich Computer Equipments Co.,Ltd  MANUAL REVISION EN 1. Zoerich AB-T88 MINI Thermal Priter COMMAND SPECIFICATION MANUAL REVISION EN. Zoerich Computer Equipmets Co.,Ltd http://www.zoerich.com Commad List Prit ad lie feed Prit ad carriage retur Trasmissio real-time

More information

Indicator No mark Single preset Dual preset DIN W144 H72mm DIN W48 H96mm No mark DIN W72 H72mm (4 digit) (6 digit) Counter/Timer

Indicator No mark Single preset Dual preset DIN W144 H72mm DIN W48 H96mm No mark DIN W72 H72mm (4 digit) (6 digit) Counter/Timer FX/FX/FX Series DIN W7 7, W8 96, W 7mm er/timer Features 6 iput modes ad output modes ig speed: cps/cps/kcps/kcps Selectable voltage iput (PNP) or No voltage iput (NPN) dditio of Up/Dow iput mode Wide

More information

Modulo 2 n +1 Arithmetic Units with Embedded Diminished-to-Normal Conversion

Modulo 2 n +1 Arithmetic Units with Embedded Diminished-to-Normal Conversion 2011 14th Euromicro Coferece o Digital System Desig Modulo 2 +1 Arithmetic Uits with Embedded Dimiished-to-Normal Coversio Evagelos Vassalos, Dimitris Bakalis Electroics Laboratory, Dept. of Physics Uiversity

More information

10GBASE-T. length of precoding response, and PMA training

10GBASE-T. length of precoding response, and PMA training 1GBASE-T TxFE solutios, dpsnr vs legth of precodig respose, ad PMA traiig IEEE P82.3a Task Force Austi, May 18-2, 25 Gottfried Ugerboeck 1 Cotets Study of trasmit frot-ed solutios Simple : o digital filterig,

More information

HDL LIBRARY OF PROCESSING UNITS FOR GENERIC AND DVB-S2 LDPC DECODING

HDL LIBRARY OF PROCESSING UNITS FOR GENERIC AND DVB-S2 LDPC DECODING HDL LIBRARY OF PROCESSING UNITS FOR GENERIC AND DVB-S2 LDPC DECODING Marco Gomes 1,2, Gabriel Falcão 1,2, João Goçalves 1,2, Vitor Silva 1,2, Miguel Falcão 3, Pedro Faia 2 1 Istitute of Telecommuicatios,

More information

Pipelined Architecture (2A) Young Won Lim 4/7/18

Pipelined Architecture (2A) Young Won Lim 4/7/18 Pipelined Architecture (2A) Copyright (c) 2014-2018 Young W. Lim. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2

More information

Pipelined Architecture (2A) Young Won Lim 4/10/18

Pipelined Architecture (2A) Young Won Lim 4/10/18 Pipelined Architecture (2A) Copyright (c) 2014-2018 Young W. Lim. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2

More information

PRACTICAL FILTER DESIGN & IMPLEMENTATION LAB

PRACTICAL FILTER DESIGN & IMPLEMENTATION LAB 1 of 7 PRACTICAL FILTER DESIGN & IMPLEMENTATION LAB BEFORE YOU BEGIN PREREQUISITE LABS Itroductio to Oscilloscope Itroductio to Arbitrary/Fuctio Geerator EXPECTED KNOWLEDGE Uderstadig of LTI systems. Laplace

More information

Combinational Circuits DC-IV (Part I) Notes

Combinational Circuits DC-IV (Part I) Notes Combinational Circuits DC-IV (Part I) Notes Digital Circuits have been classified as: (a) Combinational Circuits: In these circuits output at any instant of time depends on inputs present at that instant

More information

PROJECT #2 GENERIC ROBOT SIMULATOR

PROJECT #2 GENERIC ROBOT SIMULATOR Uiversity of Missouri-Columbia Departmet of Electrical ad Computer Egieerig ECE 7330 Itroductio to Mechatroics ad Robotic Visio Fall, 2010 PROJECT #2 GENERIC ROBOT SIMULATOR Luis Alberto Rivera Estrada

More information

HB860H 2-phase Hybrid Servo Drive

HB860H 2-phase Hybrid Servo Drive HB860H 2-phase Hybrid Servo Drive 20-70VAC or 30-100VDC, 8.2A Peak No Tuig, Nulls loss of Sychroizatio Closed-loop, elimiates loss of sychroizatio Broader operatig rage higher torque ad higher speed Reduced

More information

AME50461 SERIES EMI FILTER HYBRID-HIGH RELIABILITY

AME50461 SERIES EMI FILTER HYBRID-HIGH RELIABILITY PD-94595A AME5046 SERIES EMI FILTER HYBRID-HIGH RELIABILITY Descriptio The AME Series of EMI filters have bee desiged to provide full compliace with the iput lie reflected ripple curret requiremet specified

More information

Reducing Power Dissipation in Complex Digital Filters by using the Quadratic Residue Number System Λ

Reducing Power Dissipation in Complex Digital Filters by using the Quadratic Residue Number System Λ Reducig Power Dissipatio i Complex Digital Filters by usig the Quadratic Residue Number System Λ Agelo D Amora, Alberto Naarelli, Marco Re ad Gia Carlo Cardarilli Departmet of Electrical Egieerig Uiversity

More information

Datapath Components. Multipliers, Counters, Timers, Register Files

Datapath Components. Multipliers, Counters, Timers, Register Files Datapath Components Multipliers, Counters, Timers, Register Files Multipliers An N x N multiplier Multiplies two N bit binary inputs Generates an NN bit result Creating a multiplier using two-level logic

More information

Experiment # 4. Binary Addition & Subtraction. Eng. Waleed Y. Mousa

Experiment # 4. Binary Addition & Subtraction. Eng. Waleed Y. Mousa Experiment # 4 Binary Addition & Subtraction Eng. Waleed Y. Mousa 1. Objectives: 1. To study adder and subtractor circuits using logic gates. 2. To construct and test various adders and subtractor circuits.

More information

DIGITALLY TUNED SINUSOIDAL OSCILLATOR USING MULTIPLE- OUTPUT CURRENT OPERATIONAL AMPLIFIER FOR APPLICATIONS IN HIGH STABLE ACOUSTICAL GENERATORS

DIGITALLY TUNED SINUSOIDAL OSCILLATOR USING MULTIPLE- OUTPUT CURRENT OPERATIONAL AMPLIFIER FOR APPLICATIONS IN HIGH STABLE ACOUSTICAL GENERATORS Molecular ad Quatum Acoustics vol. 7, (6) 95 DGTALL TUNED SNUSODAL OSCLLATOR USNG MULTPLE- OUTPUT CURRENT OPERATONAL AMPLFER FOR APPLCATONS N HGH STABLE ACOUSTCAL GENERATORS Lesław TOPÓR-KAMŃSK Faculty

More information

CS 61C: Great Ideas in Computer Architecture Finite State Machines, Functional Units

CS 61C: Great Ideas in Computer Architecture Finite State Machines, Functional Units CS 61C: Great Ideas in Computer Architecture Finite State Machines, Functional Units Instructors: Vladimir Stojanovic and Nicholas Weaver http://inst.eecs.berkeley.edu/~cs61c/sp16 1 Machine Interpretation

More information

Encode Decode Sample Quantize [ ] [ ]

Encode Decode Sample Quantize [ ] [ ] Referece Audio Sigal Processig I Shyh-Kag Jeg Departmet of Electrical Egieerig/ Graduate Istitute of Commuicatio Egieerig M. Bosi ad R. E. Goldberg, Itroductio to Digital Audio Codig ad Stadards, Kluwer

More information

Computer Architecture and Organization:

Computer Architecture and Organization: Computer Architecture and Organization: L03: Register transfer and System Bus By: A. H. Abdul Hafez Abdul.hafez@hku.edu.tr, ah.abdulhafez@gmail.com 1 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU Outlines

More information

AkinwaJe, A.T., IbharaJu, F.T. and Arogundade, 0.1'. Department of Computer Sciences University of Agriculture, Abeokuta, Nigeria

AkinwaJe, A.T., IbharaJu, F.T. and Arogundade, 0.1'. Department of Computer Sciences University of Agriculture, Abeokuta, Nigeria COMPARATIVE ANALYSIS OF ARTIFICIAL NEURAL NETWORK'S BACK PROPAGATION ALGORITHM TO STATISTICAL LEAST SQURE METHOD IN SECURITY PREDICTION USING NIGERIAN STOCK EXCHANGE MARKET AkiwaJe, A.T., IbharaJu, F.T.

More information

Combinational Logic Circuits. Combinational Logic

Combinational Logic Circuits. Combinational Logic Combinational Logic Circuits The outputs of Combinational Logic Circuits are only determined by the logical function of their current input state, logic 0 or logic 1, at any given instant in time. The

More information

AME28461 SERIES EMI FILTER HYBRID-HIGH RELIABILITY

AME28461 SERIES EMI FILTER HYBRID-HIGH RELIABILITY PD-94597A AME28461 SERIES EMI FILTER HYBRID-HIGH RELIABILITY Descriptio The AME Series of EMI filters have bee desiged to provide full compliace with the iput lie reflected ripple curret requiremet specified

More information

Computer Architecture and Organization: L08: Design Control Lines

Computer Architecture and Organization: L08: Design Control Lines Computer Architecture and Organization: L08: Design Control Lines By: A. H. Abdul Hafez Abdul.hafez@hku.edu.tr, ah.abdulhafez@gmail.com, hafez@research.iiit.ac.in 1 CAO, by Dr. A.H. Abdul Hafez, CE Dept.

More information

High Speed Area Efficient Modulo 2 1

High Speed Area Efficient Modulo 2 1 High Speed Area Efficiet Modulo 2 1 1-Soali Sigh (PG Scholar VLSI, RKDF Ist Bhopal M.P) 2- Mr. Maish Trivedi (HOD EC Departmet, RKDF Ist Bhopal M.P) Adder Abstract Modular adder is oe of the key compoets

More information

Model Display digit Size Output Power supply 24VAC 50/60Hz, 24-48VDC 9999 (4-digit) 1-stage setting

Model Display digit Size Output Power supply 24VAC 50/60Hz, 24-48VDC 9999 (4-digit) 1-stage setting FXY Series DIN W7 6mm Of er/timer With Idicatio Oly Features ig speed: cps/cps/kcps/kcps Selectable voltage iput (PNP) method or o-voltage iput (NPN) method Iput mode: Up, Dow, Dow Dot for Decimal Poit

More information

Binary Adder and Subtractor circuit

Binary Adder and Subtractor circuit Digital circuit Experiment manual Experiment 9 inary dder and Subtractor circuit Part list. x. x. 8 x. x. 8 x Theory inary number addition n adder is a digital circuit that performs addition of numbers.

More information

EECS150 - Digital Design Lecture 23 - Arithmetic and Logic Circuits Part 4. Outline

EECS150 - Digital Design Lecture 23 - Arithmetic and Logic Circuits Part 4. Outline EECS150 - Digital Design Lecture 23 - Arithmetic and Logic Circuits Part 4 April 19, 2005 John Wawrzynek Spring 2005 EECS150 - Lec23-alc4 Page 1 Outline Shifters / Rotators Fixed shift amount Variable

More information

A New Design of Log-Periodic Dipole Array (LPDA) Antenna

A New Design of Log-Periodic Dipole Array (LPDA) Antenna Joural of Commuicatio Egieerig, Vol., No., Ja.-Jue 0 67 A New Desig of Log-Periodic Dipole Array (LPDA) Atea Javad Ghalibafa, Seyed Mohammad Hashemi, ad Seyed Hassa Sedighy Departmet of Electrical Egieerig,

More information

OPTIMIZATION OF RNS FIR FILTERS FOR 6-INPUTS LUT BASED FPGAS

OPTIMIZATION OF RNS FIR FILTERS FOR 6-INPUTS LUT BASED FPGAS OPTIMIZATION OF RNS FIR FILTERS FOR 6-INPUTS LUT BASED FPGAS G.C. Cardarilli, M. Re, A. Salsao Uiversity of Rome Tor Vergata Departmet of Electroic Egieerig Via del Politecico 1 / 00133 / Rome / ITAL {marco.re,

More information

After completing this chapter you will learn

After completing this chapter you will learn CHAPTER 7 Trasistor Amplifiers Microelectroic Circuits, Seeth Editio Sedra/Smith Copyright 015 by Oxford Uiersity Press After completig this chapter you will lear 1. How to use MOSFET as amplifier. How

More information

Combined Scheme for Fast PN Code Acquisition

Combined Scheme for Fast PN Code Acquisition 13 th Iteratioal Coferece o AEROSPACE SCIENCES & AVIATION TECHNOLOGY, ASAT- 13, May 6 8, 009, E-Mail: asat@mtc.edu.eg Military Techical College, Kobry Elkobbah, Cairo, Egypt Tel : +(0) 4059 4036138, Fax:

More information

Experiment # 3 Combinational Circuits (I) Binary Addition and Subtraction

Experiment # 3 Combinational Circuits (I) Binary Addition and Subtraction Experiment # 3 Combinational Circuits (I) Binary Addition and Subtraction Objectives: 1. To study adder and subtractor circuits using logic gates. 2. To construct and test various adders and subtractor

More information

Design and Implementation of Vedic Algorithm using Reversible Logic Gates

Design and Implementation of Vedic Algorithm using Reversible Logic Gates www.ijecs.i Iteratioal Joural Of Egieerig Ad Computer Sciece ISSN: 2319-7242 Volume 4 Issue 8 Aug 2015, Page No. 13734-13738 Desig ad Implemetatio of Vedic Algorithm usig Reversible Logic s Hemagi P.Patil

More information

(2) The MOSFET. Review of. Learning Outcome. (Metal-Oxide-Semiconductor Field Effect Transistor) 2.0) Field Effect Transistor (FET)

(2) The MOSFET. Review of. Learning Outcome. (Metal-Oxide-Semiconductor Field Effect Transistor) 2.0) Field Effect Transistor (FET) EEEB73 Electroics Aalysis & esig II () Review of The MOSFET (Metal-Oxide-Semicoductor Field Effect Trasistor) Referece: Neame, Chapter 3 ad Chapter 4 Learig Outcome Able to describe ad use the followig:

More information

Output. Function f. Characteristic Predictor. Predicted Output Characteristic. Checker. Output. Error

Output. Function f. Characteristic Predictor. Predicted Output Characteristic. Checker. Output. Error WHICH CONCURRENT ERROR DETECTION SCHEME TO CHOOSE? Subhasish Mitra ad Edward J. McCluskey Ceter for Reliable Computig Departmets of Electrical Egieerig ad Computer Sciece Staford Uiversity, Staford, Califoria

More information

信號與系統 Signals and Systems

信號與系統 Signals and Systems Sprig 2 信號與系統 Sigals ad Systems Chapter SS- Sigals ad Systems Feg-Li Lia NTU-EE Feb Ju Figures ad images used i these lecture otes are adopted from Sigals & Systems by Ala V. Oppeheim ad Ala S. Willsky,

More information

Outline. Motivation. Analog Functional Testing in Mixed-Signal Systems. Motivation and Background. Built-In Self-Test Architecture

Outline. Motivation. Analog Functional Testing in Mixed-Signal Systems. Motivation and Background. Built-In Self-Test Architecture Aalog Fuctioal Testig i Mixed-Sigal s Jie Qi Dept. of Electrical & Computer Egieerig Aubur Uiversity Co-Advisors: Charles Stroud ad Foster Dai Outlie Motivatio ad Backgroud Built-I Self-Test Architecture

More information

LIST OF EXPERIMENTS. KCTCET/ /Odd/3rd/ETE/CSE/LM

LIST OF EXPERIMENTS. KCTCET/ /Odd/3rd/ETE/CSE/LM LIST OF EXPERIMENTS. Study of logic gates. 2. Design and implementation of adders and subtractors using logic gates. 3. Design and implementation of code converters using logic gates. 4. Design and implementation

More information

ELEN 624 Signal Integrity

ELEN 624 Signal Integrity ELEN 624 Sigal Itegrity Lecture 8 Istructor: Ji hao 408-580-7043, jzhao@ieee.org ELEN 624, Fall 2006 W8, 11/06/2006-1 Ageda Homework review S parameter calculatio From time domai ad frequecy domai Some

More information

(CSC-3501) Lecture 6 (31 Jan 2008) Seung-Jong Park (Jay) CSC S.J. Park. Announcement

(CSC-3501) Lecture 6 (31 Jan 2008) Seung-Jong Park (Jay)   CSC S.J. Park. Announcement Seung-Jong Park (Jay) http://www.csc.lsu.edu/~sjpark Computer Architecture (CSC-3501) Lecture 6 (31 Jan 2008) 1 Announcement 2 1 Reminder A logic circuit is composed of: Inputs Outputs Functional specification

More information

信號與系統 Signals and Systems

信號與系統 Signals and Systems Sprig 24 信號與系統 Sigals ad Systems Chapter SS- Sigals ad Systems Feg-Li Lia NTU-EE Feb4 Ju4 Figures ad images used i these lecture otes are adopted from Sigals & Systems by Ala V. Oppeheim ad Ala S. Willsky,

More information

Subtractor Logic Schematic

Subtractor Logic Schematic Function Of Xor Gate In Parallel Adder Subtractor Logic Schematic metic functions, including half adder, half subtractor, full adder, independent logic gates to form desired circuits based on dif- by integrating

More information

Application of Improved Genetic Algorithm to Two-side Assembly Line Balancing

Application of Improved Genetic Algorithm to Two-side Assembly Line Balancing 206 3 rd Iteratioal Coferece o Mechaical, Idustrial, ad Maufacturig Egieerig (MIME 206) ISBN: 978--60595-33-7 Applicatio of Improved Geetic Algorithm to Two-side Assembly Lie Balacig Ximi Zhag, Qia Wag,

More information

FUNCTIONAL BLOCK DIAGRAM DV CC V DD V SS AGND DGND LDAC X2A REGISTER X2B REGISTER A/B MUX MUX X2A REGISTER X2B REGISTER A/B MUX MUX

FUNCTIONAL BLOCK DIAGRAM DV CC V DD V SS AGND DGND LDAC X2A REGISTER X2B REGISTER A/B MUX MUX X2A REGISTER X2B REGISTER A/B MUX MUX 16-Chael, 16-/14-Bit, Serial Iput, Voltage-Output DAC AD5360/AD5361 FEATURES 16-chael DAC i 52-lead LQFP ad 56-lead LFCSP packages Guarateed mootoic to 16/14 bits Nomial output voltage rage of 10 V to

More information

ELEC 350 Electronics I Fall 2014

ELEC 350 Electronics I Fall 2014 ELEC 350 Electroics I Fall 04 Fial Exam Geeral Iformatio Rough breakdow of topic coverage: 0-5% JT fudametals ad regios of operatio 0-40% MOSFET fudametals biasig ad small-sigal modelig 0-5% iodes (p-juctio

More information

Measurement of Equivalent Input Distortion AN 20

Measurement of Equivalent Input Distortion AN 20 Measuremet of Equivalet Iput Distortio AN 2 Applicatio Note to the R&D SYSTEM Traditioal measuremets of harmoic distortio performed o loudspeakers reveal ot oly the symptoms of the oliearities but also

More information

Test Time Minimization for Hybrid BIST with Test Pattern Broadcasting

Test Time Minimization for Hybrid BIST with Test Pattern Broadcasting Test Time Miimizatio for Hybrid BIST with Test Patter Broadcastig Raimud Ubar, Maksim Jeihhi Departmet of Computer Egieerig Talli Techical Uiversity EE-126 18 Talli, Estoia {raiub, maksim}@pld.ttu.ee Gert

More information

Spread Spectrum Signal for Digital Communications

Spread Spectrum Signal for Digital Communications Wireless Iformatio Trasmissio System Lab. Spread Spectrum Sigal for Digital Commuicatios Istitute of Commuicatios Egieerig Natioal Su Yat-se Uiversity Spread Spectrum Commuicatios Defiitio: The trasmitted

More information

DELD MODEL ANSWER DEC 2018

DELD MODEL ANSWER DEC 2018 2018 DELD MODEL ANSWER DEC 2018 Q 1. a ) How will you implement Full adder using half-adder? Explain the circuit diagram. [6] An adder is a digital logic circuit in electronics that implements addition

More information

4. INTERSYMBOL INTERFERENCE

4. INTERSYMBOL INTERFERENCE DATA COMMUNICATIONS 59 4. INTERSYMBOL INTERFERENCE 4.1 OBJECT The effects of restricted badwidth i basebad data trasmissio will be studied. Measuremets relative to itersymbol iterferece, usig the eye patter

More information

MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI

MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI 6 DEPARTMENT: ECE QUESTION BANK SUBJECT NAME: DIGITAL SYSTEM DESIGN SEMESTER III SUBJECT CODE: EC UNIT : Design of Combinational Circuits PART -A ( Marks).

More information

Mapping Multiplexers onto Hard Multipliers in FPGAs

Mapping Multiplexers onto Hard Multipliers in FPGAs Mapping Multiplexers onto Hard Multipliers in FPGAs Peter Jamieson and Jonathan Rose The Edward S. Rogers Sr. Department of Electrical and Computer Engineering University of Toronto Modern FPGAs Consist

More information

3. Error Correcting Codes

3. Error Correcting Codes 3. Error Correctig Codes Refereces V. Bhargava, Forward Error Correctio Schemes for Digital Commuicatios, IEEE Commuicatios Magazie, Vol 21 No1 11 19, Jauary 1983 Mischa Schwartz, Iformatio Trasmissio

More information

FUNCTIONAL BLOCK DIAGRAM DV CC V DD V SS AGND DGND LDAC 14 REGISTER X2A REGISTER A/B MUX MUX X2B REGISTER X2A REGISTER A/B MUX MUX X2B REGISTER

FUNCTIONAL BLOCK DIAGRAM DV CC V DD V SS AGND DGND LDAC 14 REGISTER X2A REGISTER A/B MUX MUX X2B REGISTER X2A REGISTER A/B MUX MUX X2B REGISTER 8-Chael, 16-/14-Bit, Serial Iput, Voltage Output DAC AD5362/AD5363 FEATURES 8-chael DAC i 52-lead LQFP ad 56-lead LFCSP packages Guarateed mootoic to 16/14 bits Nomial output voltage rage of 10 V to +10

More information

Survey of Low Power Techniques for ROMs

Survey of Low Power Techniques for ROMs Survey of Low Power Techiques for ROMs Edwi de Agel Crystal Semicoductor Corporatio P.O Box 17847 Austi, TX 78744 Earl E. Swartzlader, Jr. Departmet of Electrical ad Computer Egieerig Uiversity of Texas

More information

A study on the efficient compression algorithm of the voice/data integrated multiplexer

A study on the efficient compression algorithm of the voice/data integrated multiplexer A study o the efficiet compressio algorithm of the voice/data itegrated multiplexer Gyou-Yo CHO' ad Dog-Ho CHO' * Dept. of Computer Egieerig. KyiigHee Uiv. Kiheugup Yogiku Kyuggido, KOREA 449-71 PHONE

More information

A New Space-Repetition Code Based on One Bit Feedback Compared to Alamouti Space-Time Code

A New Space-Repetition Code Based on One Bit Feedback Compared to Alamouti Space-Time Code Proceedigs of the 4th WSEAS It. Coferece o Electromagetics, Wireless ad Optical Commuicatios, Veice, Italy, November 0-, 006 107 A New Space-Repetitio Code Based o Oe Bit Feedback Compared to Alamouti

More information

Features. +Vout. +Vin. AHF28XX/CH (or Other) DC/DC Converter. Input Return. +Vout AHF28XX/CH (or Other) DC/DC Converter Output Return.

Features. +Vout. +Vin. AHF28XX/CH (or Other) DC/DC Converter. Input Return. +Vout AHF28XX/CH (or Other) DC/DC Converter Output Return. PD-94587A AMH461 SERIES EMI FILTER HYBRID / HIGH RELIABILITY Descriptio The AMH Series EMI filter has bee desiged to provide full compliace with the iput lie reflected ripple curret requiremet specified

More information

Design of Area and Speed Efficient Modulo 2 n -1 Multiplier for Cryptographic Applications

Design of Area and Speed Efficient Modulo 2 n -1 Multiplier for Cryptographic Applications Iteratioal Joural of Sciece, Egieerig ad Techology Research (IJSETR) Desig of Area ad Speed Efficiet Modulo 2-1 Multiplier for Cryptographic Applicatios Abstract The ecryptio ad decryptio of PKC algorithms

More information

Electronics. Digital Electronics

Electronics. Digital Electronics Electronics Digital Electronics Introduction Unlike a linear, or analogue circuit which contains signals that are constantly changing from one value to another, such as amplitude or frequency, digital

More information

Counting on r-fibonacci Numbers

Counting on r-fibonacci Numbers Claremot Colleges Scholarship @ Claremot All HMC Faculty Publicatios ad Research HMC Faculty Scholarship 5-1-2015 Coutig o r-fiboacci Numbers Arthur Bejami Harvey Mudd College Curtis Heberle Harvey Mudd

More information

DESIGN AND IMPLEMENTATION OF AREA EFFICIENT, LOW-POWER AND HIGH SPEED 128-BIT REGULAR SQUARE ROOT CARRY SELECT ADDER

DESIGN AND IMPLEMENTATION OF AREA EFFICIENT, LOW-POWER AND HIGH SPEED 128-BIT REGULAR SQUARE ROOT CARRY SELECT ADDER DESIGN AND IMPLEMENTATION OF AREA EFFICIENT, LOW-POWER AND HIGH SPEED 128-BIT REGULAR SQUARE ROOT CARRY SELECT ADDER MURALIDHARAN.R [1],AVINASH.P.S.K [2],MURALI KRISHNA.K [3],POOJITH.K.C [4], ELECTRONICS

More information

Multisensor transducer based on a parallel fiber optic digital-to-analog converter

Multisensor transducer based on a parallel fiber optic digital-to-analog converter V Iteratioal Forum for Youg cietists "pace Egieerig" Multisesor trasducer based o a parallel fiber optic digital-to-aalog coverter Vladimir Grechishikov 1, Olga Teryaeva 1,*, ad Vyacheslav Aiev 1 1 amara

More information

Features. +Vout. +Vin. +Vout AMF28XX (or Other) DC/DC Converter Input Return. Output Return. +Vout AMF28XX (or Other) DC/DC Converter Input Return

Features. +Vout. +Vin. +Vout AMF28XX (or Other) DC/DC Converter Input Return. Output Return. +Vout AMF28XX (or Other) DC/DC Converter Input Return PD-5856A AFH461 SERIES EMI FILTER HYBRID / HIGH RELIABILITY Descriptio The AFH Series EMI filter has bee desiged to provide full compliace with the iput lie reflected ripple curret requiremet specified

More information

The Simeck Family of Lightweight Block Ciphers

The Simeck Family of Lightweight Block Ciphers The Simeck Family of Lightweight Block Ciphers Gagqiag Yag, Bo Zhu, Valeti Suder, Mark D. Aagaard, ad Guag Gog Departmet of Electrical ad Computer Egieerig, Uiversity of Waterloo Waterloo, Otario, N2L

More information

LOGIC DIAGRAM: HALF ADDER TRUTH TABLE: A B CARRY SUM. 2012/ODD/III/ECE/DE/LM Page No. 1

LOGIC DIAGRAM: HALF ADDER TRUTH TABLE: A B CARRY SUM. 2012/ODD/III/ECE/DE/LM Page No. 1 LOGIC DIAGRAM: HALF ADDER TRUTH TABLE: A B CARRY SUM K-Map for SUM: K-Map for CARRY: SUM = A B + AB CARRY = AB 22/ODD/III/ECE/DE/LM Page No. EXPT NO: DATE : DESIGN OF ADDER AND SUBTRACTOR AIM: To design

More information

Slides copyright 1996, 2001, 2005, 2009 by Roger S. Pressman. For non-profit educational use only

Slides copyright 1996, 2001, 2005, 2009 by Roger S. Pressman. For non-profit educational use only Chapter 7 Requiremets Modelig: Flow, Behavior, Patters, ad WebApps Slide Set to accompay Software Egieerig: A Practitioer s Approach, 7/e by Roger S. Pressma Slides copyright 1996, 2001, 2005, 2009 by

More information

3GPP TS V8.0.0 ( )

3GPP TS V8.0.0 ( ) TS 25.213 V8.0.0 (2008-03) Techical Specificatio 3rd Geeratio Partership Project; Techical Specificatio Group Radio Access Network; Spreadig ad modulatio (FDD) (Release 8) The preset documet has bee developed

More information

Unit level 4 Credit value 15. Introduction. Learning Outcomes

Unit level 4 Credit value 15. Introduction. Learning Outcomes Unit 20: Unit code Digital Principles T/615/1494 Unit level 4 Credit value 15 Introduction While the broad field of electronics covers many aspects, it is digital electronics which now has the greatest

More information

CHAPTER 6 IMPLEMENTATION OF DIGITAL FIR FILTER

CHAPTER 6 IMPLEMENTATION OF DIGITAL FIR FILTER CHAPTER 6 IMPLEMENTATION OF DIGITAL FIR FILTER 6.1 INTRODUCTION The digital FIR filters are commo compoets i may digital sigal processig (DSP) systems. There are various applicatios like high speed/low

More information

Single Bit DACs in a Nutshell. Part I DAC Basics

Single Bit DACs in a Nutshell. Part I DAC Basics Sigle Bit DACs i a Nutshell Part I DAC Basics By Dave Va Ess, Pricipal Applicatio Egieer, Cypress Semicoductor May embedded applicatios require geeratig aalog outputs uder digital cotrol. It may be a DC

More information

PV210. Solar PV tester and I-V curve tracer

PV210. Solar PV tester and I-V curve tracer PV210 Solar PV tester ad I-V curve tracer The PV210 provides a highly efficiet ad effective test ad diagostic solutio for PV systems, carryig out all commissioig tests required by IEC 62446 ad performig

More information

MEASUREMENT AND CONTORL OF TOTAL HARMONIC DISTORTION IN FREQUENCY RANGE 0,02-10KHZ.

MEASUREMENT AND CONTORL OF TOTAL HARMONIC DISTORTION IN FREQUENCY RANGE 0,02-10KHZ. ELECTRONICS 00 September, Sozopol, BLGARIA MEASREMENT AND CONTORL OF TOTAL HARMONIC DISTORTION IN FREQENCY RANGE 0,0-0KHZ. Plame Agelov Agelov Faculty for Computer Sciece, Egieerig ad Natural Studies,

More information

32-Channel, 16-/14-Bit, Serial Input, Voltage Output DAC AD5372/AD5373

32-Channel, 16-/14-Bit, Serial Input, Voltage Output DAC AD5372/AD5373 32-Chael, 6-/4-Bit, Serial Iput, Voltage Output DAC AD5372/AD5373 FEATURES 32-chael DAC i a 64-lead LQFP AD5372/AD5373 guarateed mootoic to 6/4 bits Maximum output voltage spa of 4 VREF (20 V) Nomial output

More information

Department of Electrical and Computer Engineering, Cornell University. ECE 3150: Microelectronics. Spring Due on April 26, 2018 at 7:00 PM

Department of Electrical and Computer Engineering, Cornell University. ECE 3150: Microelectronics. Spring Due on April 26, 2018 at 7:00 PM Departmet of Electrical ad omputer Egieerig, orell Uiersity EE 350: Microelectroics Sprig 08 Homework 0 Due o April 6, 08 at 7:00 PM Suggested Readigs: a) Lecture otes Importat Notes: ) MAKE SURE THAT

More information

LOGIC GATES AND LOGIC CIRCUITS A logic gate is an elementary building block of a Digital Circuit. Most logic gates have two inputs and one output.

LOGIC GATES AND LOGIC CIRCUITS A logic gate is an elementary building block of a Digital Circuit. Most logic gates have two inputs and one output. LOGIC GATES AND LOGIC CIRCUITS A logic gate is an elementary building block of a Digital Circuit. Most logic gates have two inputs and one output. At any given moment, every terminal is in one of the two

More information

ECE 2201 PRELAB 4A MOSFET SWITCHING APPLICATIONS. Digital CMOS Logic Inverter

ECE 2201 PRELAB 4A MOSFET SWITCHING APPLICATIONS. Digital CMOS Logic Inverter ECE 2201 PRELAB 4A MOSFET SWITCHING APPLICATIONS Digital CMOS Logic Iverter Had Aalysis P1. I the circuit of Fig. P41, estimate the roagatio delays t PLH ad t PHL usig the resistive switch model for each

More information

NOISE IN A SPECTRUM ANALYZER. Carlo F.M. Carobbi and Fabio Ferrini Department of Information Engineering University of Florence, Italy

NOISE IN A SPECTRUM ANALYZER. Carlo F.M. Carobbi and Fabio Ferrini Department of Information Engineering University of Florence, Italy NOISE IN A SPECTRUM ANALYZER by Carlo.M. Carobbi ad abio errii Departet of Iforatio Egieerig Uiversity of lorece, Italy 1. OBJECTIVE The objective is to easure the oise figure of a spectru aalyzer with

More information

PV200. Solar PV tester and I-V curve tracer

PV200. Solar PV tester and I-V curve tracer PV200 Solar PV tester ad I-V curve tracer The PV200 provides a highly efficiet ad effective test ad diagostic solutio for PV systems, carryig out all commissioig tests required by IEC 62446 ad performig

More information

A New 3-Bit Integrating Time to Digital Converter Using Time to Voltage Conversion Technique

A New 3-Bit Integrating Time to Digital Converter Using Time to Voltage Conversion Technique Bulleti of Eviromet, Pharmacology ad Life Scieces Bull. Ev. Pharmacol. Life Sci., ol 3 [11] October 2014:115-122 2014 Academy for Eviromet ad Life Scieces, dia Olie SSN 2277-1808 Joural s URL:http://www.bepls.com

More information

EEE 301 Digital Electronics

EEE 301 Digital Electronics EEE 301 Digital Electronics Lecture 1 Course Contents Introduction to number systems and codes. Analysis and synthesis of digital logic circuits: Basic logic functions, Boolean algebra,combinational logic

More information

Some Modular Adders and Multipliers for Field Programmable Gate Arrays

Some Modular Adders and Multipliers for Field Programmable Gate Arrays Some Modular Adders ad Multipliers for Field Programmable Gate Arras Jea-Luc Beuchat Laboratoire de l Iformatique du Parallélisme (CNRS, ENSL, INRIA) 46, Allée d Italie F 69364 Lo Cede 7 Jea-Luc.Beuchat@es-lo.fr

More information

COMPRESSION OF TRANSMULTIPLEXED ACOUSTIC SIGNALS

COMPRESSION OF TRANSMULTIPLEXED ACOUSTIC SIGNALS COMPRESSION OF TRANSMULTIPLEXED ACOUSTIC SIGNALS Mariusz Ziółko, Przemysław Sypka ad Bartosz Ziółko Departmet of Electroics, AGH Uiversity of Sciece ad Techology, al. Mickiewicza 3, 3-59 Kraków, Polad,

More information

Improved IDEA. The IDEA 1 (International Data Encryption Algorithm) algorithm. 1 The IDEA cryptographic algorithm is patented in Europe and in the

Improved IDEA. The IDEA 1 (International Data Encryption Algorithm) algorithm. 1 The IDEA cryptographic algorithm is patented in Europe and in the Improved IDEA Sérgio L. C. Salomão salomao@lpc.ufrj.br Vladimir C. Alves castro@lpc.ufrj.br João M. S. de Alcâtara jmarcelo@lpc.ufrj.br Felipe M. G. Fraca felipe@lpc.ufrj.br Military Istitute of Egieerig

More information

Open Two Radio Switching Protocol (OTRSP)

Open Two Radio Switching Protocol (OTRSP) Ope Two Radio Switchig Protocol (OTRSP) Copyright 2009, 2019 Paul Youg. This work is licesed uder the Creative Commos Attributio 3.0 Licese. To view a copy of this licese, visit www.creativecommos.org

More information