AltiumLive 2017: 8 NEW DESIGN FEATURES OF HIGH DENSITY PWBS

Transcription

1 AltiumLive 2017: 8 NEW DESIGN FEATURES OF HIGH DENSITY PWBS Happy Holden PCB Technologist San Diego, October 4 th 2017

2 Agenda What HDI Design Features Gain The Most 1 Where to place the blind vias 2 3 BGA breakouts Reduction of the big TH drilled vias Ease into HDI-Higher wiring density with VeCS Horz-Vert microvia routing pairs Finer traces/spaces & vias/pads BC and decoupling capacitor removal Split PWR plane supply with blind-vias

3 1-Where To Place The Microvias?

4 HDI Routing with Blind Vias 2 techniques: Perimeter and Channel Perimeter Channel Perimeter uses bands of blind vias around the perimeter. Works best on small BGAs and low I/O. Channel uses rows of blind vias working inwards to create I/L channels for routing. Works best on large BGAs and high I/O.

5 HDI BGA Routing - Basics (Near) Via in pad techniques µvias many times should have multiple angles, in order to maximize the routing channels on the layer below and how it might be connected to buried vias. A B C New larger channel for breakout Inset nvip Partial vip Offset-center vip

6 Swing TH Via Placement SMT Land TH Via Pad: 0.2 mm FHS 0.35mm 0.40mm 0.45mm SMT Land TH Via Pad: 0.2 mm FHS 0.35mm 0.40mm 0.45mm TH Via Pad: 0.2 mm FHS 0.35mm 0.40mm 0.45mm SMT Land 0.30mm 0.40mm 0.50mm 0.25mm 0.35mm 0.45mm 0.22mm 0.30mm 0.40mm FINE PITCH: 0.65mm 0.80mm

7 Swing Blind Via Placement SMT Land: Blind Via Pad: 0.25mm SMT Land: BV: 0.15 mm SMT Land: 0.50mm 0.50mm 0.50mm 0.45mm 0.45mm 0.45mm 0.40mm 0.40mm 0.40mm FINE PITCH: 0.65mm 0.80mm 1.0mm

8 HDI MicroVia Structures (NVIP) Near via-in-pad allows plane fill but without the assembly via fill need

9 Blind Via Placement for Fine-Pitch Reassigned pattern FINE PITCH: Copyright 2007 Mentor Graphics

10 BGA uvia Routing Fine Pitch

11 2-HDI Boulevard Routing for BGA Breakout

12 Fanout Patterns Blind & Buried-Vias Multiple Fanout Patterns Using a number of different patterns works well in this context A - Swing Columns & Rows -blind vias (1-2) B - Swing Columns & Rows -skip vias (1-3) C - Transition BV Dog-Bone (1-2) D - Quadrant TH Dog-Bone (1-N) D B C Diagonal A

13 SWING VIAS Ld Vd S S θ P θ New BGA Breakout w/ground Pour 1517 pin 0.8 mm pitch SMT Pitch-P (mm) Land dia- Ld (mm) Via dia- Vd (mm) Via Angle-θ Via Angle-θ X X X X X X X X X X X X X X X X X WHERE: S=>0.102 mm

14 Simple Trigonometric Spreadsheet

15 SWING VIAS VERTEX pins More details on BGA Breakout & Routing in Charle s new book, see last page

16 SWING VIAS More Options

17 Increasing Component Complexity Xilinx Vertex Pin Pkg Breakout L3-Signal Rocket IO

18 Xilinx Vertex Pin Pkg Breakout 2 Signal Layers plus Ref Planes 13 traces between buried vias L5-Signal Diff Pair IO

19 Top view The conventional TH breakout adds 6 more signal layers and 4 reference planes!! 7 traces between blind vias, 15 between buried vias

20 Providing Boulevards GND/SMT X-routing Y-routing PWRs GND

21 Providing Boulevards Top view The conventional TH breakout adds 6 more signal layers and 4 reference planes!! 15 traces between buried vias

22 Key is Blind Via Placement Alternate blind vias from 1-2 w/ buried vias from 2-11 Alternate blind vias from 1-3

23 Top view The conventional TH breakout adds 6 more signal layers and 4 reference planes!! 2 traces through-vias

24 No Boulevards

25 Fancy View

26 Hands-on Hdi Workshop Test Vehicle-example

27 Reference Book BGA Breakouts & Routings-Effective Design Methods for Very Large BGAs by Pfeil, Charles, 177 ppg, May 2008, Mentor Graphics Amazon-$12.50 OR FREE AT d_routing.pdf th=/pcb/techpubs/requestpubs&id=52590

28 3-Eliminating the BIG drilled vias (TH or buried) Routing w/microvias

29 Example HDI Stackup Using the blind microvia and the skip microvia to replace the larger drilled THs and buried vias Blind skip micro-via 1 3

30 What s New Using HDI from Through-Holes? Use of Microvias in Place of Through-Holes Layer Stackup Changes to Eliminate Drilled Holes Using the Blind Vias to Form Channels Placing the Blind Vias to Open Up Boulevards

31 Surface 3 Layers TYPE I SMT/GND PWR SIG SMT/SIG GND SIG/PWR SMT/GND SIG SIG SMT/GND SIG PWR TYPE II SMT/GND PWR SIG SMT/GND SIG PWR/GND SMT/SIG SIG/GND SIG/PWR/GND TYPE III SMT/GND PWR SIG SMT/SIG SIG PWR/GND SMT/SIG SIG PWR/GND SMT/GND SIG PWR/GND

32 Moving PWRs Closer to the Surface 1.7 to 2.8 mil prepreg with the 3.0 mil core or prepreg being the lowest cost/highest performance TYPE I TYPE II TYPE III SMT/GND PWR SIG SMT/GND PWR SIG SMT/GND PWR SIG

33 Distributed Capacitance Materials

34 4- HDI Using VeCS Technology

35 VeCS Vertical Conductive Structures A new technology for High-Density Interconnects Developed by Joan Torné Using the conventional PCB TH fab equipment, increased densities and routing are capable down to 0.4 mm pitch. Process hasn t changed, just a few additional steps: Drill or route a slot between BGA lands Metalize and plate as normal Image with VeCS breakouts At final fabrication, drill out the metallization for vertical traces Patent Pending

36 VeCS Schematic diagram of VeCS, sequentially laminated.

37 VeCS Board with daisy chain on 1.0 mm pitch using VeCS technology used for reliability testing of the interconnects. The fabrication and testing is done by WUS. Examples. After multiple lead-free reflow cycles and thermal cycling to failure-results comparable with through-hole

38 VeCS Cross-section of the interconnect with the innerlayer, after six solder shocks of 288C

39 VeCS INNERLAYERS 2-13 VeCS technology in Altium design system.

40 VeCS VeCS Fabrication Process Drill/Route: Metallize: Image: Plate: Strip/Etch: Final Fab:

41 VeCS VeCS Fabrication Process TH uvia

42 VeCS Routing 1.0 mm pitch 0.5 mm pitch No tracks TH 2 tracks µvia 7 tracks 7 tracks VeCS 7 tracks 5 tracks

43 5-Horz-Vert microvia routing pair

44 Providing High-Density Routing Pairs TYPE II-drill TYPE II-Mod SMT/GND SIG_H SIG_V Can pick up noise from other planes HDI via-cross-overs provide low inductance and freedom from noise TH s pick up on plane layers.

45 Telecom Router High-Density Routing Pairs Example For Telecom Board

46 6- Finer traces/spaces & via/pads

47 SMALLER for SPEED! Inner Layers (traces/spaces).004 /.004 to.003 /.004 to.003 /.003 to.002 /.003 Build-up Layer (via / lands).006 /.014 to.004 /.012 to.004 /.010 Drilled Holes (via / lands).012 /.024 to.010 /.020 to.008 /.018 Material Thickness.003 FR-4 PP to.001 RRCF to.0002 BC/R ceramic filled Since ICs are evolving, so must the PCB design rules - Pick a partner with a proven ROADMAP Example: ACPT s HDI orders have gone from 20% to 88% today

48 High Density Interconnects Evolutions Need to make Everything SMALLER! Figure 16, Chapter 4, HDI Handbook,pp180 Vias closer together (current loops) Blind vias to planes (current loops) Smaller via pads (smaller annular rings->to landless (direct-digital imaging)

49 Landless Smaller via pads (smaller annular rings->to landless This is a good question to ask a PCB Fab: Can you do or develop a landless via process? If the answer is, Not Possible, then maybe they are not your first choice as an HDI partner! If the answer is, We do not have that capability currently, but will see if we can implement that process. then they may be a worthy partner. The answer is, Landless vias have been used on PCBs since 1984 and there are four (4) ways to fabricate them. 1. Japanese way: liquid electrophoretic positive photoresist (see Candor ads) 2. H-P way: Reduce pads size to be smaller than FHS (no cost $) PCB Mag-June Russian way:no pad artwork-bake dryfilm photoresist for 5 min, then develop way: Using the new direct digital imaging with hole scanning for perfect registration. HDI technologies are NOT-the same old PCB processes!

50 Landless Landless TH technology Landless HDI technology in Japan-2002

51 7- Removal of Decoupling Capacitors

52 Moving PWRs Closer to the Surface Material could be 0.2 mil with 3M & Oak-Mitsui BC materials TYPE I TYPE II SMT/GND PWR SIG SMT/GND PWR SIG TYPE III SMT/GND PWR SIG

53 Distributed Capacitance Materials

54 Distributed Capacitance Impedance Comparison & 75 micron FR4 PP.

55 Power Integrity 25% fewer layers and 70% smaller 16-Layer TH 10.0 x 7.8 inches TO 12-Layer HDI 6.0 x 4.0 inch (using fine-pitch connectors and BGAs) Source: DesignCon 2009 PI Effects of HDI

56 Signal & Power Integrity 12L, 10 Layer and 8 layers HDI alternatives Source: DesignCon 2009 PI Effects of HDI

57 HANDS-ON HDI Training CRANE Stackup using HDI BC BR Hands-On Design /Fab Training at the CRANE NWS BR BC

58 PDN impedance for 3.3V Original design uF caps uF caps uF cap HDI design uF caps uF caps uF cap

59 PDN impedance for 2.5V Original design uF caps uF caps 1 10uF cap HDI design uF caps uF caps 1 10uF cap

60 8- Use of Split Planes & Power Mesh

61 Evolution of split power and ground planes

62 An evolution from Univ of AK s IMPS architecture Power Mesh is an offset coplanar stripline RF architecture

63 Power Mesh Signal / Power Layers Signal_Y/Power Mesh: Layer 2 12-L TH to 4-L Power Mesh Ground SMT: Layer 4 Signal_X/Power Mesh: Layer 3

64 First Power Mesh - HDI 1994 Thickness: 0.020" VIA / PAD DIA. (inch) TRACE / SPACE (inch) Outerlayers GND plane POUR Innerlayers / / 0.003

65 Other Power Mesh Examples 12L TH >4L 10L TH 2-sided SMT > 4L 1-sided SMT 12L TH >4L 10L TH >4L cross section

66 Thanks for your Attention! Questions?

67 Additional Reading HDI Handbook Other free e-books from I-Connect007 Download now the HDI HANDBOOK Free at: hdihandbook.com or in Mandarin at hdihandbook.cn

68 Strain Range (in./in.) Strain Range (in./in.) Landless Reliability Landless and small Annular Ring reliability Page 1307, Ch 60, Printed Circuits Handbook-7 th Ed. Chapter written by Reza Ghaffarian-JPL/NASA 0.6 Elastic 0.6 Elastic 0.5 Pad Tilt-FR-4 (D) Pad Tilt-FR-4 (P) 0.5 Cu plating ductility 30% 20% 10% 0.4 Pad Tilt-BT 0.4 Barrel FR-4 (D) Pad Annular Ring (mil) Cycles-to-Failure Cycle-to-failure