MC Low Voltage Rail-To-Rail Sleep Mode Operational Amplifier

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1 MC3334 Low Voltage Rail-To-Rail Sleep Mode Operational Amplifier The MC3334 is a monolithic bipolar operational amplifier. This low voltage rail to rail amplifier has both a rail to rail input and output stage, with high output current capability. In sleep mode, the micropower amplifier is active and waiting for an input signal. When a signal is applied, causing the amplifier to source or sink 2 A (typically) to the load, it will automatically switch to the awake mode (supplying up to 7 ma to the load). When the output current drops below 9 A, the amplifier automatically returns to the sleep mode. Excellent performance can be achieved as an audio amplifier. This is due to the amplifier s low noise and low distortion. A delay circuit is incorporated to prevent crossover distortion. Ideal for Battery Applications Full Output Signal (No Distortion) for Battery Applications Down to ±.9 VDC. Single Supply Operation (+1.8 to +12 V) Rail To Rail Performance on Both the Input and Output Output Voltages Swings Typically within mv of Both Rails (R L = 1. m ) Two States: Sleep Mode (Micropower, I D = 1 A/Amp) and Awake Mode (High Performance, I D = 12 A/Amp) Automatic Return to Sleep Mode when Output Current Drops Below Threshold, Allowing a Fully Functional Micropower Amplifier Independent Sleep Mode Function for Each Amplifier No Phase Reversal on the Output for Overdriven Input Signals High Output Current (7 ma typically) 6 Drive Capability Standard Pinouts; No Additional Pins or Components Required Drop In Replacement for Many Other Quad Operational Amplifiers Similar to MC3321, MC3322 and MC3324 Family The MC3334 Amplifier is Offered in the Plastic DIP or SOIC Package (P and D Suffixes) 14 1 SO14 D SUFFIX CASE 751A PDIP14 P SUFFIX CASE MARKING DIAGRAMS 14 MC3334P AWLYYWW A = Assembly Location WL = Wafer Lot YY, Y = Year WW = Work Week Output 1 Inputs 1 V CC 1 PIN CONNECTIONS Inputs Output (Quad, Top View) MC3334D AWLYWW Output 4 Inputs 4 V EE Inputs 3 Output 3 ORDERING INFORMATION Device Package Shipping MC3334D SO14 55 Units/Rail MC3334DR2 SO14 25 Tape & Reel MC3334P PDIP14 25 Units/Rail Semiconductor Components Industries, LLC, 211 August, 211 Rev. 3 1 Publication Order Number: MC3334/D

2 MC3334 TYPICAL DC ELECTRICAL CHARACTERISTICS () Characteristic V CC = 2. V V CC = 3.3 V V CC = 5. V Unit Input Offset Voltage V IO(max) MC3334 ± ± ± Output Voltage Swing V OH (R L = 6 ) V min V OL (R L = 6 ) V max Power Supply Current per Amplifier (I D ) ma A Specifications are for reference only and not necessarily guaranteed. V EE = GND. MAXIMUM RATINGS Rating Symbol Value Unit Supply Voltage (V CC to V EE ) V S +16 V ESD Protection Voltage at Any Pin Human Body Model V ESD 2 Voltage at Any Device Pin (Note 2) V DP V S ±.5 V Input Differential Voltage Range V IDR (Notes 1 and 2) V mv V Output Short Circuit Duration t s Indefinite (Note 3) sec Maximum Junction Temperature T J +15 C Storage Temperature Range T stg 65 to +15 C Maximum Power Dissipation P D (Note 5) mw RECOMMENDED OPERATING CONDITIONS Characteristic Symbol Min Typ Max Unit Supply Voltage V S V Single Supply Split Supplies ±.9 ±6. Input Voltage Range, and V ICR V EE V CC V Ambient Operating Temperature Range T A 4 +5 C 1. The differential input voltage of each amplifier is limited by two internal diodes. The diodes are connected across the inputs in parallel and opposite to each other. For more differential input voltage range, use current limiting resistors in series with the input pins. 2. The common mode input voltage range of each amplifier is limited by diodes connected from the inputs to both power supply rails. Therefore, the voltage on either input must not exceed supply rail by more than ±5 mv. 3. Simultaneous short circuits of two or more amplifiers to the positive or negative rail can exceed the power dissipation ratings and cause eventual failure of the device. 4. Railtorail performance is achieved at the input of the amplifier by using parallel NPN PNP differential stages. When the inputs are near the negative rail (V EE < V CM < 8 mv), the PNP stage is on. When the inputs are above 8 mv (i.e. 8 mv < V CM < V CC ), the NPN stage is on. This switching of the input pairs will cause a reversal of input bias current. Slight changes in the input offset voltage will be noted between the NPN and PNP pairs. Cross coupling techniques have been used to keep this change to a minimum. 5. Power dissipation must be considered to ensure maximum junction (T J ) is not exceeded. (See Figure 2) 6. When connected as a voltage follower and used in transient conditions, a current limiting resistor may be needed between the output and the inverting input. This is because of the back to back diodes clamped across the inputs. The value of this resistor should be between 1. k and k. If the amplifier does not become slew rate limited and is processing low frequency waveforms, then no resistor would be necessary. (The output could be tied directly to the negative input.) 2

3 MC3334 DC ELECTRICAL CHARACTERISTICS (V CC = +5. V, V EE = GND,, unless otherwise noted.) Characteristic Symbol Min Typ Max Unit Input Offset Voltage (V CM = V, V O = V) (Note 4) and T A = 4 to +5 C Average Temperature Coefficient of Input Offset Voltage (R S = 5, V CM = V, V O = V) T A = 4 to +5 C, and Input Bias Current (V CM = V, V O = V) (Note 4) T A = 4 to +5 C Input Offset Current (V CM = V, V O = V) (Note 4) T A = 4 to +5 C Large Signal Voltage Gain (V CC = +5. V, V EE = 5. V), R L = 6 T A = 4 to +5 C V IO V IO / T I IB I IO Power Supply Rejection Ratio, PSRR 65 9 db Output Short Circuit Current () (V ID = ±.2 V) Source Sink Output Transition Current, Source/Sink to, V CC = +1. V, V EE = 1. V to, V CC = +5. V, V EE 5. V Output Voltage Swing (V ID = ±.2 V) V CC = +5. V, V EE = V, R L = 1. M V CC = V, V EE = 5. V, R L = 1. M V CC = +2. V, V EE = V, R L = 1. M V CC = V, V EE = 2. V, R L = 1. M V CC = +5. V, V EE = V, R L = 6 V CC = V, V EE = 5. V, R L = 6 V CC = +2. V, V EE = V, R L = 6 V CC = V, V EE = 2. V, R L = 6 V CC = +2.5 V, V EE = 2.5 V, R L = 6 V CC = +2.5 V, V EE = 2.5 V, R L = 6 A VOL I SC I TH1 I TH2 V OH V OL V OH V OL V OH V OL V OH V OL V OH V OL Common Mode Rejection Ratio CMRR 6 9 db Power Supply Current (per Amplifier) V CC = +2. V, V EE = V T A = +25 C V CC = +2.5 V, V EE = 2.5 V T A = +25 C T A = 4 to +5 C V CC = +12 V, V EE = V T A = +25 C V CC = +2.5 V, V EE = 2.5 V T A = +25 C T A = 4 to +5 C Thermal Resistance SOIC Plastic DIP 4. Railtorail performance is achieved at the input of the amplifier by using parallel NPN PNP differential stages. When the inputs are near the negative rail (V EE < V CM < 8 mv), the PNP stage is on. When the inputs are above 8 mv (i.e. 8 mv < V CM < V CC ), the NPN stage is on. This switching of the input pairs will cause a reversal of input bias current. Slight changes in the input offset voltage will be noted between the NPN and PNP pairs. Cross coupling techniques have been used to keep this change to a minimum. I D JA mv V/ C na na db ma A V A C/W 3

4 MC3334 AC ELECTRICAL CHARACTERISTICS (V CC = +6. V, V EE = 6. V, R L = 6,, unless otherwise noted.) Characteristic Symbol Min Typ Max Unit Slew Rate (V CC = +2.5 V, V EE = 2.5 V, A V = +1.) (Note 6) SR.5.89 V/ s Gain Bandwidth Product (f = khz) GBW 2.2 MHz Gain Margin (C L = pf) (R L = 1. k ) Phase Margin (R L = 1. k, V O = V, C L = pf) to Transition Time R L = 6 R L = k to Transition Time t tr2 1.5 sec Channel Separation (f = 1. khz) A m m t tr1 CS db Deg sec db Power Bandwidth (V O = 4. V pp, R L = 2. k, THD 1.%) BW p 28 khz Distortion (V O = 2. V pp, A V = +1.) (f = khz) (f = 1. khz, R L = Infinite) Open Loop Output Impedance (V O = V, f = 2. MHz, A V = +, I Q = A) Differential Input Impedance (V CM = V) Differential Input Capacitance (V CM = V) Equivalent Input Noise Voltage (R S =, f = 1. khz) Equivalent Input Noise Current (f = 1. khz) THD Z O R IN C IN e n i n % k pf nv Hz pa Hz 6. When connected as a voltage follower and used in transient conditions, a current limiting resistor may be needed between the output and the inverting input. This is because of the back to back diodes clamped across the inputs. The value of this resistor should be between 1. k and k. If the amplifier does not become slew rate limited and is processing low frequency waveforms, then no resistor would be necessary. (The output could be tied directly to the negative input.) 4

5 MC3334 Fractional Load Current Detector % of I L Current Threshold Detector Awake to Delay Circuit I Hysteresis Buffer Buffer I Enable I ref C Storage Bias Bias Boost I L V in Input Stage Interface Stage Output Stage R L V out Overdrive Correction I Bias Enable Current Regulator I Sleep Current Regulator I Awake There are 515 active components for the entire quad device. Figure 1. Equivalent Circuit Block Diagram (Each Amplifier) 5

6 MC3334 DEVICE DESCRIPTION The MC3334 will begin to function at power supply voltages as low as V S = ±.8 V. The device has the ability to swing rail to rail on both the input and the output. Since the common mode input voltage range extends from V CC to V EE, it can be operated with either single or split voltage supplies. The MC3334 is guaranteed not to latch up or phase reverse over the entire common mode range. However, the output could go into phase reversal state if input voltage is set higher than +V CC or V EE. When power is initially applied, the part may start to operate in the awake mode. This occurs because of bias currents being generated from the charging of the internal capacitors. When this occurs, the user will have to wait approximately 1.5 seconds before the device will switch back to the sleep mode. The amplifier is designed to switch from sleep mode to awake mode whenever the output current exceeds a preset current threshold (I TH ) of approximately 2 A. As a result, the output switching threshold voltage (V ST ) is controlled by the output loading resistance (R L ). Large valued load resistors require a large output voltage to switch, but reduce unwanted transitions to the awake mode. Most of the transition time is consumed slewing in the sleep mode until V ST is reached, therefore, small values of R L allow rapid transition to the awake mode. The output switching threshold voltage (V ST ) is higher for the larger values of R L, requiring the amplifier to slew longer in the slower sleep mode state before switching to the awake mode. Although typically 2 A, I TH varies with supply voltage, temperature and the load resistance. Generally, any current loading on the output which causes a current greater than I TH to flow will switch the amplifier into the awake mode. This includes transition currents like those generated by charging load capacitances. In fact, the maximum capacitance that can be driven while attempting to remain in the sleep mode is approximately 3 pf. The awake mode to sleep mode transition time is controlled by an internal delay circuit, which is necessary to prevent the amplifier from going to sleep during every zero crossing of the output waveform. This delay circuit also eliminates the crossover distortion commonly found in micropower amplifiers. The MC3334 railtorail sleep mode operational amplifier is unique in its ability to swing railtorail on both the input and output using a bipolar design. This offers a low noise and wide common mode input voltage range. Since the common mode input voltage range extends from V CC to V EE, it can be operated with either single or split voltage supplies. Railtorail performance is achieved at the input of the amplifiers by using parallel NPNPNP differential input stages. When the inputs are within 8 mv of the negative rail, the PNP stage is on. When the inputs are more than 8 mv above V EE, the NPN stage is on. This switching of input pairs will cause a reversal of input bias currents. Also, slight differences in offset voltage may be noted between the NPN and PNP pairs. Crosscoupling techniques have been used to keep this change to a minimum. In addition to the railtorail performance, the output stage is current boosted to provide enough output current to drive 6 loads. Because of this high current capability, care should be taken not to exceed the 15 C maximum junction temperature specification. 6

7 MC k 15 P D(max), MAXIMUM POWER DISSIPATION (mw) 2. k 1.5 k 1. k.5 k -55 MC3334P MC3334P T A, AMBIENT TEMPERATURE ( C) I IB, INPUT BIAS CURRENT (na) T A, AMBIENT TEMPERATURE ( C) V CC = +5. V V EE = Gnd V CM = V Figure 2. Maximum Power Dissipation versus Temperature Figure 3. Input Bias Current versus Temperature I IB, INPUT BIAS CURRENT (na) V CC = +5. V V EE = Gnd A VOL, OPEN LOOP VOLTAGE GAIN (db) V CC = +5. V V EE = Gnd R L = 6 V O =.5 to 4.5 V V CM, COMMON MODE INPUT VOLTAGE (V) T A, AMBIENT TEMPERATURE ( C) Figure 4. Input Bias Current versus Common Mode Input Voltage Figure 5. Open Loop Voltage Gain versus Temperature V O, OUTPUT VOLTAGE (V pp ) R L = 6-1. M / ±1. ± 2. ± 3. ± 4. ± 5. ± 6. V CC, V EE SUPPLY VOLTAGE (V) V O, OUTPUT VOLTAGE SWING (V pp ) (R L = 1. M ) V CC = +6. V V EE = -6. V A V = f, FREQUENCY (khz) (R L = 6 ) 1. k Figure 6. Output Voltage Swing versus Supply Voltage Figure 7. Output Voltage versus Frequency 7

8 MC3334 V O, OUTPUT VOLTAGE SWING (V pp ) 1..1 V CC = +6. V V EE = -6. V f = 1. khz 1. k k k CMR, COMMOM MODE REJECTION (db) V CC = +6. V V EE = -6. V 1. k k k 1. m m R L, LOAD RESISTANCE TO GROUND ( ) Figure 8. Maximum PeaktoPeak Output Voltage Swing versus Load Resistance f, FREQUENCY (Hz) Figure 9. Common Mode Rejection versus Frequency PSR, POWER SUPPLY REJECTION (db) I, CURRENT THRESHOLD ( μ A) I TH ±PSR V CC = +6. V V EE = -6. V ±PSR 8 1. k k k 1. M M f, FREQUENCY (Hz) Figure. Power Supply Rejection versus Frequency T A = 125 C Source Current T A = -55 C V CC, V EE, SUPPLY VOLTAGE (V) Figure 12. to Current Threshold versus Supply Voltage I TH2, CURRENT THRESHOLD ( μ A) SC, OUTPUT SHORT CIRCUIT CURRENT (ma) T A = 125 C V CC, V EE, SUPPLY VOLTAGE (V) Source Current T A = -55 C Figure 11. to Current Threshold versus Supply Voltage Source Sink IV O I, OUTPUT VOLTAGE (V) V CC = +6. V V EE = -6. V V ID = ±1. V Figure 13. Output Short Circuit Current versus Output Voltage 8

9 MC3334, OUTPUT SHORT CIRCUIT CURRENT (ma) I D, SUPPLY CURRENT ( μ A) I SC Sink Source V CC = +5. V V EE = Gnd V ID = ±.2 V R L = 1. M T A, AMBIENT TEMPERATURE ( C) Figure 14. Output Short Circuit Current versus Temperature ( A) Single Supply No Load V CC, SUPPLY VOLTAGE (V) Figure 16. Supply Current versus Supply Voltage SUPPLY CURRENT ( μ A) I D, SR, SLEW RATE (V/ μ s) 4. k 3. k 2. k 1. k V CC = +2.5 V V EE = -2.5 V V O = ±2. V R L = 6 Single Supply R L = V CC, SUPPLY VOLTAGE (V) Figure 15. Supply Current versus Supply Voltage with Load + Slew Rate - Slew Rate T A, AMBIENT TEMPERATURE ( C) Figure 17. Slew Rate versus Temperature GBW, GAIN BANDWIDTH PRODUCT (MHz) V CC = V V EE = V f = khz A m, GAIN MARGIN (db) V CC = +6. V V EE = -6. V R T = R1 + R2 V O = V 1. k k T A, AMBIENT TEMPERATURE ( C) R T, DIFFERENTIAL SOURCE RESISTANCE ( ) Figure 18. Gain Bandwidth Product versus Temperature Figure 19. Gain Margin versus Differential Source Resistance 9

10 MC φ m, PHASE MARGIN ( ) V CC = +6. V V EE = -6. V R T = R1 + R2 V O = V 1. k R T, DIFFERENTIAL SOURCE RESISTANCE ( ) k, GAIN MARGIN (db) m A V CC = +6. V V EE = -6. V 1. k C L, OUTPUT LOAD CAPACITANCE (pf) Figure 2. Phase Margin versus Differential Source Resistance Figure 21. Gain Margin versus Output Load Capacitance PHASE MARGIN ( ) CS, CHANNEL SEPARATION (db) V CC = +6. V V EE = -6. V R L = 6 1. k 1. k k k C L, OUTPUT LOAD CAPACITANCE (pf) f, FREQUENCY (Hz) Figure 22. Phase Margin versus Output Load Capacitance Figure 23. Channel Separation versus Frequency THD, TOTAL HARMONIC DISTORTION (%) V CC = +6. V V EE = -6. V R L = 6 A V = A V = A V = A V = 1. V O = 2. V pp 1. k k k f, FREQUENCY (Hz) e n, INPUT REFERRED NOISE VOLTAGE (nv/ Hz) k f, FREQUENCY (Hz) V CC = +6. V V EE = -6. V k k Figure 24. Total Harmonic Distortion versus Frequency Figure 25. Input Referred Noise Voltage versus Frequency

11 MC3334 i n, INPUT NOISE CURRENT (pa/ Hz) f, FREQUENCY (Hz) V CC = +6. V V EE = -6. V (R S = k) 1. k k k OS, PERCENT OVERSHOOT (%) V CC = +6. V V EE = -6. V (R L = 6 ) C L, LOAD CAPACITANCE (pf) (R L = ) 1. k Figure 26. Current Noise versus Frequency Figure 27. Percent Overshoot versus Load Capacitance 11

12 MC PACKAGE DIMENSIONS B PDIP14 P SUFFIX CASE 6466 ISSUE M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. T SEATING PLANE N A INCHES MILLIMETERS DIM MIN MAX MIN MAX A F L B C D C F G. BSC 2.54 BSC H J K L K J M H G D 14 PL M N (.5) M SO14 D SUFFIX CASE 751A3 ISSUE F T SEATING PLANE G A D 14 PL 7 B K P 7 PL C.25 (.) M T B S A S.25 (.) M B M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION.15 (.6) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE.127 (.5) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS INCHES R X 45 F DIM MIN MAX MIN MAX A B C D M J F G 1.27 BSC.5 BSC J K M 7 7 P R ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 8217 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative MC3334/D

MARKING DIAGRAMS ORDERING INFORMATION Figure 1. Representative Schematic Diagram (Each Amplifier) DUAL MC33078P

MARKING DIAGRAMS ORDERING INFORMATION Figure 1. Representative Schematic Diagram (Each Amplifier) DUAL MC33078P The MC33078/9 series is a family of high quality monolithic amplifiers employing Bipolar technology with innovative high performance concepts for quality audio and data signal processing applications.