MC33078, MC MARKING DIAGRAMS. Features

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MC337, MC3379 Low Noise Dual/Quad Operational Amplifiers The MC337/9 series is a family of high quality monolithic amplifiers employing Bipolar technology with innovative high performance concepts

1 MC337, MC3379 Low Noise Dual/Quad Operational Amplifiers The MC337/9 series is a family of high quality monolithic amplifiers employing Bipolar technology with innovative high performance concepts for quality audio and data signal processing applications. This family incorporates the use of high frequency PNP input transistors to produce amplifiers exhibiting low input voltage noise with high gain bandwidth product and slew rate. The all NPN output stage exhibits no deadband crossover distortion, large output voltage swing, excellent phase and gain margins, low open loop high frequency output impedance and symmetrical source and sink AC frequency performance. The MC337/9 family offers both dual and quad amplifier versions and is available in the plastic DIP and SOIC packages (P and D suffixes). Features Dual Supply Operation: 5. V to V Low Voltage Noise: 4.5 nv/ Hz Low Input Offset Voltage:.5 mv Low T.C. of Input Offset Voltage: 2. V/ C Low Total Harmonic Distortion:.2% High Gain Bandwidth Product: 6 MHz High Slew Rate: 7. V/ s High Open Loop AC 2 khz Excellent Frequency Stability Large Output Voltage Swing: 4. V/ 4.6 V ESD Diodes Provided on the Inputs PbFree Packages are Available J Amplifier Biasing Z Q Q2 D Neg R C Q3 D2 R3 R2 Q4 Q5 Q6 R4 Q7 Pos D3 C2 Q R6 R5 Q9 R7 Q D4 C3 R9 Q V EE Q2 V CC Q3 V out 4 4 DUAL QUAD PDIP P SUFFIX CASE 626 SOIC D SUFFIX CASE 75 4 PDIP4 P SUFFIX CASE SOIC4 D SUFFIX CASE 75A A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or = PbFree Package MARKING DIAGRAMS MC337P AWL YYWWG 337 ALYW MC3379P AWLYYWWG MC3379DG AWLYWW ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page of this data sheet. Figure. Representative Schematic Diagram (Each Amplifier) Semiconductor Components Industries, LLC, 26 October, 26 Rev. 7 Publication Order Number: MC337/D

2 MC337, MC3379 PIN CONNECTIONS DUAL CASE 626/75 QUAD CASE 646/75A Output Inputs V EE (Dual, Top View) V CC Output 2 Inputs 2 Output Inputs V CC Inputs 2 Output Output 4 Inputs 4 V EE Inputs 3 Output 3 (Quad, Top View) MAXIMUM RATINGS Rating Symbol Value Unit Supply Voltage (V CC to V EE) V S 36 V Input Differential Voltage Range V IDR Note V Input Voltage Range V IR Note V Output Short Circuit Duration (Note 2) t SC Indefinite sec Maximum Junction Temperature T J 5 C Storage Temperature T stg 6 to 5 C ESD Protection at any Pin MC337 MC3379 Human Body Model Machine Model Human Body Model Machine Model V esd Maximum Power Dissipation P D Note 2 mw Operating Temperature Range T A 4 to 5 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.. Either or both input voltages must not exceed the magnitude of V CC or V EE. 2. Power dissipation must be considered to ensure maximum junction temperature (T J ) is not exceeded (see Figure 2). V 2

3 MC337, MC3379 DC ELECTRICAL CHARACTERISTICS (, V EE = 5 V,, unless otherwise noted.) Characteristics Symbol Min Typ Max Unit Input Offset Voltage (R S =, V CM = V, V O = V) (MC337)T A = 25 C T A = 4 to 5 C (MC3379)T A = 25 C T A = 4 to 5 C Average Temperature Coefficient of Input Offset Voltage V IO / T 2. V/ C R S =, V CM = V, V O = V, T A = T low to T high Input Bias Current (V CM = V, V O = V) T A = 25 C T A = 4 to 5 C Input Offset Current (V CM = V, V O = V) T A = 25 C T A = 4 to 5 C Common Mode Input Voltage Range ( V IO = 5. mv, V O = V) V ICR ±3 ±4 V Large Signal Voltage Gain (V O = V, R L = 2. k ) T A = 25 C T A = 4 to 5 C Output Voltage Swing (V ID =.V) R L = 6 R L = 6 R L = 2. k R L = 2. k R L = k R L = k V IO I IB I IO A VOL 9 5 V O V O V O V O V O V O Common Mode Rejection (V in = ±3V) CMR db Power Supply Rejection (Note 3) V CC /V EE = 5 V/ 5 V to 5. V/ 5. V mv na na db PSR 5 db V Output Short Circuit Current (V ID =. V, Output to Ground) Source Sink I SC ma Power Supply Current (V O = V, All Amplifiers) (MC337) T A = 25 C (MC337) T A = 4 to 5 C (MC3379) T A = 25 C (MC3379) T A = 4 to 5 C I D ma 3. Measured with V CC and V EE differentially varied simultaneously. 3

4 MC337, MC3379 AC ELECTRICAL CHARACTERISTICS (, V EE = 5 V,, unless otherwise noted.) Characteristics Symbol Min Typ Max Unit Slew Rate (V in = V to V, R L = 2. k, C L = pf A V =.) SR V/ s Gain Bandwidth Product (f = khz) GBW 6 MHz Unity Gain Bandwidth (Open Loop) BW 9. MHz Gain Margin (R L = 2. k ) C L = pf C L = pf Phase Margin (R L = 2. k ) C L = pf C L = pf Channel Separation (f = 2 Hz to 2 khz) CS 2 db Power Bandwidth (V O = 27 V pp, R L = 2. k, THD.%) BW p 2 khz Total Harmonic Distortion (R L = 2. k, f = 2 Hz to 2 khz, V O = 3. V rms, A V =.) A m m db Deg THD.2 % Open Loop Output Impedance (V O = V, f = 9. MHz) Z O 37 Differential Input Resistance (V CM = V) R in 75 k Differential Input Capacitance (V CM = V) C in 2 pf Equivalent Input Noise Voltage (R S =, f =. khz) e n 4.5 nv/ Hz Equivalent Input Noise Current (f =. khz) i n.5 Hz pa/ PМ, D MAXIMUM POWER DISSIPATION (mw) IМ, IB INPUT BIAS CURRENT (na) MC337P & MC3379P MC3379D MC337D Figure 2. Maximum Power Dissipation versus Temperature V EE = 5 V V CM = V Figure 4. Input Bias Current versus Temperature IМ, IB INPUT BIAS CURRENT (na) VМ, IO INPUT OFFSET VOLTAGE (mv) V CM = V V CC, V EE, SUPPLY VOLTAGE (V) 2... V EE = 5 V R S = V CM = V A V = Figure 3. Input Bias Current versus Supply Voltage Unit Unit 2 Unit Figure 5. Input Offset Voltage versus Temperature 4

5 IМ, IB INPUT BIAS CURRENT (na) V CM, COMMON MODE VOLTAGE (V) Figure 6. Input Bias Current versus Common Mode Voltage MC337, MC3379 V EE = 5 V, INPUT COMMON MODE VOLTAGE RANGE (V) V ICR V CC V CC.5 V CC. V CC.5 V EE.5 V EE. V EE.5 V CM V CC = 3. V to 5 V V EE = 3. V to 5 V V IO = 5. mv V O = V Voltage Range V CM V EE Figure 7. Input Common Mode Voltage Range versus Temperature, OUTPUT SATURATION VOLTAGE (V) sat V V CC. V CC 3. V CC 5. V EE 5. V EE C 55 C 25 C 25 C 25 C 25 C V EE = 5 V V EE R L, LOAD RESISTANCE TO GROUND (k ) IМ, SC OUTPUT SHORT CIRCUIT CURRENT (ma) Sink Source V EE = 5 V R L < V ID =. V Figure. Output Saturation Voltage versus Load Resistance to Ground Figure 9. Output Short Circuit Current versus Temperature IМ, CC SUPPLY CURRENT (ma) ±5 V ±5. V ±5 V ±5. V ±4. V ± V ± V Supply Voltages V CM = V R L = V O = V MC3379 MC337 CMR, COMMON MODE REJECTION (db) V EE = 5 V V CM = V V CM = ±.5 V V CM CMR = 2Log A DM V CM A DM V O V O 2. k k k. M M Figure. Supply Current versus Temperature Figure. Common Mode Rejection versus Frequency 5

6 MC337, MC3379 PSR, POWER SUPPLY REJECTION (db) PSR = 2Log PSR PSR V O /A DM V CC PSR = 2Log A DM V O /A DM V CC V CC 4 2 V EE = 5 V. k k k. M M V EE Figure 2. Power Supply Rejection versus Frequency V O GWB, GAIN BANDWIDTH PRODUCT (MHz) 3 2 V CC V EE, SUPPLY VOLTAGE (V) R L = k C L = pf f = khz Figure 3. Gain Bandwidth Product versus Supply Voltage GWB, GAIN BANDWIDTH PRODUCT (MHz) V EE = 5 V f = khz R L = k C L = pf Figure 4. Gain Bandwidth Product versus Temperature V O, OUTPUT VOLTAGE (Vp) R L = k R L = 2. k 5. R L = 2. k R L = k 5 V O V CC V EE, SUPPLY VOLTAGE (V) Figure 5. Maximum Output Voltage versus Supply Voltage V O V O, OUTPUT VOLTAGE (V pp ) V CC = 5 V R L = 2. k A V =. THD.%. k k k. M M AМ, VOL OPEN LOOP VOLTAGE GAIN (db) 9 R L = 2. k f Hz V O = 2/3 (V CC V EE ) V CC V EE, SUPPLY VOLTAGE (V) Figure 6. Output Voltage versus Frequency Figure 7. Open Loop Voltage Gain versus Supply Voltage 6

7 MC337, MC3379 AМ, VOL OPEN LOOP VOLTAGE GAIN (db) 5 95 V EE = 5 V R L = 2. k f Hz V O = V to V Figure. Open Loop Voltage Gain versus Temperature ZМ, O OUTPUT IMPEDANCE (М ) Ω V EE = 5 V V O = V A V = A V = A V = A V =.. k k k. M M Figure 9. Output Impedance versus Frequency CS, CHANNEL SEPARATION (db) k V OM MC337 MC3379 Drive Channel V EE = 5 V R L = 2. K V OD = 2 V pp V OA Measurement Channel CS = 2 Log V OM. k k k THD, TOTAL HARMONIC DISTORTION (%)... V EE = 5 V V O =. Vrms.. k k k V O 2. k Figure 2. Channel Separation versus Frequency Figure 2. Total Harmonic Distortion versus Frequency THD, TOTAL HARMONIC DISTORTION (%). V EE = 5 V.5 f = 2. khz A V = A V = A V = A V = V O, OUTPUT VOLTAGE (Vrms) Figure 22. Total Harmonic Distortion versus Output Voltage R A V in k V O 2. k SR, SLEW RATE (V/ μ s) V in = 2/3 (V CC V EE ) V in 2. k V O Falling Rising V CC V EE, SUPPLY VOLTAGE (V) Figure 23. Slew Rate versus Supply Voltage 7

8 i MC337, MC3379 SR, SLEW RATE (V/Мs) μ V EE = 5 V V in = 2 V V in Falling Rising 2. k V O Figure 24. Slew Rate versus Temperature AММ, VOL OPEN LOOP VOLTAGE GAIN (db) Gain V EE = 5 V R L = 2. k Phase.. k k k. M M Figure 25. Voltage Gain and Phase versus Frequency φ, EXCESS PHASE (DEGREES) AМ, m OPEN LOOP GAIN MARGIN (db) V in 2. k V EE = 5 V V O = V 25 C C L V O 25 C 25 C 55 C Phase C 55 C 6 Gain 7 C L, OUTPUT LOAD CAPACITANCE (pf) Figure 26. Open Loop Gain Margin and Phase Margin versus Load Capacitance φ m, PHASE MARGIN (DEGREES) os, OVERSHOOT (%) V in C L V O 25 C 25 C 55 C V EE = 5 V V in = mv. k k C L, OUTPUT LOAD CAPACITANCE (pf) Figure 27. Overshoot versus Output Load Capacitance eм, n INPUT REFERRED NOISE VOLTAGE (ММММ) nv/ Hz k k k V EE = 5 V Voltage Current Figure 2. Input Referred Noise Voltage and Current versus Frequency n, INPUT REFERRED NOISE CURRENT ( pa/ Hz ) V, REFERRED NOISE VOLTAGE nv/ ( Hz ) n V EE = 5 V f =. khz V n (total) = (i nrs) 2 en 2 4KTRS.. k k k. M R S, SOURCE RESISTANCE ( ) Figure 29. Total Input Referred Noise Voltage versus Source Resistance

MC337, MC3379 4 7 A m, GAIN MARGIN (db) 2.

k k k R T, DIFFERENTIAL SOURCE RESISTANCE ( ) Figure 3.

(DEGREES) φ m VМ, O OUTPUT VOLTAGE (5. V/DIV) V EE = 5 V A V =. R L = 2.

s/div) t, TIME (2. s/div) Figure 3. Inverting Amplifier Slew Rate Figure 32.

9 MC337, MC A m, GAIN MARGIN (db) R R 2 V EE = 5 V R T = R R 2 A V = V O = V V O Phase Gain. k k k R T, DIFFERENTIAL SOURCE RESISTANCE ( ) Figure 3. Phase Margin and Gain Margin versus Differential Source Resistance , PHASE MARGIN (DEGREES) φ m VМ, O OUTPUT VOLTAGE (5. V/DIV) V EE = 5 V A V =. R L = 2. k C L = pf VМ, O OUTPUT VOLTAGE (5. V/DIV) V EE = 5 V A V =. R L = 2. k C L = pf t, TIME (2. s/div) t, TIME (2. s/div) Figure 3. Inverting Amplifier Slew Rate Figure 32. Noninverting Amplifier Slew Rate VМ, O OUTPUT VOLTAGE (5. V/DIV) V EE = 5 V R L = 2. k C L = pf A V =. eм, INPUT NOISE VOLTAGE ( nv/div) n V EE = 5 V BW =. Hz to Hz t, TIME (2 s/div) t, TIME (. sec/div) Figure 33. Noninverting Amplifier Overshoot Figure 34. Low Frequency Noise Voltage versus Time 9

10 MC337, MC3379. F k 2. k D.U.T. 4.7 F Voltage Gain = 5, /2 MC337 k 4.3 k 2.2 F 22 F Scope R in =. M 24.3 k. F k Note: All capacitors are nonpolarized. Figure 35. Voltage Noise Test Circuit (. Hz to Hz pp ) ORDERING INFORMATION MC337D MC337DG Device Package Shipping SOIC SOIC (PbFree) 9 Units / Rail MC337DR2 MC337DR2G MC337P MC337PG MC3379D MC3379DG MC3379DR2 MC3379DR2G SOIC SOIC (PbFree) PDIP PDIP (PbFree) SOIC4 SOIC4 (PbFree) SOIC4 SOIC4 (PbFree) 25 / Tape & Reel 5 Units / Rail 55 Units / Rail 25 / Tape & Reel MC3379P MC3379PG PDIP4 PDIP4 (PbFree) 25 Units / Rail For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD/D.

11 MC337, MC3379 PACKAGE DIMENSIONS PDIP P SUFFIX CASE 6265 ISSUE L 5 B NOTES:. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, 92. NOTE 2 T SEATING PLANE H 4 F A C N D K G.3 (.5) M T A M B M L J M MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G 2.54 BSC. BSC H J K L 7.62 BSC.3 BSC M N

12 MC337, MC3379 PACKAGE DIMENSIONS SOIC NB CASE 757 ISSUE AH Y B X A 5 4 S.25 (.) M Y M K NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION.5 (.6) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE.27 (.5) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION THRU 756 ARE OBSOLETE. NEW STANDARD IS 757. Z H G D C.25 (.) M Z Y S X S SEATING PLANE. (.4) N X 45 M J MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D G.27 BSC.5 BSC H J K M N S SOLDERING FOOTPRINT* SCALE 6: mm inches *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 2

13 MC337, MC3379 PACKAGE DIMENSIONS PDIP4 CASE 6466 ISSUE P 4 7 B NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. T N SEATING PLANE A INCHES MILLIMETERS DIM MIN MAX MIN MAX A B F L C D C F G. BSC 2.54 BSC H J K K J L M H G D 4 PL M N (.5) M 3

14 MC337, MC3379 SOIC4 CASE 75A3 ISSUE H T SEATING PLANE G A 4 D 4 PL 7 B K P 7 PL C.25 (.) M T B S A S.25 (.) M B M NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION.5 (.6) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE.27 (.5) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS INCHES R X 45 F DIM MIN MAX MIN MAX A B C D M J F G.27 BSC.5 BSC J K M 7 7 P R SOLDERING FOOTPRINT* 4X.5 7X 7.4 4X PITCH DIMENSIONS: MILLIMETERS *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 563, Denver, Colorado 27 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative MC337/D

MARKING DIAGRAMS ORDERING INFORMATION Figure 1. Representative Schematic Diagram (Each Amplifier) DUAL MC33078P

MARKING DIAGRAMS ORDERING INFORMATION Figure 1. Representative Schematic Diagram (Each Amplifier) DUAL MC33078P The MC33078/9 series is a family of high quality monolithic amplifiers employing Bipolar technology with innovative high performance concepts for quality audio and data signal processing applications.