A Highly Digitized Multimode Receiver Architecture for 3G Mobiles

Transcription

1 IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY, VOL. 52, NO. 3, MAY A Highly Digitized Multimode Receiver Architecture for 3G Mobiles Brian J. Minnis, Senior Member, IEEE, and Paul A. Moore Abstract A highly digitized multimode receiver architecture is described. It is configured primarily for the Universal Mobile Telecommunication System (UMTS) and Global System for Mobile Communications (GSM) modes, but has the potential to operate in other modes such as CDMA2000 as well. The receiver uses a single down conversion to mix the RF signal to a zero intermediate frequency (IF) for UMTS mode and a low IF for GSM. It uses a reconfigurable analog-to-digital converter (ADC) to digitize the IF signals as early as possible and to transfer most of the channel filtering into the digital domain. Only a minimum of automatic gain control (AGC) is employed. The architecture aims to maximize reuse of common hardware and to make significant gains in terms of design costs, size, and adaptability. System simulations confirm the feasibility and performance of the new concept. Index Terms Mobile, multimode, receiver, third generation. I. INTRODUCTION DURING the early deployment of third-generation (3G) cellular services, new handset products will be needed that operate in at least two modes. For a given region, they must operate not only in the appropriate 3G mode, but also in the existing second-generation (2G) mode to ensure adequate geographical coverage. In the longer term, still further modes will need to be added, as handset functionality evolves to include broadcast and other high-speed wireless data services. The natural consequences of multimode operation for the handset are generally an increase in size, cost, and complexity. One way to mitigate this is to employ new transceiver architectures that maximize the reuse of components within a minimal set of common hardware. This was the main motivation for the work to be described. This paper focuses on the receiver part of the problem, presenting a detailed investigation of a new multimode architecture for 3G mobiles. As reuse of hardware is generally easier in the digital rather than the analog domain, the basic approach is to digitize as much of the receiver signal chain as possible. This is made easier if the receiver uses a single stage of down conversion to either a low or a zero intermediate frequency (IF). The analog-to-digital converter (ADC) is positioned immediately after the down converter, eliminating the need for any analog channel filters or automatic gain control (AGC). While making reconfiguration easier, moving the ADC to such a forward location in the receiver requires the processing of a much greater dynamic range. Therefore, finding a suitable ADC with Manuscript received December 14, 2001; revised July 19, The authors are with Philips Research Laboratories, Redhill, Surrey RH1 5HA, U.K. ( brian.minnis@philips.com). Digital Object Identifier /TVT a sufficiently large dynamic range and a low power consumption is critical to the success of the architecture. The particular standards addressed in the paper are the global system for mobile (GSM) communications and the frequency-division duplex (FDD) mode of UMTS (universal mobile telecommunication system). These are the 2 and 3G cellular standards most relevant in Europe. However, the time-division duplex (TDD) mode of UMTS should also be within the scope of the basic architecture, as should other modes such as CDMA2000 and time-division synchronous code division multiple access (TD-SCDMA), which are relevant in other parts of the world. The main body of the paper will begin by summarizing the basic performance requirements of the receiver in the UMTS and GSM modes. It will present a conventional approach to the architecture before dealing in turn with the different configurations of the new architecture needed for the two modes. In each case, in adddition to describing the architecture, the sections will describe the dimensioning of the various functional blocks, deriving values for some of the most important parameters, such as noise figure and ADC dynamic range. Descriptions will also be given of the design of critical components such as the ADC and the rather special filters needed for the GSM mode. Results of system simulations will be presented to verify the feasibility of the new architecture. The latter part of the paper will describe how the two configurations for UMTS and GSM merge together to form the resultant dual-mode receiver architecture. II. PERFORMANCE REQUIREMENTS A. UMTS The UMTS standard is based on wideband code-division multiple access (W-CDMA), for which the technical specifications are now under the responsibility of the 3G Partnership Project (3GPP) [1]. It is a direct-sequence, spread-spectrum system in which users are separated by means of a set of pseudorandom orthogonal codes. In the FDD mode, mobile reception is within the band of 2110 to 2170 MHz (Region 1). The channel spacing is nominally 5 MHz, although there is a 200-kHz raster. After spreading and scrambling, the quadrature phse-shift keying (QPSK) modulation occupies an instantaneous bandwidth equal to the chip rate of 3.84 MHz. The specifications most relevant to the receiver design can be found in references [2] [4]. With particular reference to [2], the various receiver characteristics relate to a bit error rate (BER) of 0.1% for the 12.2 kb/s service, to be achieved under various different signal conditions and in a static propagation channel /03$ IEEE

2 638 IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY, VOL. 52, NO. 3, MAY 2003 TABLE I RECEIVER CHARACTERISTICS FOR UMTS TABLE II RECEIVER CHARACTERISTICS FOR GSM Channel coding is of the one-third rate convolutional type with a constraint length of 9. This corresponds to a physical bit rate of 60 kb/s or a symbol rate of 30 kb/s, given the QPSK modulation. The most important receiver characteristics for UMTS can be summarized as found in Table I. B. GSM The GSM standard, in contrast, is based on a mixture of time-division multiple access (TDMA) and frequency-division multiple access (FDMA). Each user is allocated a particular frequency channel of width 200 khz and a time slot of duration s. Over the frequency range of 915 to 960 MHz, there are 175 available channels and over a period of 4.16 ms, there are eight available time slots. The information rate is typically 9.6 kb/s, which, after channel-coding and training bits are added, translates into a physical bit rate of kb/s. The type of modulation used is Gaussian minimum-shift keying (GMSK) with a BT shape factor of 0.3. Full details of the performance requirements that are relevant to the design of the receiver in GSM mode can be found in [5]. These relate to a small mobile terminal receiving full-rate speech. There are several different fading conditions under which the terminal must operate, the most relevant of which are the static, TU50, and EQ50 profiles. With a static profile (i.e., no fading), the BER requirement is generally 2% unless specified otherwise. For the TU50 profile, which is intended to represent a typical urban situation where the terminal is limited to a velocity of 50 km/h, the BER requirement is 8%. A 3% BER usually applies to the EQ50 profile. The most important of the receiver characteristics for GSM are given in Table II. Notwithstanding the differences listed in Tables I and II, it is the difference between the bandwidths of the two signals in the UMTS and GSM modes that exercises the strongest influence on the receiver architecture. III. A CONVENTIONAL APPROACH In the architecture shown in Fig. 1, the signals for the UMTS and GSM modes are processed in separate receiver chains and there is very little reuse of common hardware. For the sake of clarity, only the UMTS part is shown in detail, but both could be based on the same dual-conversion superhet concept. Using two separate receivers offers the possibility of operating in both modes simultaneously, but the need for this should not be great since handover between the modes can be accommodated by the UMTS compressed mode. Fig. 1 indicates that the RF input is mixed down to a first IF of the order of 200 MHz and then mixed down again by a quadrature pair of mixers to a zero IF. Choosing such a high first IF ensures that the image frequency of the wanted signal can be rejected by the RF filter. Channel selectivity would normally be provided by a high-q analog filter in the first IF stage, with only a small contribution coming from the digital filters in the second IF. Such analog filters cannot be realized on an integrated circuit. Automatic gain control would be implemented as an analog function in the RF and/or the first IF stages. A control range somewhere in the region of 90 db is needed, which is a demanding requirement for the variable-gain amplifier(s). ADC takes place relatively late in the receiver chain, where signal bandwidths have already been restricted and the dynamic range is low. This helps to reduce power consumption in the ADCs but means that most of the signal processing in the receiver is necessarily in the analog domain. The dual-conversion superhet is a low-risk receiver solution offering excellent performance in terms of sensitivity, selectivity, and low power consumption. However, its reliance on highly selective analog channel filters and its substantial use of AGC makes it relatively expensive and difficult to reconfigure for other modes. IV. NEW ARCHITECTURE FOR UMTS (FDD) MODE In the interest of integrating the channel filters and reusing common hardware, a single down conversion to a low or zero IF is an attractive option. It allows the channel filters to be integrated as active devices, thereby reducing assembly costs and giving the receiver better scope for reconfiguration. However, the scope is further improved if the ADC function is moved forward in the signal chain so that most of the AGC is eliminated and the channel filtering takes place in the digital domain. Such changes have been implemented in the new receiver architecture, illustrated in Fig. 2. As previously reported [6], operating with a zero IF can bring about several important advantages. By using the lowest possible IF, the wanted signal is confined to the smallest possible bandwidth, leading to a useful power saving in the ADCs and channel filters. Furthermore, the need to filter any image of the wanted signal is completely avoided. There are some disadvantages to be taken into consideration, however, not the least of

3 MINNIS AND MOORE: HIGHLY DIGITIZED MULTIMODE RECEIVER ARCHITECTURE FOR 3G MOBILES 639 Fig. 1. A conventional architecture solution. Fig. 2. New architecture configuration for UMTS mode. which are the adverse effects of dc offsets and second-order intermodulation products generated in the mixers of the front end. With a zero IF, such unwanted products occupy the same band as the wanted signal and can seriously desensitize the receiver. This is particularly true for narrowband systems such as GSM. In the case of UMTS, these disadvantages do not apply mainly due to the spread-spectrum nature of the modulated signal. With such a wide bandwidth, it is possible to use ac coupling after the mixer of the front end to filter out the dc offsets and many of the other second-order products. The hole produced by the ac coupling in the center of the signal spectrum disappears after despreading, leading to only a slight loss of signal-to-noise ratio (SNR) at the demodulator. Consequently, a zero IF receiver architecture is a very attractive solution for UMTS. With reference to Fig. 2, the incoming RF signal is mixed directly to a zero IF. The and quadrature components of the IF pass through a pair of first-order lowpass prefilters whose function is to attenuate some of the largest blocking interferers at frequency offsets greater than 15 MHz. A pair of single-step AGC elements reduce the total power in the 5-MHz bandwidth of the wanted signal for the top 19 db of its dynamic range. These blocks break the basic principle of eliminating all analog filtering and AGC, but give a worthwhile reduction in ADC dynamic range and neither is a serious impediment to reconfiguration. The ADCs are sigma-delta ( ) modulator types and are particularly well suited to this sort of application. They have a large dynamic range capability with excellent power efficiency and are highly tolerant of IC process variations. Their output is a very fast stream of binary samples whose average value represents the instantaneous value of the analog input. A time-continuous loop filter helps minimize the need for any additional

4 640 IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY, VOL. 52, NO. 3, MAY 2003 Fig. 3. Calculating noise figure for UMTS mode. anti-alias filtering. Immediately after the ADCs, a pair of digital filters provide the receiver with the bulk of its selectivity. These remove the incoming interferers as well as the high-frequency quantization noise generated by the ADCs. They have a root-raised-cosine (RRC) characteristic with a shape factor to match the characteristic used in the baseband filter of the basestation transmitter. To minimize power consumption, it is critical that these filters perform their filtering and decimation tasks in a single step. This exploits the bitstream nature of the output of the ADCs and avoids the need for digital multiplication. A. Receiver Dimensions Some of the most important receiver dimensions to be determined include noise figure, frequency selectivity, and the dynamic range requirement of the modulators. In calculating the noise figure, it is necessary to first consider the SNR requirement at the input to the QPSK demodulator for a BER of 0.1%. According to theory [7] for plain QPSK modulation, the required to achieve a BER of 0.1% is approximately 7 db, where is the energy per bit and is the noise density. As there are two bits per symbol, the SNR required must therefore be 10 db in a 30-kHz bandwidth (i.e., for a bit-duration bandwidth product of unity). When the effects of convolutional channel coding are added for the 12.2-kb/s service, system simulations show that the SNR at the input to the demodulator can be reduced by approximately 9 db for the same 0.1% BER. Hence, the resultant SNR at the demodulator could be as low as 1 db. If a margin of 2.5 db is added to allow for some performance degradation, a prudent target value of SNR is then 3.5 db. The receiver noise figure is derived from the reference sensitivity requirement of 117 dbm with the aid of the diagram given in Fig. 3. Applying the 21 db of spreading gain and taking account of the SNR requirement of 3.5 db, the equivalent input receiver noise power must be 99.5 dbm. In a 1-Hz bandwidth, this becomes dbm, whereupon subtraction of the thermal noise level of dbm yields a noise figure of 8.5 db. More formally, we can write SNR (1) where is the equivalent receiver noise power, is the reference sensitivity, is the spreading gain, SNR is the SNR required for a 0.1% BER using plain qpsk modulation, is the coding gain, and represents the performance margin. Substituting the appropriate parameter values gives and then the noise figure is given by dbm (2) db (3) The noise figure of the front end must be rather less than this to take account of the losses in the RF duplexer and the noise contribution of the ADCs. If 2.5 db is assigned to duplexer losses and 0.5 db to ADC noise, the front-end noise figure requirement must be nearer 5.5 db. It should be noted that the calculation assumes all incoming cochannel noise is orthogonal to the wanted signal and is completely removed by the despreading process. For the adjacent-channel test, the receiver must achieve a 0.1% BER with a wanted signal,,at 103 dbm and a modulated interferer,, at a level of 52 dbm. As in the noise figure calculation, the incoming cochannel orthogonal noise can be ignored. Once the spreading gain of 21 db is applied, the effective signal power rises to 82 dbm. By subtracting by the SNR requirement of 3.5 db, the maximum tolerable residue of the interferer after channel filtering is 85.5 dbm. Hence, the adjacent-channel rejection requirement,, is given by SNR db (4)

5 MINNIS AND MOORE: HIGHLY DIGITIZED MULTIMODE RECEIVER ARCHITECTURE FOR 3G MOBILES 641 Fig. 4. A fourth-order sigma-delta modulator with a three-level output. With regard to the blocking-interferer tests, the receiver must achieve the 0.1% BER with a wanted signal at a level of 114 dbm, which is only 3 db above the reference sensitivity. The blocking signal at a 15-MHz offset is fully modulated and at a level of 44 dbm. The spreading gain increases the effective wanted signal power to 93 dbm and the SNR requirement of 3.5 db places the combination of the receiver noise and the residue of the interferer after channel filtering at 96.5 dbm. Coincidentally, this power splits equally between these two components and, hence, the residue of the interferer must be another 3 db lower at 99.5 dbm. The distance between this level and the level of the interferer at 44 dbm gives the filter rejection requirement,, of 55.5 db, i.e., SNR db (5) It will become apparent that both the adjacent-channel and the blocking interferer rejection requirements are well within the capabilities of the digital-channel filter with its RRC characteristic. To deal with the unmodulated blocking interferers at 60- and 85-MHz offsets, however, the extra attenuation required must be provided by the analog prefilter and RF duplexer. Hence, the prefilter should provide at least 14-dB attenuation at the 60-MHz offset and the duplexer an extra 15 db at the 85-MHz offset. A suitable cutoff frequency for the prefilter is 8.5 MHz. The dynamic range requirement of the ADCs is determined by the largest input signal, which must be handled and by the amount of quantization noise that can be tolerated. As far as the largest signal,, is concerned, this is 44 dbm on the assumption that all input signals will be reduced to the level of the 15-MHz blocking interferer before they reach the ADCs. The analog prefilters perform this task for the 60- and 85-MHz blocking interferers and the single-step AGC deals with the large cochannel signals, whose maximum input level is 25 dbm. The quantization noise level is calculated on the assumption that the ADC will degrade the receiver noise figure by 0.5 db. Hence, if the receiver noise power is 99.5 dbm, the noise generated by the front end alone must be 100 dbm. Then the quantization noise must be approximately another 10 db below this at 110 dbm. The ADC dynamic range requirement is, therefore, 66 db, i.e., db (6) The two modulators must provide this range, each quantizing an effective signal bandwidth of MHz. B. Sigma-Delta Modulator ADC Sigma-delta modulators and their use as ADCs are discussed in some detail in [8] and [9]. As explained, they offer high conversion efficiency, excellent linearity, and strong immunity to aliasing due to their high over-sampling ratio. Their basic principle of operation is illustrated by the diagram given in Fig. 4. There are three main parts to the modulator; the loop filter in the forward signal path, the output comparator, and the digital-to-analog converter (DAC) in the feedback path. Hence, the modulator resembles something of a feedback amplifier with a saturated output stage. Signals entering the modulator are amplified by the loop filter and then quantized into a set of only two or three output levels. In this particular case, there are three output levels with the notional values 1, 0, and 1, but more often the number of levels is restricted to just two (i.e., 1). The effect of the quantization is to generate very large quantities of noise, without which the help of the feedback would completely obliterate the wanted signal. However, by feeding the noisy output signal back to the input via the very simple DAC, the loop filter is able to alter the shape of the frequency spectrum of the noise and to move most of its power to a very high frequency, away from the vicinity of the wanted signal. It is then the task of the digital filter following the modulator to remove the quantization noise and to construct a multibit representation of the wanted signal with the required resolution. The total amount of quantization noise generated is determined by the number of output quantization levels. Using three levels instead of two, therefore, reduces the total noise power by 6 db. However, the noise density is a function of the sampling frequency and the frequency characteristics of the loop filter. Hence, the sampling frequency must be high in order to spread the noise over a wide bandwidth and the loop filter must have a characteristic that provides maximum gain at low frequencies.

6 642 IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY, VOL. 52, NO. 3, MAY 2003 Fig. 5. Output spectrum of the fourth-order sigma-delta modulator. Typically, the loop filter comprises a cascade of integrators. If these are realized as time-continuous circuits, the need for any anti-alias filters before the modulator is largely avoided. Experiments with a behavioral model based on Fig. 4 have established that the performance requirement of a 66 db dynamic range in a 1.92-MHz bandwidth for UMTS can be met with a fourth-order loop filter of the type shown. This assumes the use of the three-level quantizer and a sampling frequency of MHz (i.e., 40 chip rate of 3.84 MHz). As indicated, this is a so-called feed-forward filter structure in which outputs from all four integrators are suitably weighted and added together at the common output. Two of the integrators are surrounded by a feedback element, which generates a conjugate pair of transmission poles at 2.33 MHz. Offsetting the pair of poles in this way gives the loop filter a greater average gain over a 1.92-MHz bandwidth, leading to more effective noise shaping and a correspondingly lower level of quantization noise. Each integrator output passes through a clipping circuit that limits the output swing to a level of. These help to maintain loop stability under large drive conditions by progressively reducing the effective loop gain. They also prevent the loop from entering a latch-up condition. Having chosen suitable values for the set of parameters,,, and the DAC gain, the fourth-order modulator of Fig. 4 produces the output spectrum shown in Fig. 5 when its input signal is a simple 1-MHz tone with a relative amplitude of 0.7. In relation to the output swing of the comparator, this magnitude of input signal represents the maximum that the modulator can process while still maintaining good noise shaping. As shown, the quantization noise level is low within a bandwidth of approximately 2.5 MHz, rises steeply outside this band, and reaches a maximum at half the sampling frequency (i.e., 76.8 MHz). It is also possible to see the hole in the noise caused by the transmission pole of the loop filter at 2.33 MHz. The second curve shown in Fig. 5 is the spectrum of the modulator output after it has been filtered by the digital-channel filter. As well as having the necessary RRC characteristic, this filter also decimates by a factor of five to reduce the sampling rate from MHz at the output of the modulator to the MHz typically required at the input to the rake correlator. As required, the spectrum within a 1.92-MHz bandwidth is largely unchanged but the high-frequency quantization noise above 1.92 MHz has been heavily attenuated. By integrating the power in the spectrum and subtracting the power in the 1-MHz tone, it is possible to determine that the dynamic range achieved by the modulator is 80.5 db. Although the value is very much better than the 66-dB target requirement, it must be stressed that this simulation only includes quantization noise and does not include the circuit and thermal noise that will inevitably be generated in the analog parts of the loop filter. There will also be a noise contribution from clock jitter. C. System Simulations A series of system simulations have been carried out, the results of which are presented in Figs The objectives were to validate the new receiver architecture and to confirm that it would achieve the necessary performance given the particular dimensions assigned to its various parts. To simplify the simulation, the model used to represent the receiver accepts an input signal that is essentially the baseband output of the basestation transmitter. Hence, the low-noise amplifier and mixers of the receiver are represented as linear devices whose only effect on the signal is to add additive white Gaussian noise (AWGN). The minor disadvantage of this is that it is not possible to model the effects of front-end nonlinearity. All the filters of the system shown in Fig. 2 are modeled as finite impulse response (FIR) devices, including the analog prefilters and ac couplings. The preamplifiers before the modulators have a gain of 41 db, to map the 44 dbm power of a 15-MHz blocking signal to the 3 dbm maximum-effective drive level of the pair of modulators. The modulators themselves are represented by

7 MINNIS AND MOORE: HIGHLY DIGITIZED MULTIMODE RECEIVER ARCHITECTURE FOR 3G MOBILES 643 Fig. 6. Output spectrum after the digital-channel filters (UMTS). means of the behavioral model, which has already been mentioned. Time synchronization for the despreading and descrambling processes after the channel filters are achieved manually and are fixed for the duration of the simulation. Hence, the rake correlator only has a single static finger and there is no need to include a searcher. While most of the simulations involve computing a BER, the first simulation result to be presented is of a more general interest. Fig. 6 shows the signal spectrum at the output of the digital-channel filters, when only AWGN is present at the receiver input. With the modulators temporarily bypassed, the spectrum gives a clear indication of the RRC frequency response of the digital filters which, with an impulse response truncated at a length of 24 chips, achieves a stopband rejection in excess of 55 db. This is sufficient for attenuating all relevant interferers. The hole seen in the center of the spectrum is caused by the ac coupling. In this case, the coupling element was a first-order, high-pass filter with a cutoff frequency of 100 khz. Its effect on the receiver is to degrade sensitivity by less than 0.5 db. With the modulators active, there is no visible change to the signal spectrum within the passband of the channel filter and the level outside the passband, while still apparent, is 25 db lower than the in-band signal power. Hence, this is good evidence of the effectiveness of the channel filter in attenuating the high-frequency quantization noise. The modulators increase the total receiver noise by less than 0.1 db, which is consistent with the earlier dynamic range prediction of 80.5 db. The sensitivity achieved by the receiver is indicated by the results plotted in Fig. 7. The two curves extending to the right of the figure are the results obtained without channel coding and for the two cases of with and without the modulators. As anticipated, the modulators have no significant impact on sensitivity, the BER of 0.1% being achieved at a power level of dbm. The two curves to the left represent the results with channel coding active and for the two cases of with and without the analog prefilters. They indicate that there is no degradation associated with adding the prefilters and that the receiver sensitivity is 119 dbm. By comparing the two sets of curves to the left and right, it can be deduced that the gain associated with the channel coding is 8.5 db (N.B. 9 db was the figure used for the receiver dimensioning). The results for the adjacent-channel interferer test are plotted in Fig. 8. Without channel coding and the modulators, the BER does not rise until the interferer power reaches 40 dbm, 12 db above the level required by the specification. Hence, the channel filters clearly have adequate selectivity for this test. When the modulator is present but with the prefilter still absent, the rise at 45 dbm is due to an overdrive condition of the modulator. As this level is still within the specification, it is not of any real consequence and confirms the dimensioning of the modulators in coping with signals up to approximately 44 dbm. Adding the prefilter increases the performance margin a little but, interestingly, adding channel coding is of virtually no help (N.B. channel coding is known to be of no help when the BER is already high). Results for the 15-MHz blocking-interferer test are plotted in Fig. 9. It must be noted here that the wanted signal for the test is only 3 db above the reference sensitivity of 117 dbm and, therefore, in the absence of channel coding the receiver noise prevents the BER from falling to zero. Hence, all three curves obtained without coding are asymptotic to a BER of 2%. Despite this, the result obtained without the modulators confirms the effectiveness of the channel filtering and when the prefilter and modulators are added the overdrive of the modulators does not occur until the interferer reaches 40 dbm. The attenuation provided by the prefilter appears to be in the region of 6 db,

8 644 IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY, VOL. 52, NO. 3, MAY 2003 Fig. 7. System simulations for receiver sensitivity (UMTS). Fig. 8. System simulations for adjacent channel interferer (UMTS). which is consistent with its cutoff frequency of 8.5 MHz. With channel coding, the receiver passes the test with a 5-dB margin. V. NEW ARCHITECTURE FOR GSM MODE For operation in GSM mode, the same basic principle of using a single down-conversion and digitizing as soon as possible applies, as applied to the UMTS mode. However, as a relatively narrow-band system, which does not use spread-spectrum techniques, GSM is not well suited to the zero IF solution. As previously explained, dc offsets from the mixers or a hole in the middle of the signal spectrum caused by ac coupling will usually cause unacceptable damage to the modulation. There are one or two GSM handset products based on a zero IF receiver architecture that are beginning to appear on the market [10], but they are the result of taking extreme care with the cancellation of dc offsets. The hardware and software overheads associated with the dc-offset cancellation are not insignificant. The low IF or near-zero IF receiver [11] is a concept introduced specifically to overcome the dc-offset problems with the zero IF architecture. By mixing the wanted signal down to a low IF of half the channel spacing (i.e., 100 khz for GSM) instead of zero, the hole caused by ac coupling is moved to the lower side of the signal spectrum, where it is much less damaging. There is the complication of requiring a complex channel filter instead of the simple lowpass filters of the zero IF receiver, but the analog solution described in [11] has proven to be very successful. A low IF GSM receiver will invariably have a better performance than a zero IF type, especially in a hostile interference environment. With the reuse of common hardware in mind, it is interesting to contemplate how the receiver of Fig. 2 could be made to operate for GSM. Clearly, if the zero IF were to be retained, minimal structural changes would be required in the IF chain, the only significant changes being to the dynamic range and bandwidth requirements of the ADCs and digital filters.

9 MINNIS AND MOORE: HIGHLY DIGITIZED MULTIMODE RECEIVER ARCHITECTURE FOR 3G MOBILES 645 Fig. 9. System simulations for 15-MHz blocking interferer (UMTS). Fig. 10. New architecture configuration for GSM mode. However, for the purposes of this study, this is not considered an acceptable option. To set up a low IF, the local oscillator (LO) has to be offset from the center frequency of the wanted signal by 100 khz. Once created, the main impact of the low IF would then be on the ADCs and digital filters, both of which should ideally become complex devices. This would ensure that the quantization noise spectrum from the ADCs and the frequency response of the digital filters were together aligned with the center frequency of the wanted signal. If this were not the case, there would be a heavy loss in ADC conversion efficiency and a corresponding increase in power consumption. However, making these devices complex is not an entirely attractive option. It quadruples the hardware resources required for the digital filters and increases what is already a difficult design problem for the modulators. In the receiver configuration shown in Fig. 10, the need for a complex ADC is avoided by a novel variation in the IF signal processing. Instead of processing both the and components of the low IF output from the front end, the component is discarded and only the component is passed to a single modulator. The effect of this is to make the spectrum of the now-real IF signal symmetrical about zero, as if the IF were itself zero. Hence, the spectrum is naturally aligned with that of the quantization noise spectrum of the modulator. It is

10 646 IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY, VOL. 52, NO. 3, MAY 2003 Fig. 11. Calculating noise figure for GSM mode. then relatively easy to make the IF signal complex once again, by performing the equivalent of a Hilbert transform in the digital-channel filters that follow. The last step before equalization and demodulation is to derotate the signal by 100 khz in establishing a final IF of zero. An obvious consequence of processing only the component of the IF signal is a loss of image rejection. Any interferer present in the lower adjacent channel will be folded over about zero and will become indistinguishable from the wanted signal. For slightly different reasons, it is also necessary to attenuate an interferer in the lower alternate channel because when this signal is folded about zero it falls into what is effectively the adjacent channel on the upper side of the wanted signal. Fortunately, both these problems are easily overcome by filtering the frontend output with a simple polyphase filter. Except for interstage buffers, the filter is passive and therefore consumes negligible dc power. As shown, the system of Fig. 10 uses no AGC and, despite the presence of the polyphase filter, the vast majority of the channel selectivity is implemented in the digital domain. The dc offsets from the mixers are removed by ac couplings, whose highpass characteristics have a noncritical cutoff frequency in the region of 10 khz. The use of a single modulator results in a useful saving in power consumption. It is essentially the same modulator as used for the UMTS mode, although its loop filter and clock speed need to change to suit the particular bandwidth and dynamic range requirements of GSM. The combined channel and make-complex filters use the same physical FIR structures as used for the UMTS mode, but with a different set of coefficients. A. Receiver Dimensions For the noise figure calculation in GSM mode, the logical starting point is to establish the SNR requirement at the demodulator of a pseudo-ideal receiver, which gives an 8% BER in a TU50 propagation channel. It is convenient to do this by system simulation, for a receiver that includes a channel equalizer and has no imperfections except for the introduction of AWGN at its input. The obtained from such a simulation is 5.2 db and when a correction factor of 1.32 db is applied to take account of the ratio of the bit rate to the channel bandwidth (i.e., /200), the SNR requirement (SNR ) becomes 6.5 db. Hence, as illustrated in Fig. 11, the total noise power at the input to the receiver under these conditions must be dbm if the wanted signal power is 108 dbm, i.e., dbm (7) If this is compared with the thermal noise level raised by 53 db to account for the 200-kHz bandwidth, the overall receiver noise figure must then be db (8) The front end alone needs a noise figure slightly less than this to allow for the noise contribution of the modulator ADC. Assuming the referred noise from the ADC is approximately 10 db below the frontend noise, the degradation in noise figure will be 0.5 db and, therefore, the noise figure of the front end should be nearer to 6.0 db. If 2.5 db of losses are also to be tolerated in the RF filters, the active part of the front end needs a noise figure as low as 3.5 db. As this is lower than the value required for UMTS, it is clear that the GSM mode has the dominant influence on the circuit design of the dual-mode receiver front end. The adjacent- and alternate-channel rejection requirements of the receiver are illustrated by the curves plotted in Fig. 12. These represent the spectral envelopes of a wanted signal, a co, adjacent-, and an alternate-channel interferer at the relative frequencies and levels stipulated in the specification. For the tests in question, the wanted signal is at a relatively high level of 82 dbm and, therefore, the receiver noise can be ignored. Given that the receiver can achieve a BER of 8% in a TU50 propagation channel with an SNR of 6.5 db, it should have no difficulty in meeting the cochannel rejection requirement of 9dB.

11 MINNIS AND MOORE: HIGHLY DIGITIZED MULTIMODE RECEIVER ARCHITECTURE FOR 3G MOBILES 647 Fig. 12. Illustrating channel filter rejection requirements (GSM). Then, on the basis that an adjacent-channel interferer at a level 9 db above the wanted signal must be attenuated to the level of a cochannel interferer, the adjacent-channel rejection requirement must be at least 18 db. Similarly, the alternate-channel rejection requirement must be in the order of 50 db. On the upper side of the wanted signal, these levels of rejection are provided easily by the digital-channel filter. However, on the lower side, the 18 db of attenuation for the adjacent channel must be provided by the passive-polyphase filter. Of the 50 db of attenuation needed in the lower alternate channel, at least 32 db must be provided by the polyphase filter if the previously mentioned problem of spectral folding into the upper adjacent channel is to be avoided. Of the different blocking signals, the one with a 3-MHz offset at a level of 23 dbm ( ) is generally regarded as the most demanding. Under the relevant test conditions, the wanted signal is at a level of 99 dbm and if the required SNR of 6.5 db is to be achieved, the residue of the blocking signal after filtering must be no higher than dbm. At the level of 115 dbm, the noise power of the front end can largely be ignored and the rejection requirement for the blocking interferer,, is then simply SNR db (9) As in the case of UMTS, the dynamic range requirement of the ADC is determined by the level of the largest blocking interferer to reach the ADC and by the level of the quantization noise the ADC is allowed to generate. Hence, the difference between the 23 dbm level of the 3-MHz blocking signal and the 125 dbm level of the ADC noise (Fig. 11) gives a dynamic range requirement of 102 db. Although substantial, this is known to be within the capability of the current state of the art in modulator design. The requirement is also not quite so severe if the signal-to-noise-and-distortion ratio (SINAD) of the ADC is taken into consideration, which, for the purposes of passing the blocking-interferer test, is a lower value of 85.5 db. It is derived in much the same way as the filtering requirement for the blocking signal, the extra 3 db reflecting the fact that both the ADC noise and the blocking signal will contribute toward the noise residue of dbm referred to above. B. Polyphase Image-Rejection Filter Passive polyphase filters were studied some time ago by Gingell [12] and take the form shown in Fig. 13. They are a cascade of RC sections, each one of which is capable of creating a transmission zero at a frequency such that. Whether the zero is at a positive or negative frequency will depend upon the relative polarities of the and components of the input voltage. If each section were to be treated in isolation and driven by a pair of voltage sources, the frequency of the transmission zero would uniquely define the whole of the frequency response and the impedance of the section would be of no consequence. However, because of the loading effect of each successive section on its preceding neighbor, the overall frequency response is affected by the relative impedances. This substantially complicates the synthesis process and although the impedance of the sections should generally increase in the direction of the output to minimize the loading effects, the design procedure usually involves choosing the transmission zeros to give the desired stopband response and adjusting the impedances in a process of trial and error to achieve the desired passband response. The ideal passband response is generally one that is as flat as possible in the region of the wanted signal. In order to attain an attenuation of at least 30 db over the approximate band 400 khz to 0, a three-section filter was needed, in which the transmission zeros are set at the frequencies 375, 173, and 80 khz while the corresponding resistor values are 1, 2, and 4 k. This produces the frequency response shown in Fig. 14, in which the stopband requirement is fulfilled

12 648 IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY, VOL. 52, NO. 3, MAY 2003 Fig. 13. Passive polyphase filter network. Fig. 14. Frequency response of a passive polyphase filter. over the band 400 to 60 khz and the response is flat for positive frequencies between about 30 khz and 1 MHz. Difficulties with physical realization and with group delay variation prevent the transmission zero at 80 khz being moved closer to zero, but the lack of rejection in this region has no significant impact on the ability of the network to reject an adjacent-channel interferer. In any case, the ac coupling elements elsewhere in the receiver chain will force a transmission zero at dc. In the practical implementation, the polyphase filter will incorporate interstage buffer amplification to help reduce the loading effects of successive stages and to render insignificant the thermal noise generated by its resistors. C. Sigma-Delta Modulator ADC For operation in the GSM mode, the basic objective is to use the same modulator ADC as used for UMTS, but to scale

13 MINNIS AND MOORE: HIGHLY DIGITIZED MULTIMODE RECEIVER ARCHITECTURE FOR 3G MOBILES 649 Fig. 15. Digital make-complex and channel filter arrangement (GSM). down both the bandwidth of its loop filter and the frequency of the clock. However, if this is attempted with the fourth-order modulator already described, even with a relatively high clock speed of 26 MHz (i.e., 96 the bit rate), it is not possible to achieve the very large dynamic range requirement of 102 db. Hence, an alternative fifth-order modulator has subsequently been investigated with a 2-level, instead of a 3-level, output. Not only does this meet the dynamic range requirement with the 26-MHz clock, but its 2-level output results in much better loop stability when the modulator is under very low or very high drive conditions. It can be scaled to operate very effectively in the UMTS mode as well and, therefore, has become the preferred choice for use in the dual-mode receiver. All the subsequent system simulations for the GSM mode have incorporated this fifth-order modulator. D. Make-Complex Channel Filter As previously stated, the output of the single modulator in GSM mode must be made complex once again, which could be accomplished with a pair of FIR filters that perform the equivalent of a Hilbert transform [13]. A Hilbert transform of a real function in time is given by (10) where has exactly the same amplitude frequency spectrum as, but a phase spectrum that is shifted by 90 for positive frequencies and 90 for negative frequencies. Ignoring any difficulties with a direct, mathematical implementation of this transform, the need to incorporate channel filtering at the same time provides a strong case for combining these two functions into a single pair of FIR filters. The basic filter combination required is illustrated by Fig. 15, in which the FIR filter in the signal path has a lowpass amplitude response and the FIR filter in the signal path has an identical amplitude response except for the presence of a hole at dc. The width of the hole is determined by the sampling rate and by the length of the impulse responses of the filters. The phase characteristic for the component is, in this case, linear and has a slope determined by the delay of the filter. The phase characteristic of the component is identical except for the step discontinuity in the middle. Both filters must have the same delay. The frequency response plotted in Fig. 16 was obtained by first synthesizing a lowpass response of an appropriate shape and then simply translating its frequency by 100 khz. The two respective impulse responses for the and devices were then calculated using an inverse, discrete Fourier transform. The delay of the filter is 18.2 s, which is equivalent to 475 samples at a sampling frequency of 26 MHz. As shown in Fig. 16, the filter is substantially more selective than the attenuation template would suggest is necessary, but the extra selectivity and deep stopband floor are essential to attenuate the quantization noise generated by the modulator. The filter decimates directly to the bit rate, as no oversampling is used in the equalizer. E. System Simulations The behavioral model used for the GSM simulations has the same basic structure as shown in the diagram of Fig. 10 except that, as in the UMTS simulations, the front end is only implemented in terms of its AWGN. Hence, the input signal comprises a wanted GMSK signal centered on an IF of 100 khz, accompanied by an interfering signal, either modulated or continuous wave CW and offset from the wanted signal by the appropriate interval. Before entry into the receiver, both wanted and interfering signals are subjected to independent fading as required by the particular test being simulated. All filters of the system are modeled as FIR devices, including the ac couplings whose cutoff frequency is 10 khz. The gain of the amplifier shown at the input to the polyphase filter has a fixed value of 16 db, which, when the 4-dB gain of the polyphase filter and the 3-dB loss associated with dropping the channel are added, maps the maximum input level of a blocking signal at 23 dbm onto the 6 dbm maximum drive level of the single modulator. The frequency shift back to a zero IF after the digital-channel filters is accomplished with a perfect complex derotation by 100 khz and the equalization at the end of the receiver chain uses a

14 650 IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY, VOL. 52, NO. 3, MAY 2003 Fig. 16. Frequency response of digital filter (GSM). Fig. 17. Output spectra from fifth-order sigma-delta modulator and digital filters. Viterbi algorithm. All BER calculations are based on a comparison of physical (not coded) bits at the bit rate of kb/s. In an initial simulation of particular interest, the frequency spectrum at the output of the modulator is examined when a pure tone of 100 khz is injected at the receiver input. In this case, the power in the tone is 23 dbm and the AWGN at the front end is temporarily removed. As shown in Fig. 17, the tone is clearly present on both sides of the spectrum, as is to be expected with only the component of the IF signal represented. Its power level is 6 dbm as required, the lower indication in the figure resulting from the effects of the Hanning weighting being applied prior to performing the point fast Fourier transform (FFT). The spectrum of the quantization noise generated by the modulator is also symmetrical about zero, the hole in the center being approximately 400 khz wide. This was produced by the fifth-order modulator previously mentioned, which has two nonzero transmission poles in its loop filter at frequencies of 130 and 210 khz. With a clock speed of 26 MHz, the modulator achieves a dynamic range due to quantization noise in the region of 100 db. The second curve plotted in Fig. 17 shows the spectrum of the same signal after it has passed through the pair of digital-channel filters. Not only has the pair of filters eliminated the majority of the quantization noise, but it has also made the signal complex once more, as evidenced by

15 MINNIS AND MOORE: HIGHLY DIGITIZED MULTIMODE RECEIVER ARCHITECTURE FOR 3G MOBILES 651 Fig. 18. System simulations for receiver sensitivity (GSM). Fig. 19. System simulations for selectivity (GSM). the different levels of the tones now seen on either side of the spectrum. The tone on the right at 100 khz is unchanged in magnitude, but that on the left at 100 khz has been attenuated by approximately 70 db. This is the effective image-rejection ratio of the make-complex filter function. A simulation of receiver sensitivity for the GSM mode with a TU50 propagation channel yields the results plotted in Fig. 18. As shown, without the modulator present, the BER falls through a value of 8% for an input signal power of dbm and continues to fall toward zero at an input power of 82 dbm. It remains zero for all higher input powers since without the modulator the receiver is perfectly linear. With the modulator present, the degradation in receiver sensitivity for a BER of 8% is less than 0.5 db, confirming that the quantization noise power generated by the modulator must be below 125 dbm. Hence, in terms of sensitivity, the receiver achieves the target performance of 108 dbm. At higher signal levels, the modulator appears to cause some minor degradation in BER for input powers in the region of 80 dbm. This effect is believed to be linked to the nonlinear behavior of the channel equalizer for very low BERs, rather than just a simple loss of SNR. In any case, it is of little consequence. At still higher power levels, the BER is substantially zero until it rises sharply at an input power of 20 dbm. The rise in BER is caused by an overdrive of the modulator. As the receiver must operate with a maximum input signal level of 15 dbm (static channel), this rise in BER is slightly premature. However, there is some doubt over the accuracy of the behavioral model used for the modulator when operating under such large-signal conditions and results obtained in practice suggest that a real receiver is more likely to meet this particular performance requirement. Fig. 19 illustrates the selectivity performance of the receiver in dealing with co, adjacent-, and alternate-channel interferers. In each case, the BER for a TU50 propagation channel is

16 652 IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY, VOL. 52, NO. 3, MAY 2003 Fig. 20. New dual-mode receiver architecture for UMTS and GSM. plotted against the relative level of the interferer with respect to the wanted signal, the wanted signal itself being at a level of 82 dbm. For the cochannel interferer, the receiver passes the specification by a margin of 1.5 db, confirming that the passband of the channel filters is well chosen and not unduly narrow. In the presence of the adjacent-channel interferers, the receiver passes the specification by a good margin of approximately 6 db, the rejection of the interferer on the lower side being due largely to the action of the polyphase filter and that on the upper side largely to the digital-channel filters. As far as the alternate-channel interferers are concerned, the rise in BER at a relative level of 55 db is caused by an overdrive of the modulator, but this is of no consequence as there is already a very substantial performance margin of 14 db. VI. MULTIPLE MODES By merging the two receiver configurations of Figs. 2 and 10, the dual-mode receiver architecture takes the form shown in Fig. 20. There is a design issue associated with the RF parts of the receiver in coping with the multiple frequency bands that apply to the different modes, which has not been addressed by this study. However, as shown by the dotted outlines in the figure, most of the other functional blocks of the receiver are now being reused. Even some of the baseband processing for the two modes shown separated in the figure could take place on a common digital signal processor (DSP) core. After down conversion to either a zero or low IF, depending on the mode, the ac couplings have a cutoff frequency of 10 khz to suit GSM and the lowpass prefilters have a cutoff frequency of 8.5 MHz to suit UMTS. Neither requires any modification when changing modes. An extra gain step needs to be added to the IF preamplifiers for the GSM mode to ensure that the different dynamic range of the IF signals matches that of the modulators. In the case of the image-rejection filter, this is only required for the GSM mode and is preferably bypassed for UMTS. However, as implied in Fig. 20, it could be left in place for UMTS with relatively little adverse effect on sensitivity. Both modulators are active in UMTS mode and clocked at a frequency of MHz. Based on previous studies, these are expected to be fifth-order devices with a two-level output, each one feeding its own digital FIR filter with an RRC frequency response. When operating in the GSM mode, only one of the modulators is active, the other being shut down to save power consumption. The active modulator is electronically reconfigured to reduce the bandwidth of its loop filter and to change the clock frequency to 26 MHz. Its output is then fed to both digital filters, whose frequency responses are also changed to implement the make-complex and channel-filtering requirements of GSM. VII. CONCLUSION This paper has described the basic concept of a dual-mode receiver for use in future 3G cellular handset products. It has considered the performance requirements of the UMTS and GSM modes and has shown how these relate to the dimensions that must be assigned to the various functional parts of the receiver. Some of the most important functional parts have been described in some detail, such as the modulator ADCs, the analog prefilters, and the digital-channel filters. System simulations have been conducted, the results from which confirm that the basic concept is both feasible and will meet the target performance requirements that apply to the two modes. The basic principle has been to take a zero or low IF architecture and digitize as much of the IF signal chain as possible. This maximizes reuse of common functional parts and gives the receiver the potential to support several other radio

17 MINNIS AND MOORE: HIGHLY DIGITIZED MULTIMODE RECEIVER ARCHITECTURE FOR 3G MOBILES 653 standards beside UMTS and GSM. Work is now in progress to demonstrate the capability of the new concept in hardware. REFERENCES [1] [Online]. Available: [2] UE Radio Transmission and Reception (FDD), 3rd-Generation Partnership Project, TSG RAN WG4, 3GPP TS V3.7.0 ( )., [3] Spreading and Modulation (FDD), 3rd-Generation Partnership Project, TSG RAN WG1, 3GPP TS V3.6.0 ( ), [4] UTRA (BS) FDD; Radio Transmission and Reception, 3rd-Generation Partnership Project, TSG RAN WG4, 3GPP TS V3.7.0 ( ), [5] GSM: Digital Cellular Telecommunications System (Phase 2) Radio Transmission and Receptions (GSM 05.05), ETSI Secretariat, Sophia Anitpolis, Cedex, France, ETS , [6] B. Razavi, Design considerations for direct-conversion receivers, IEEE Trans. Circuits Syst. II, vol. 44, pp , June [7] S. Haykin, Digital Communications. New York: Wiley, [8] B. E. Boser and B. A. Wooley, Design of sigma-delta modulation analogue-to-digital converters, IEEE J. Solid-State Circuits, vol. 23, pp , Dec [9] J. C. Candy and G. C. Temes, Oversampling methods for A/D and D/A conversion, in Oversampling Delta-Sigma Data Converters, Theory, Design and Simulation. Piscataway, NJ: IEEE Press, 1991, pp [10] J. Brursztejn, GSM terminals, Elect. Commun., pp , 2nd Quarter [11] B. J. Minnis, P. A. Moore, A. W. Payne, A. C. Caswell, and M. E. Barnard, A low-if polyphase receiver for GSM using log-domain signal processing, in Proc. IEEE Radio Frequency Integrated Circuits (RFIC) 00 Symp., Boston, MA, June 11 13, 2000, pp [12] M. J. Gingell, Single sideband modulation using sequence asymmetric polyphase networks, Elect. Commun., vol. 48, no. 1 and 2, pp , [13] S. Haykin, Communication Systems, 2nd ed. New York: Wiley, Brian J. Minnis (SM 00) was born in Sheffield, U.K., in He received the B.Sc. (Honors) and Ph.D. degrees in electronics from the University of Kent, Canterbury, U.K., in 1973 and 1994, respectively. He joined Philips Research Laboratories in 1978 to work on the design of microwave systems and components. In 1996, he moved into the field of wireless communications and now, as a Research Fellow, leads a team of scientists studying the design of integrated transceivers for cellular and cordless radio applications. He has published approximately 30 papers covering various aspects of his work and a book on the subject of exact network synthesis applied to microwave circuit design. Dr. Minnis is a Fellow of the Institution of Electrical Engineers (IEE). Paul A. Moore was born in Swindon, U.K., in He received the B.Sc. (Eng.) degree (first class Honors) from Queen Mary College, University of London, U.K., in He joined Philips Research Laboratories in 1978 and initially worked on the theory and application of surface-acoustic wave (SAW) resonators in filters and oscillators. He has worked on the development of a number of highly integrated receiver solutions targeted at various different applications. He has been a Senior Principal Scientist since 1995 and is currently involved in the development of advanced transceiver architectures for cellular radio handsets. He is an active radio amateur, holding the call-sign G0OJA. He has published more than 20 papers and applied for more than 30 patent applications. Since 1981, his primary research interests have been in novel receiver architectures and high dynamic range integrated filter techniques. Mr. Moore is a Member of the Institution of Electrical Engineers (IEE).

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