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1 Agilent EEsof EDA This document is owned by Agilent Technologies, but is no longer kept current and may contain obsolete or inaccurate references. We regret any inconvenience this may cause. For the latest information on Agilent s line of EEsof electronic design automation (EDA) products and services, please go to:

2 RF SiP/Module Workshop Hands-on Labs RF SiP/Module Design Made Simple! Page 1

3 Workshop Objectives Provides an hand-on experience on RF SiP/Module design Provides an hand-on experience of ADS design tools and utilities in RF SiP/Module design Page 2

4 Agenda Electro-Magnetic Simulation Technologies Overview Stack-Up Designs Scalable Passive Model Development with AMC (Advanced Model Composer) Passive Component Characterization and Modeling Design Kits Multilayer Circuit Design 3D Interconnect Designs Page 3

5 Electro-Magnetic Simulation Technologies Overview Page 4

6 Why Electromagnetic Simulation? Solution are based on Maxwell s Equations It can account for: It can account for all Parasitic interactions Packaging effects Distributed nature of fields inside the structure High Frequency RF Designs / High Speed Digital designs It can simulate arbitrary geometric models It is not bounded by Analytical equation s accuracy limits Directly compatible with popular Mechanical CAD tools Page 5

7 Electromagnetic vs. Circuit Simulation EM Analyzes physical structure based on EM theory (Maxwell s Equations) Considers all coupling Passive components only Generally slower simulations Circuit Simulators Analyzes circuit schematic using built-in models Considers explicit coupling Passive & Active components Generally faster simulations 1 L= 10 mil W= 10 mil L= 15 mil W= 10 mil L= 120 mil W= 10 mil L= 15 mil W= 10 mil L= 10 mil W= 10 mil 3 S= 15 mil 2 L= 10 mil W= 10 mil L= 15 mil W= 10 mil L= 10 mil W= 10 mil 4 Page 6

8 EM Simulation Technologies Today Method of Moments (e.g. Agilent Momentum) Finite Element Method (e.g. Agilent EMDS) Finite Difference Time Domain (e.g Agilent AMDS) Page 7

2.5D / 3D-Planar Methods: Method of Moments This is the method for solving problems where the fields depend on 3 space dimension, while their sources (currents) are mainly confined planes with two

9 2.5D / 3D-Planar Methods: Method of Moments This is the method for solving problems where the fields depend on 3 space dimension, while their sources (currents) are mainly confined planes with two space dimensions Typical geometries which can be solved using MoM techniques are planar structures such as Microstrip circuits, Co-planar circuits, Patch antennas and General multi-layer structures that contain planar conductor pattern etc Page 8

category comprises all volumic full-wave general purpose formulations.

10 3D Methods: Finite Element and FDTD These are the methods for solving problems where both the field and source functions depend on three space dimensions This category comprises all volumic full-wave general purpose formulations. Most popular 3D solution methods are Finite Elements (Frequency Domain) and FDTD (Time Domain) Page 9

11 Momentum 3D-Planar Electromagnetic Simulator Physical Structure z Air multilayered medium 3D planar metallization H(r) E(r) ε, µ σ h 1 Layer [1] 1 1, 1 ε, µ σ h 2 Layer [2] 2 2, 2 Port 1 source ε, µ σ h 3 Layer [3] 3 3, 3 Gnd source ω load J s (r) Port 2 load [S] S-parameters Your Virtual Network Analyzer Page 10

12 Momentum 3D-Planar Electromagnetic Simulator Momentum simulation process: Substrate database generation Green function calculation Mesh generation B 1 (r) B 2 (r) B 3 (r) I 1 I 2 I 3 S 1 S 2 [Z].[I]=[V] [S] Adaptive frequency loop For every frequency: Matrix Load: calculate [Z] elements Square dense Computationally intensive Matrix Solve: [Z].[I] = [V] Direct and iterative solvers, support of machine optimized libraries Page 11

13 EMDS: 3D EM modeling using FEM EMDS (Electro-Magnetic Design System) Full 3D EM Frequency domain FEM Great cost-performance (starting from less than US$20k) Standalone package and integration into ADS Page 12

14 EMDS simulation capabilities Application of EMDS for design & verification: Arbitrarily 3D shaped structures Conductors, resistors, isotropic & anisotropic dielectrics, isotropic & anisotropic linear magnetic materials Unlimited number of ports and/or circuit sources Frequencies greater than zero Absorbing boundary condition (free space) To compute: Network parameters (S, Y, Z) Electric and Magnetic Fields Multi-Mode impedance & propagation constants Antenna parameters (gain, directivity, polarization ) Page 13

15 EMDS Technology Finite Element Method (FEM) Generate mesh of tetrahedrons Approximate electric field over each tetrahedron with a second-order polynomial containing unknown coefficients Solve resulting matrix to determine values for the polynomial coefficients Page 14

16 Comparing MoM and FEM Stable at DC MoM Strips, slots, and vias in infinite, planar dielectrics (3D planar) Full-wave and Quasi-static modes User controlled metal surface meshing with rectangular, triangular and polygon cells Dense matrix, compression techniques Simulation time: O(N 3 ) (direct), O(N 2 ) (iterative), O(NlogN) (iterative/compr.) Memory: O(N 2 ), O(NlogN) FEM Arbitrarily shaped 3D metals and dielectrics Full-wave mode Unstable at DC Adaptive tetrahedral (volumetric) mesh Sparse matrix Simulation time: square Memory: linear to square Page 15

17 Questions Q: What is the most efficient EM simulation technology for multilayer applications? A: 3D planar (Momentum) Q: What is the most efficient EM simulation technology for 3D interconnect designs? A: 3D full-wave (EMDS and AMDS) Page 16

18 Congratulations! You have successfully completed the EM Technology Overview workshop Page 17

19 Stack-Up Designs Source: Intel Page 18

20 Sample Stack-up Configuration Substrate Dupont 943 Green Tape TM LTCC Stack-up configuration 8 metallization layers 7 substrate layers, H=23.1 mil Conductor Thickness, T=0.35 mil Dielectric Constant, Er=7.4 Loss Tangent, Tan d= Conductivity Au : 4.521E7 S/m 23.1mil Ag : 6.301E7 S/m 1.7mil 4.5mil 1.7mil 4.5mil Au, 0.35mil Ag, 0.35mil Page 19

21 Sample Layout Layers Strip & Via Layers Metal Layers D01-L1C D05-L2C Pin Pad Layer GND Layer D03-L1V D07-L2V D10-L3V D14-L4V D18-L5V D20-L6V D22-L2V D08-L3C D12-L4C D16-L5C D19-L6C D21-L7C D23-L8C GND Layer Via Layers Page 20

22 ADS Stack-up Definition - 3 Steps 3 steps to define stack-up configuration with Momentum substrate definition dialog 1 Invoke the menu Define substrate layers 2 3 Define Strip & Via (layout) layers Page 21

23 Pre-Computation of Substrate Menu: Momentum (RF)>Substrate>Precompute SUBSTRATE GENERATION (Intel Core2 CPU 2GHz) Process size : 6.77 MB User Time : 0h10m59s Elapsed Time : 0h11m 4s Momentum RF with DC ~ 10GHz frequency range Page 22

Lab Exercise Substrate Stack-up Objective Creating a substrate stack-up definition for the stack-up configuration below Open the design, Lab_Stackup_design Read

24 Lab Exercise Substrate Stack-up Objective Creating a substrate stack-up definition for the stack-up configuration below Open the design, Lab_Stackup_design Read Lab_Stackup_design_layer.lay file with Options>Layer menu Define the stack-up as shown below (Metal: Perfect conductor, Via: 2D via) Save the stack-up as Lab_Multilayer_Stackup Page 23

25 Using Supplied Substrates 1 There are many precomputed substrate definitions for typical stack-ups in ADS Alumina RT Duroid PCB 2 Page 24

26 Using User-Defined Substrate Stack-up User-defined substrate stack-ups can be loaded by browsing.slm files 1 2 Page 25

27 Tips On Multi-Layered Vias Q: How do you define multilayer via stackup in Momentum? 1. By creating new via layers for multilayer vias Easy to place vias But there might be many via layers to create 2. By stacking individual via layers Only same number of via layers as substrate layers But difficult to stack vias for multi-layer and sometimes prone to errors Page 26

material type to Dielectric (Eps) Set Real value of Eps to 1 Then click Via to map the

28 Cavity Stack-Up Definition Use via layer to define dielectric bricks Example Spiral inductor w/ an air cavity Choose dielectric brick (air) layer for the layout layer Set material type to Dielectric (Eps) Set Real value of Eps to 1 Then click Via to map the dielectric brick to the substrate layers Cavity Note: This only works with EMDS for ADS not Momentum. Page 27

29 Lab Exercise Loading GT943 Stack-up Objective Loading the pre-defined GT943 stack-up for a design Open the layout design Lab_loading_stackup Select menu Momentum (RF)>Substrate>Open Find and load GT943_7Layers_Subst00_2Dv.slm Page 28

30 Congratulations! You have successfully completed the Stack-Up Designs workshop Page 29

31 Scalable Passive Model Development with AMC (Advanced Model Composer) Page 30

32 Advanced Model Composer (AMC) component : tee_s : symmetrical tee model is function of : substrate frequency range layout parameters W12 & W3 W12 W3 Momentum calculates S-data W12 W3 single frequency single W12, W3 freq W12 W3 continuous frequency single W12, W3 freq ADS Model Composer builds parameterized models for passive components continuous frequency range & discrete and/or continuously varying layout parameters W3 W3 W3 W12 freq W12 freq W12 freq continuous frequency discrete W12 discrete W3 continuous frequency discrete W12 continuous W3 continuous frequency continuous W12 continuous W3 Page 31

33 More On AMC AMC uses an adaptive rational/polynomial curve fitting algorithm, which is a multi-dimensional version of Momentum s Adaptive Frequency Sampling (AFS) algorithm. The.rat (=RATional) files generated by Momentum s AFS algorithm contain information about the rational fitting model of single Momentum simulations. There can be multiple.rat files in the model database for a single layout component. The AMC algorithms combine multiple.rat files into one global.pml (Passive Model Library) file. This file contains the multi-dimensional rational/polynomial model that is used to represent the S-data in the userdefined parameter/design space. Note Multiple.rat files that build up a.pml can be deleted. However, this is not necessary and may not be advisable as these.rat files can be re-used in a future AMC model generation. Page 32

Examples - Capacitor characterization with AMC 2

the area from 20x20 to 100x100 mil 2 Fast model

34 Examples - Capacitor characterization with AMC 2 Layers parallel plate series capacitor Vector Single perturbed parameter Variable=EdgeDistFromCenter (10~50mils) Results in the area from 20x20 to 100x100 mil 2 Fast model development time EdgeDistFromCenter 0h 2m19s with 512MB RAM and 2GHz processor PC Page 33

35 Comparison of AMC model vs. EM Simulation 50x50mil and 75x75mil parallel plates capacitors compared 50x50mil Excellent agreement Simulation speed improvement, over 70x AMC=0.89 sec Momentum=1min 4sec Once the model is calculated, AMC provides a fast and accurate model development solution AMC EM 75x75mil Page 34

Examples Helical Inductor 2-Layer Helical

slm with Perfect Conductor 2D Via Try new

36 Examples Helical Inductor 2-Layer Helical Inductor on the layer L3C and L4C Substrate Stack-up GT943_7Layers_Subst00_2Dv.slm with Perfect Conductor 2D Via Try new 3D Previewer with ADS 2006 Update2 Find it under EMDS menu pick 4.5mil 3D View 2D View Page 35

37 AMC Model Generation 3 Steps Step 1-A: Create Layout Component Parameters Only one perturbation parameter Center2Edge 4 edges will be perturbed by a single vector Type = Nominal/Perturbed 0.3mm 0.5mm Center2Edge Page 36

Select all vertices of right hand side Apply dx=0.

38 AMC Model Generation 3 Steps Step 1-B: Create Layout Component Parameters Click Edit/View Perturbation menu Set perturbation for all four directions Select all vertices of right hand side Apply dx=0.2 dy=0 to those vertices Repeat for other four sides Click OK to complete the edit dx=0.2mm Page 37

39 AMC Model Generation 3 Steps Step 2: Create Layout Component Menu: Momentum (RF)>Component>Create/Update It creates layout look-alike schematic symbol for schematic Library Browser Page 38

layout parameters Sweep Type: Continuous Range Min 0.25mm to Max 1.

40 AMC Model Generation 3 Steps Step 3: Generate AMC model Menu: Momentum (RF)>Component>Advanced Model Composer>Create Model Set layout parameters Sweep Type: Continuous Range Min 0.25mm to Max 1.2mm Then Apply and OK This will launch model generation process Page 39

41 Lab Exercise Creating AMC Models Objective Creating an AMC model for a given Helical Inductor Using the library browser to place the component in ADS schematic window Using 3D viewer to check the 3D drawing Open the design, Lab_creating_AMC_model Stack-up: GT943_7Layers_Subst00_2Dv.slm layer.lay: AMC_DK_GT943_7LAYERS_2Dv_layout.lay Check the 3D drawing with EMDS 3D viewer ( EMDS>3D EM Preview ) Create a model for the size from 0.5x0.5mm to 1.0x1.0mm Frequency 1 ~ 5GHz Once the model generation is finished, check the library browser if there are new three designs created Layout component, Momentum perturbed design, and work design Page 40

42 Congratulations! You have successfully completed the EM Technology Overview workshop Page 41

43 Passive Component Characterization and Modeling Page 42

p -Network Inductor Characterization p- network model parameter extraction by y-parameters Calculation of Q Converts 2-port S-parameter to 1-port S-parameter Calculates Q value from

44 p -Network Inductor Characterization p- network model parameter extraction by y-parameters Calculation of Q Converts 2-port S-parameter to 1-port S-parameter Calculates Q value from the 1-port S-parameter Imaginary (S11) Q = Real (S11) [ S ] Y1=y11+y21 Y2=y22+y12 Y3=-(y21+y12)/2 Calculation of effective L Effective Inductance Y3 L eff = Imaginary (Z11)? Y1 Y2 Page 43

45 ADS Measurement Equations for p -Network Inductor Model Use ADS measurement equations to extract p-network model parameters Initial Estimated Values Page 44

45GHz Model verification for 100MHz ~ 10GHz frequency range

46 Examples - L3C-L4C Helical Inductor Model Extraction Modeling Frequency Model verification for 100MHz ~ 10GHz frequency range Helical Inductor Size 0.6x0.6mm, where Center2Edge=0.3mm Calculated Model Parameters Page 45

47 Comparison Of Modeled vs. EM Phase(S21) Excellent agreement! S11 S22 Page 46

48 Characterization for L3C-L4C Helical Inductor Q-factor, Inductance, and SRF with Center2Edge=0.3mm Q-factor and Inductance with swept Center2Edge (0.3 ~ 0.8mm) Can get inductance and Qfactor vs size of Helical inductor m_length: ADS swept variable for Center2Edge Page 47

frequencies Helical inductor also has the biggest inductance value over others Meander shows a very

49 Comparison of Various Inductors* Q factor Helical Inductor has the best Q value over the frequency range of use However it is decreased faster due to the increased capacitance with higher frequencies Helical inductor also has the biggest inductance value over others Meander shows a very flat inductance over the frequency range of use L Q Inductance * Note: The length of inductors are same Page 48

Helical Inductors on A Different Layer Combination Inductors on thinner layers generally give larger inductance but show lower SRF due to increased

50 Helical Inductors on A Different Layer Combination Inductors on thinner layers generally give larger inductance but show lower SRF due to increased parasitics D01-L1C D05-L2C D08-L3C D12-L4C D16-L5C D19-L6C D21-L7C D23-L8C Q factor Inductance Inductance Lowered SRF for L4,5,6C Helical Inductors Page 49

51 Lab Exercise AMC Inductor Characterization Objective Creating a p-network model for Helical inductor Use the AMC model from previous lab Lab_creating_AMC_model Use ADS schematic design Lab_AMC_Pi_Model_Extraction to calculate p-network parameters Comparing modeled (p-network) vs. AMC model Build a schematic entry for the p-network using Lab_Pi_Model_Network Use Lab_Compare_Model_vs_AMC to compare the results S11 and S22 Page 50

52 Multilayer Inter-digital Capacitor Multilayer inter-digital capacitor on 3 layers, L3C, L4C, and L5C Capacitance area: 1mm x 1mm Characteristic 2.45GHz 3.7GHz 1mm 1mm Page 51

53 Swept Simulation of Multilayer Inter-digital Capacitor AMC Model Swept simulation of capacitor size Swept the size (m_length variable) from 0.05mm to 0.5mm This results in 0.1x0.1mm 2 ~ 1x1mm 2 capacitor 0.3x0.3mm gives ~400fF capacitance Page 52

54 Lab Exercise Objective Performing a swept simulation of AMC model for the size Ploting inductance and Q factor vs. swept parameter Use the Helical inductor from previous lab Lab_creating_AMC_model 0.5x0.5mm ~ 1.0x1.0mm Frequency 1 ~ 5GHz Open the design Lab_AMC_sweep Set the variable to m_length Simulate and plot the effective inductance and Q factor vs. inductor size Page 53

55 Broadband SPICE Page 54

56 Basic of the Broadband SPICE tool S-data S-data of passive components? equivalent circuit models. Flowchart of the tool Rational fit Passivity enforced? No A rational fit is performed on the input S- parameters The fitting procedure is based on the vector fitting algorithm (for more details: see *) The passivity enforcement step modifies the residues of the model in order to obtain a passive model. *: Rational Approximation of Frequency Domain Responses by Vector Fitting Bjørn Gustavsen and Adam Semlyen, IEEE Transactions on Power Delivery, Vol.14, No. 3, July Passivity enforcement Spice2 needed? S2Y transformation END Yes Yes No Page 55

Broadband Spice Broadband SPICE tool start-up: Menu (Schematic) Tools>Spice Model Generator>Start Broad Band Generator Steps: Choose input file type Dataset, Citifile, touchstone, Mom

57 Broadband Spice Broadband SPICE tool start-up: Menu (Schematic) Tools>Spice Model Generator>Start Broad Band Generator Steps: Choose input file type Dataset, Citifile, touchstone, Mom rational file (.rat) Browse input file with Browse button in Input dialog window Select output file type Choose output file name prefix Choose output directory or browse to select Page 56

58 Broad Band SPICE Model Generator Example Example Helical Spiral Inductor Page 57

59 Broad Band SPICE Model Generator Example Example Model Generation Page 58

60 Verification Simulation Setup o Double-click on the BBS2P item to bring up the Edit Parameter window. o Click on the Browse button next to File Name to browse the generated ADS network o Change files of type from.bbn to All Files (*.*) o Select the file ~networks/bbspiceds_heli_l03_l04_0_3m m_single.ckt o Then click on Open and OK. Page 59

61 Verification Results Excellent agreement! Page 60

62 Lab Exercise Broadband Spice Model Generation Objective Creating a broadband spice model for Helical inductor from the previous lab Page 61

63 Congratulations! You have successfully completed the Passive Component Characterization and Modeling workshop Page 62

64 ADS Design Kits Page 63

65 A Design Kit What is Design Kit? A kit typically created for each process and each CAD tool with the components and models by IC foundries However the design kit technology can be used for any other technologies to create a set of libraries ADS Design Kit Menu Page 64

66 Design Kit Installation 1. See what kits are installed DesignKit/List Design Kits Page 65

67 Design Kit Installation 2. Install Design Kit if the kit isn t installed DesignKit/Install Design Kits Unzip the design kit package that comes in a zip format Browse the design kit directory 3 Levels installation User Project Site Page 66

68 Lab Installation of NEC Design Kit File: NEC_mdl_kit_v1.5.zip NEC transistor library version update.asp File Location ~Workshop/NEC_mdl_kit_v1.5.zip Verify the design kit installation Page 67

69 Verify Design Kit Installation 1 Check if the design kit is installed and enabled 2 Check the palette in schematic Page 68

70 Creating AMC Design Kit (1) AMC models can be packaged into a design kit Menu Momentum (RF)>Component>Advanced Model Composer>Design Kit Steps 1. Open a AMC original design that would go into a design kit 2. Click the design kit menu 3. Work with Design kit dialog See next page Page 69

$HOME/hpeesof/amc/design_kit 2 3 Enter the component description Select

71 Creating AMC Design Kit (2) 1 Assign the name of component By default, AMC design kit is created under the directory $HOME/hpeesof/amc/design_kit 2 3 Enter the component description Select Model 4 Finish! Repeat these processes with all components that will go into the design kit. Page 70

72 Lab Exercise Installation of AMC Design Kit Objective Installing an AMC design kit Checking the installation with the library browser Copy amc directory (given by instructor) to $HOME/hpeesof Install the kit Check the installation Page 71

73 Congratulations! You have successfully completed the Design Kit workshop Page 72

74 Multilayer Circuit Design Page 73

75 Balun A Balun is a device that converts balanced impedance to unbalanced and vice versa Also Balun provides Impedance transformation Balanced to unbalanced transformation The word Balun is a contraction of balanced to unbalanced transformer Page 74

76 Transmission Line Balun Transmission Line Balun Each quarter wave length transmission lines can be represented by pi-type equivalent Therefore the transmission line balun can be transformed into a LC balun circuit Reference: Design Method of a Dual Band Balun and Divider 2002 IEEE MTT-S Digest Jung-Hyun Sung, Dal Ahn LC Equivalent Network Page 75

77 LC Balun Final Schematic High Pass Low Pass Resonance at f o Page 76

78 LC Balun Design at 2.44GHz Inductance = 4.58nH Capacitance = 0.928pF Page 77

79 Lab Exercise LC Balun Design Objective Designing a LC balun at 5GHz and find LC values Open the design Lab_LumpedPassiveEquiv_Balun Change wo value to 5GHz Simulate and plot the value of Lo and Co Page 78

80 LC Balun with AMC components Design the LC Balun with AMC components Inductor size: 0.295mm x 0.295mm = 4.58nH Capacitor size: 0.24mm x 0.24mm = 0.928pF Frequency: 1.8 ~ 3GHz de-tuned Page 79

81 Tuning AMC Design Use ADS tuning feature to tune the AMC design for a better performance The size of Inductor, 0.31mm, improves the performance of LC balun on loss and phase characteristic Page 80

82 Completed LC Balun ADS Layout Component Size 2.6mm x 2mm 6 land patterns 1 input and 2 outputs, 3 ground pins Component shapes are maintained but vias and some transmission lines are added to make proper connections 3D View Page 81

83 Simulation Result of Completed LC Balun Page 82

84 Lab Exercise Objective Designing the LC balun at 5GHz (from the previous lab) with the AMC design kit installed Use the AMC design kit installed from the previous lab Choose appropriate inductors and capacitors from the design kit Find the physical size of AMC components that meet L and C values for the design Simulate and check the performance Page 83

85 Congratulations! You have successfully completed the Multilayer Circuit Design workshop Page 84

86 3D Interconnect Designs Page 85

87 Bondwire Interconnects Simulation Most versatile and widely used microwave interconnect technique to connect ICs to ICs, ICs to circuits, and circuits to circuits. Alternative techniques such as BGA, top layer interconnect, etc can be high performance, but have high overhead to implement. Bondwires generally require full-wave 3D EM simulations Two options for 3D EM simulations EMDS stand-alone EMDS for ADS Bondwire Substrate 1 Substrate 2 Page 86

88 Bondwires in ADS Two bondwire shapes are available in ADS BONDW_Shape (Philips/TU Delft Bondwire Parameterized Shape) BONDW_Usershape (Philips/TU Delft Bondwire Model with User- Defined Shape) Page 87

89 Example Bondwire Simulation with EMDS for ADS Steps: 1. Create a bondwire shape in ADS schematic 2. Open a layout window from the schematic 3. Create the layout with bondwires The cavity represented by via in EMDS stack-up 4. Setup EMDS simulation and simulate Page 88

90 Lab Exercise Objective Simulating the bondwire interconnect with a different bond height, 75um Open the schematic design LAY_Bondwire_2Subst Change MaxH to 75um Open the layout Lab_Bondwire_2Subst Check the drawing with EMDS previewer Simulate the structure with EMDS>Simulation>S-Parameters Simulate and plot db(s11) and db(s22) Page 89

91 Congratulations! You have successfully completed the 3D Interconnect Designs workshop Page 90

92 For more information about Agilent EEsof EDA, visit: Agilent Updates Get the latest information on the products and applications you select. Agilent Direct Quickly choose and use your test equipment solutions with confidence. For more information on Agilent Technologies products, applications or services, please contact your local Agilent office. The complete list is available at: Americas Canada (877) Latin America United States (800) Asia Pacific Australia China Hong Kong India Japan 0120 (421) 345 Korea Malaysia Singapore Taiwan Thailand Europe & Middle East Austria Belgium 32 (0) Denmark Finland 358 (0) France * *0.125 /minute Germany ** **0.14 /minute Ireland Israel /544 Italy Netherlands 31 (0) Spain 34 (91) Sweden Switzerland United Kingdom 44 (0) Other European Countries: Revised: March 27, 2008 Product specifications and descriptions in this document subject to change without notice. Agilent Technologies, Inc. 2008

MMIC/RFIC Packaging Challenges Webcast (July 28, AM PST 12PM EST)

MMIC/RFIC Packaging Challenges Webcast ( 9AM PST 12PM EST) Board Package Chip HEESOO LEE Agilent EEsof 3DEM Technical Lead 1 Agenda 1. MMIC/RFIC packaging challenges 2. Design techniques and solutions