Agilent EEsof EDA.

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1 Agilent EEsof EDA This document is owned by Agilent Technologies, but is no longer kept current and may contain obsolete or inaccurate references. We regret any inconvenience this may cause. For the latest information on Agilent s line of EEsof electronic design automation (EDA) products and services, please go to:

3 22 DEVIE MODEING 2 P2 P3 P 2 s2 P2 s2 P3 s3 s s P 2 2 s3 P3 P3 2 s2 P2 2 s2 P3 s s BSIM4_NMOS MOSFET s3 s P 2 s2 P2 2 s2 P3 TIN T Z=5 Ohm s s P s3 P3 P3 Figure 2: Open, Short, Through, and DUT physical and schematic representations niques will be presented in the device modelling flow section. Some F device models require special etensions to the intrinsic device model, and modifications to the parameter etraction methodology Devices operating at GHz frequencies begin to see the effects of parasitics that normally do not impact the D behaviour. While many standard models offer some general F parameters, they may not fully address the device non-linearities or high-frequency behaviour. Device modelling engineers often have to add F etensions in the form of sub-circuits as well as customise the etraction routines. Device non-linearities are not adequately modelled Nonlinear models are typically etracted and verified using only linear data such as S-parameters. This data only includes small-signal information about the device at the ecitation frequency. It does not include information about harmonics being generated by the device under large-signal conditions. This can lead to inaccurate results when using the model in a nonlinear frequency domain (harmonic balance) simulation. At a minimum, nonlinear models should be verified by comparing nonlinear simulations to nonlinear measurement data. There are also new methods being proposed to etract certain model parameters directly from nonlinear measurement data, which will be discussed later in the article. Device modelling flow Accurate modelling begins with accurate measurements Essential to obtaining a good F model is the accuracy of the measurements. The data must reflect the measurement of the intrinsic device without the effects of the surrounding measurement environment. Firstly, the measurement system must be well calibrated before any measurement can be made. Several advanced calibration techniques have been developed over the years to effectively correct the system losses and bring the measurement reference plane up to the tip of the probes. The measurement data include parasitic effects of device pads and interconnects and must be de-embedded to remove the embedded parasitics. The pre-requisite for proper de-embedding is the availability of the dummy test structures, which include: OPEN, SHOT, THOUGH and DUT (device under test) as illustrated with equivalent circuit diagrams in Figure 2. A commonly used technique is de-embedding from the OPEN and verifying with THOUGH. This method removes the parallel circuit elements, which are critical to the low frequencies. The S-parameters of the device and the OPEN test structure are transformed into Y- parameters. The removal of the parallel circuits are performed as follows: Y DUT = Y total - Y open onvert Y- to S-parameters: S DUT = S(Y DUT ) The Y DUT -parameters are converted into the S-Parameters, which represent the de-embedded S-Parameters of the intrinsic device. The advantage of this method is that only the OPEN test structure besides the DUT is required. However, the OPEN de-embedding is good for lower frequencies up to approimately 5-0GHz, depending on the layout and the size of the test structures. A more accurate de-embedding is OPEN-SHOT, which methodically removes both the parallel and series circuit elements. First, the parallel circuit elements are removed from both the SHOT and the device test structures as follows: De-embed from OPEN: Y DUT /OPEN = Y total - Y OPEN Y SHOT /OPEN = Y SHOT - Y OPEN In the second step, the partially de-embedded Y-parameters are converted to Z- Microwave Engineering Europe December/January

4 DEVIE MODEING 23 parameters, which are used to subtract the influence of the series circuit elements as illustrated below. onvert Y- to Z-parameters: Z DUT /OPEN = Z(Y DUT /OPEN) Z SHOT /OPEN = Z(Y SHOT /OPEN) De-embed from SHOT: Z DUT = Z DUT /OPEN - Z SHOT /OPEN onvert from Z- to S-parameters: S DUT = S(Z DUT ) The fully de-embedded Z-parameters can be converted into the S-parameters, which represent the S-parameters of the intrinsic device. The final step is to verify the de-embedding results for both de-embedding methods with a THOUGH. If the device is properly de-embedded, the S-parameters of the THOUGH should represent the behaviour of a transmission line. The S and S 22 of the THOUGH should represent a physical characteristic impedance. With the measured S-parameters properly de-embedded, the data is ready to be used for etracting the model parameters that affect the device high-frequency behaviour. Direct etraction methodologies yield highly physical, highly accurate results Direct etraction means that the model parameter values are etracted from the physical equations of the compact model. There are several advantages to direct etraction. Firstly the model is more realistic because the parameters are etracted directly from a small set of relevant measured data instead of globally fitted to the entire data set. Secondly, etraction routines enable the direct etraction of model parameters from the equations of the intrinsic model, resulting in more physical parameter values. A good eample is to look at the threshold voltage model of a typical 0.8µm MOS process as a function of gate length, using the BSIM4 model. Purely using optimisation, one can achieve an agreement between the measured and simulated data as depicted in Figure 3(a). In this case, the model parameters acted as fitting parameters, which sometimes have no physical meaning to the device model. However, when the parameters (i.e. PE0, DVTP0, PEB, DVT0, DVT & DVT2) were first etracted from the measured data and followed by optimisation, the result, in Figure 3(b) shows a much better fit and the parameter values were very different. Accurate F model starts with an accurate D model Having an accurate D model parameter set is essential to obtaining a good F model. For eample, the starting points of the S 2 -parameters of a BSIM4 model are determined by the D model parameters. Figure 4(d) shows the magnitude of S 2 at the lowest frequency for different gate biases. The very good fit between measured data (red) and simulated curves (blue) can be achieved with an ecellent fit of the D behaviour, mainly the output drain current and the output resistance out: see Figures 4(a) and 4(b). The good fit of the S-parameters cannot be achieved without the correct starting point at the lowest frequency. This eample shows the importance of physically etracted D model parameters for further F modelling. ustomise intrinsic model and etraction methodologies for F model As discussed earlier, one of the challenges for F device modelling engineers is to be able to use the intrinsic model and enhance its F accuracy by adding high-frequency parasitics in the form of sub-circuits. That requires an open software environment such as Agilent Technologies Integrated ircuit haracterisation and Analysis Program (I-AP), which provides engineers with a fleible platform to create sub-circuit models Figure 3: Threshold voltage as a function of gate length for 8µm MOS shows good agreement between simulated and measured parameters, (a) globally optimised, and (b) directly etracted and optimised Vth_.m Vth_.s [E-3} Plot BSIM4_D_V_Etract/ength_Scaling/Vth low_vd/vth_des (On) Vth = f (des, low Vd Vth_.m Vth_.s [E-3} Plot BSIM4_D_V_Etract/ength_Scaling/Vth low_vd/vth_des (On) Vth = f (des, low Vd des [OG] Vth-scaling vs. channel lenght des [OG] Vth-scaling vs. channel lenght Microwave Engineering Europe December/January

5 24 DEVIE MODEING id.m id.s [E-3] 3.0 tout.m rout.s [E-3] vd [E+] vd [E+] S_deemb.M.2 S_deemb.S2 IMAG E EA [E+] mag (S_deemb.M.22 mag(s_deemb.s22) [E+e] Starting points of the S-parameter curve vd [E+] Figure 4: A good fit of the S-parameters (c), above, at the lowest frequency can be achieved with ecellent fit on the D drain current (a) and output resistance (b) and customised etraction routines using Parameter Etraction anguage (PE). PE is a BASI-like language that provides engineers the power to create everything from a single etraction routine to a full etraction methodology within I-AP. A sub-circuit model has been created in the I-AP BSIM3 modelling package by Advanced Modelling Solution to address the lack of an adequate F model in the intrinsic model. Important F parameters such as the gate resistance, the substrate resistance network, the overlap capacitance, and other eternal inductors, which are not incorporated in the intrinsic model, must be addressed for F model accuracy. For eample, the gate resistance significantly affects the input reflection coefficient, S. Similarly, the substrate resistance network has a significant contribution to the output reflection coefficient, S 22. The macro circuit model is added to the BSIM3 model as depicted in Figure 5. A good fit between the measured S and S 22 results were obtained as the result of the macro model implementation and the quality of the model using direct etraction methodology. It is also important to note that the eternal capacitors, the fringing capacitance between the gate and the drain/source, were necessary to achieve the good results for the forward and reverse transmission coefficients, S 2 and S 2. Etracted parameters to be optimised for better fit The first etraction of model parameters is usually followed by tuning and optimisation to give better fitting. Manual tuning of parameters enables the engineers to visualise the effects of certain parameters. Optimisation can also be in- Microwave Engineering Europe December/January

6 26 DEVIE MODEING S_deemb.M.22 S_deemb.S freq - - S_deemb.M.2 S_deemb.S.2 IMAG E EA [E-3] S_deemb.M. S_deemb.S freq - - S_deemb.M.2 S_deemb.S.2 IMAG E EA [E+] Saturated Power egion Output Power [dbm] Output Power [dbm] Output Power ompression region Input Power [dbm] Input Power [dbm] inear region (slope = small-signal gain) Amplitude Amplitude Input Power Harmonics Harmonics Figure 6: Gain compression and the generation of higher-order harmonics Microwave Engineering Europe December/January

Figure 5: BSIM3 subcircuit modelling of F parameters (shown on facing page) and plots of S-parameters (right) showing good model fit with measured data DEVIE MODEING 27 Port Drain drain fischersealed

7 Figure 5: BSIM3 subcircuit modelling of F parameters (shown on facing page) and plots of S-parameters (right) showing good model fit with measured data DEVIE MODEING 27 Port Drain drain fischersealed connectors IP68: Hermetically and pressure tight worldwide known speciality of fischer gd_et Diode Djsb_perim Diode Djsb_area sub2 Port Gate gate 4 gs_et MOSFET_NMOS BSIM3 sub3 sub Port Bulk Diode Djdb_perim Diode Djdb_area source Port Source voked to further fine-tuning of the etracted parameters. Using an optimisation tool such as the I-AP Plot Optimiser, the engineers can quickly select an optimiser from the very robust optimisation algorithms, the model parameters, and the region(s) of optimisation. For eample, if one would like to optimise certain critical regions on the plot, the plot optimiser allows the selection of multiple regions and automatically configures it in the optimisation strategy. Advanced nonlinear device modelling with harmonic balance simulation The real-world device characteristics are non-linear, meaning that the device will generate harmonics in addition to the stimulus signal. The contribution of the higher-order harmonics becomes important when the input power is significant, such as in high-power amplifier designs. Higher harmonics become apparent at signal compression level, i.e. db compression point, as illustrated in Figure 6. To model such device non-linearities, it requires accurate measurements of the amplitude and phase of the fundamental and harmonics of the incident and reflected waves or voltages and currents. This can be achieved with the use of a arge Signal Network Analyser (SNA) that can accurately measures the voltages and currents of a component under realistic conditions. Such a SNA was originally developed by Agilent Technologies and is now commercially available from Maury Microwave. The system can measure D, V, S-parameters and large signal characteristics of the DUT. The measured data can be converted in to I-AP data format and imported into the software, which can directly use Harmonic Balance simulation for advanced non-linear device modelling. Using Harmonic Balance simulation within I-AP, the model etracted from the S-parameters can be tuned and optimised toward the large signal measurements, as illustrated in Figure 7. The result presented here was realised by Agilent Technologies and NMDG Engineering. In this eample, the BSIM3 model parameters, N off and V offcv, were optimised. After optimising N off and V offcv, which have direct influence on the gate capacitance model, there is much better agreement between the measured and simulated output versus input power results for the fist, second and third harmonics. This demonstrates the real advantage of having a simulator working together with a device-modelling system to ensure that the etracted model is accurate in more advanced high-frequency circuit simulations. Modelling package The new version, I-AP 2004, builds on the highly open and fleible software architecture for advanced F device modelling with direct etraction methodologies for most industry models. I- AP users can take advantage of its open A sealed version of almost any standard connector Hermetically sealed (0-8 mbar l / s) and pressure tight for etreme environments and safety Meets and eceeds highest protection levels of IE60529, BS5490, DIN40050 Shell protecting sleeves and IP68 covers for mating faces available High performance O-ring seals made of VITON as standard Insulator-contacts sealed by 3 component glass epoy mail@ fischerconnectors.ch Swiss Headquarters Fischer onnectors SA H -43 Apples Tel Fa International Subsidiaries Asia Tel France Tel Germany Tel Italy Tel UK Tel USA Tel Infoard: Enter No: Online:

8 For more information about Agilent EEsof EDA, visit: Agilent Updates Get the latest information on the products and applications you select. Agilent Direct Quickly choose and use your test equipment solutions with confidence. For more information on Agilent Technologies products, applications or services, please contact your local Agilent office. The complete list is available at: Americas anada (877) atin America United States (800) Asia Pacific Australia hina Hong Kong India Japan 020 (42) 345 Korea Malaysia Singapore Taiwan Thailand Europe & Middle East Austria Belgium 32 (0) Denmark Finland 358 (0) France * *0.25 /minute Germany ** **0.4 /minute Ireland Israel /544 Italy Netherlands 3 (0) Spain 34 (9) Sweden Switzerland United Kingdom 44 (0) Other European ountries: evised: March 27, 2008 Product specifications and descriptions in this document subject to change without notice. Agilent Technologies, Inc. 2008

Agilent EEsof EDA.

Agilent EEsof EDA. Agilent EEsof EDA This document is owned by Agilent Technologies, but is no longer kept current and may contain obsolete or inaccurate references. We regret any inconvenience this may cause. For the latest