Design, Tuning and Testing of a Flexible PLL for Grid Synchronization of Three-Phase Power Converters

Transcription

1 Design, Tuning and Testing of a Flexible PLL for Grid Synchronization of Three- Jon Are Suul* Kjell Ljøkelsøy** Tore Undeland* *NORWEGIAN UNIVERSITY OF SCIENCE AND TECHNOLOGY, DEPARTMENT OF ELECTRICAL POWER ENGINEERING O. S. Bragstads Plass 2E, 749 Trondheim, Norway **SINTEF ENERGY RESEARCH, Sem Sælands vei, 7465 Trondheim, Norway Acknowledgements Tel.: Fax: jon.are.suul@elkraft.ntnu.no The work of SINTEF Energy Research in this paper is supported by Wärtsilä Norway. Keywords «Estimation technique»,«phase-locked Loop», «Tuning», «FPGA», «Real time processing» Abstract This paper is discussing a flexible three-phase Phase Locked Loop (PLL) with added functionality for grid voltage synchronization in a wide range of operating conditions. The presented structure is based on enhancing the well known Synchronous Reference Frame (SRF) PLL. Functions that modify the behaviour of the loop in order to handle large frequency and grid voltage deviations are also added. The PLL-structure is applicable for many applications with different control systems and different hardware, but is presented for grid synchronization of voltage source converters, with parts of the control system implemented in a Field Programmable Gate Array (FPGA). A simple tuning procedure based on analytical criteria has been developed and the system is analyzed in the frequency domain to verify the stability and illustrate the influence of the added functionality. Results from time-domain simulations and laboratory experiments are presented and discussed to verify the behaviour of the proposed PLL structure. Introduction Operation of actively controlled grid connected power electronic converters depends on information about the phase of the grid voltage, and the control system must be capable of tracking the grid voltage phase angle. Many different methods can be used for synchronizing to the grid, ranging from simple methods based on detection of zero-crossings of grid voltage to more advanced numerical processing of the grid voltage measurement []. The well established concept of Synchronous Reference Frame (SRF) or dq- PLL is inherently tracking both the grid voltage phase angle and the grid frequency, and the voltage amplitude can be calculated from the internal variables of the loop[]- [3]. The basic structure of an SRF PLL is quite simple and easily understandable, and the conceptual simplicity is especially obvious when the PLL is a part of a vector oriented control system. This paper is proposing and discussing a set of modifications to the basic SRF PLL that makes the gain of the loop independent of the grid voltage, and gives the PLL a wide operating range with improved frequency tracking performance. Controlled transition between open and closed loop operation during severe grid voltage disturbances and loss of grid voltage conditions is also obtained. The modified PLL structure can be suitable for general use in grid connected converters, and can also be adapted for Uninterruptible Power Supplies (UPS), micro-grids, or other applications where the EPE 29 - Barcelona ISBN: P.

2 connection to a larger grid can be lost. Even though only balanced three-phase conditions is treated in this paper, the main loop structure of the PLL is independent of the method for sequence separation, so most of the functionality in this paper can also be relevant for SRF PLL structures with positive sequence detection as for instance discussed in [4]-[8]. When implementing a PLL in a digital control system for a voltage source converter, the sampling rate might be quite low, as it is usually locked to the switching frequency. The signal delay and the discretization effects caused by the sampling might therefore influence the closed loop dynamics of the PLL in a non-negligible way. This has to be considered when tuning the parameters of the system and discrete time domain analysis of the control loop may be required. A simple way of selecting suitable parameter values for the software implementation, using a discrete time equivalent to the Symmetrical Optimum (SO) tuning criteria is therefore presented. [9], []. Parameter settings of the additional functionality described in this paper will also be discussed. Description of proposed PLL-structure The main loop of the PLL structure proposed in this paper is basically a traditional SRF-PLL. This concept has been extensively investigated in the literature, so the discussion is mainly focused on the functionality added to the system. The complexity of the system is increased, but the basic structure of the PLL is not changed and can be easily recognized. Figure shows a structural drawing of the proposed SRF-PLL where the main loop of the PLL is indicated with thick lines in the figure. The estimate of the grid voltage phase angle θ g,est is generated by a an integrator that acts as a voltage controlled oscillator (VCO) giving a saw-tooth signal that represents the angle of a continuously rotating vector. The measured grid voltages are transformed into a synchronously rotating dqreference frame by a Park-transformation using this estimated grid voltage phase angle. At balanced sinusoidal grid voltage, the resulting d- and q-axis voltages are DC signals. The grid voltage components are filtered by simple first order low-pass filters in order to attenuate noise and harmonics in the grid voltage. Higher order filters, notch filters, or sliding window filters for elimination of second harmonic oscillations in case of unbalanced voltages, or sequence separation techniques with inherent filtering properties could also be used [5], [7], [8], []. In the presented structure, the phase angle deviation, θ e,filt, given by the angle of the filtered grid voltage dq-components, is found by an arcus tangens operation implemented as an atan2 function to give ±8º operating range [2], [3]. By using the arcus-tangens function, the loop gain of the PLL is independent of the grid voltage amplitude, and there is no need for normalizing the voltage measurements to the amplitude of the grid voltage as indicated in [6] and [4]. The resulting phase angle is used as input signal to the PI-controller that governs the VCO by providing the frequency reference for the integrator. A special feature of the presented PLL is that a term representing the frequency difference between the input to the VCO and the grid is added to input of the PI-controller [3], [5]. This is found by differentiating the phase angle signal from the arctan-function, but the resulting signal must be low pass filtered in order limit high frequency noise introduced by the differentiation. The discontinuity that occurs if the phase signal passes ±8º is handled by simply subtracting whole revolutions from the difference signal before it is filtered, and a smooth frequency signal can therefore be obtained even from an unlocked loop. The resulting filtered signal f e,filt is multiplied with a gain K d and added to the phase angle signal before the sum is used as an input to the PI-controller. For small disturbances, adding the term depending on the filtered frequency difference has the same effect as a lead-lag block, improving the phase-response of the loop. Another modification to the PLL structure is the use of weighting factors to change the operating mode of the system [3]. If the grid voltage drops below a specified threshold value, an amplitude weighting factor W ampl is reduced linearly with the voltage from one, to zero when a lower voltage threshold is reached. This reduces the gain of the PLL to zero, leaving the feedback loop open. A complementary weight factor W lim governs an integrator discharge term which limits the steady state gain of the PI-controller. In normal operating conditions, W ampl is and W lim is zero, and the PLL is operating with infinite steady state gain and zero steady state phase error. At low grid voltages, the normal input signal to the PI-controller is attenuated while the integrator discharge term is engaged. This causes the controller output signal to go gradually towards zero, and the VCO to settle at its EPE 29 - Barcelona ISBN: P.2

3 PI-controller PI K p f f n f g VCO K VCO s g, est W f W ampl Ts i Microprocessor d dt Kd W lim K lim FPGA d dt V ampl T s f 2 Frequency error 2 f e, filt T s fd Td s e, filt arctan V q, filt V d, filt T s f T s f V q V d abc V abc nominal frequency. The effect of this is that the phase locked loop is converted into open loop phase angle generator when the grid voltage disappears, and is engaged again when the grid voltage returns. A rate-limiting function is applied to the weight factor in order to obtain a smooth and controllable transition from open-loop to normal operation. If the PLL is out of lock with a large frequency error, or is operating at low voltage as an open loop, the phase signal will pass ±8º. The phase difference feedback to the PI-controller is therefore softly suppressed when the frequency difference is large, to limit the influence of phase discontinuities at ±8º [3]. This is implemented by multiplying the phase angle signal by a weight factor, W f, generated from a look-up table based on the frequency difference, as shown in Fig. As long as the PLL is in normal operating conditions with small phase and frequency differences, the value of the weight factor is set to, but when the frequency difference is large, the phase difference signal is gradually disabled. This means that for large frequency differences, the loop can be converted to a frequency locked loop. The increase of the weight factor is controlled by a rate-limiter that gives a controlled transition from frequency to phase locking operation. In order to prevent the phase signal of passing ±8º with high gain in the loop, increase of the weight factor is stopped when the phase difference signal is outside a specified range. The functionality of the proposed PLL-structure can now be summarized by the following points: In normal operating conditions, the PLL is in lock and behave almost as a normal SRF-PLL. Using the arcus tangens-function to calculate the phase angle deviation ensures a wide lock-in range of the system and constant loop gain independent of grid voltage variations. The frequency difference between the grid and the PLL is found by differentiation of the phase angle deviation. By using this frequency difference as an additional input to the PI controller, the frequency tracking capability and the damping of the loop is improved. Weighting mechanisms is introduced to modify the behaviour of the PLL in case of low grid voltage or large frequency deviation. The voltage based weighting mechanism changes the PLL into an open loop phase angle generator, while the frequency based weighting mechanism changes the PLL into a frequency locked loop. PLL implementation Figure Continuous time equivalent diagram showing the proposed PLL structure The described PLL-structure is developed as a part of the control system for a grid connected voltage source converter. For laboratory experiments, the PLL is implemented on a processor board based on a ilinx Virtex F3T FPGA, with an embedded Power PC processor core, shown in Fig. 2 [6], [8]. The processor core in this system operates at 3 MHz while the FPGA fabric runs at MHz clock frequency. The FPGA is configured by using the ilinx Embedded Development Kit (EDK), which contains IP (Intellectual Property) modules for common functions as timers, internal RAM blocks, and various peripheral units. Necessary IP modules for angular transformation and filter functions were EPE 29 - Barcelona ISBN: P.3

4 UART FPGA RAM Processor core ADconverter IPmodule IPmodule Processor bus Figure 2 FPGA based processor board. developed by VHDL programming, and added to the processor system using EDK. Internal registers are made available through the processor bus, while discrete signals were connected directly between the IP-modules, as shown in Fig. 3. The FPGA building blocks are operating in parallel but can be connected in a pipeline structure, which gives the FPGA system very high signal processing speed [6]. The software loop runs at 5 khz sample frequency, while the FPGA functions operate at the AD converter sample rate of 4 MHz. This was easily achieved, although the main design focus was on achieving a flexible system with a simple and tidy structure. The presented PLL structure does not require the processing capability of the FPGA, but the high sampling frequency makes it possible to implement converter control methods that require high processing speed [2], [6], [7]. The high sampling rate of the FPGA also gives a high degree of over-sampling, which makes the low pass filters in the PLL capable of effectively suppressing high frequency noise. This ensures that aliasing of signal components close to multiples of the processor sampling frequency is suppressed. Switching ripple from neighbouring converters giving signal components close to the processor sampling frequency, or from converters operating with variable switching frequency, will therefore not cause problems in this system. To achieve a good compromise between flexibility and processing speed, most of the functionality of the PLL is handled by the processor, while time critical functions and functions handling AC signals are implemented as building blocks in the FPGA fabric. The parts of the PLL and the functions that are implemented in the FFGA are shown by the shaded area in Fig.. Frequency domain analysis and tuning of proposed PLL Figure 3 Structure of processor system. To facilitate the process of tuning the parameter values of the PLL, a linearized small signal model, as shown in Fig. 2, is used. This model is based on the assumption that the PLL is operating close to steady state and with small phase angle deviation. Then there is no influence from the weighting factors, and tan θ θ is an acceptable approximation. Due to the high sampling rate, the functions implemented in the FPGA can with good accuracy be represented as continuous time transfer functions. If the sampling rate of the microprocessor core is low compared to the time constant of the filters implemented in the FPGA, the discrete time nature of the system must however be taken into account for analysis and tuning of the system. The corner frequency of the filters implemented in the FPGA determines the dynamic performance of the PLL. Selecting the value of the filter time constant T f is therefore a good starting point for parameter tuning of the system. This value has to be selected as a trade-off between bandwidth of the PLL and attenuation of noise and grid voltage harmonics. The easiest way to tune the controller parameters of the PLL is to start by considering only the basic loop which consists of the PI controller, the VCO integrator and the low pass filters. Suitable parameters for a continuous time PI-controller, or a digital PI-controller with high sampling frequency, can be selected by the Symmetrical Optimum method (SO) [3], [9]-[2]. If the difference between the sampling period and the filter time constant is small, the sampling effects and the discrete nature of the controller implementation have to be taken into account. In that case, a discrete time equivalent to the symmetrical optimum tuning, as discussed in [9], [], can be used to select the parameters of the digital PI-controller. Parameters that give approximately symmetrical tuning, with maximum phase margin for a given crossover frequency can be calculated by (). These equations become equal to the EPE 29 - Barcelona ISBN: P.4

5 epll filt Td skd T s df K i p i Microprocessor FPGA T s f T s T s Figure 4 Small signal model of PLL. f VCO K VCO s normal equations for the continuous time symmetrical optimum when the sampling period of the microprocessor, T samp,µp, is small compared to the filter time constant, T f,pll. 2 Tsamp, P () Ti a Tf, PLL Kp c 2 Tsamp, P Tsamp, P akvco ( Tf ) a( Tf ) 2 2 The factor a, is a free design parameter that can be used to determine the crossover frequency, and by that the damping or the phase margin of the system. Some publications that report on robust PLL tuning use almost negligible measurement filtering and are selecting the value of a in the range of 3-35 to obtain a slow and stable PLL that is utilizing the inherent filtering properties of the low gain PIcontroller and the VCO [3], [2], [2], [2]. As the low-pass filters used in this implementation attenuates noise and harmonics, the gain of the PI-controller can be increased, and a suitable value of a, could be chosen in the range of 2-4. Selecting a = 2, which corresponds to a damping factor of.5 for a continuous time system, gives the PLL high bandwidth but results in quite large overshoot and oscillations in the time response. To obtain a system with critical damping, the value of a has to be increased to about 3. Since the addition of the frequency term described in this paper improves the phase margin of the system, a design with a = 2, is chosen as the starting point. A Bode-diagram with the frequency response of the system from Table, with parameters for the PIcontroller calculated from (), is shown in Fig. 6. The blue solid line shows the frequency response of a continuous time system without any effect of sampling action of the microprocessor. The asymptotic frequency response is also shown by dashed red lines. The black dashed lines show the frequency response when the system is considered as a discrete time system and the sampling frequency of the microprocessor is taken into account. The crossover frequency of the system is in this case reduced from 5 rad/s for the continuous case to 46 rad/s, while the phase margin is just slightly reduced compared to the continuous case since the crossover frequency is reduced to maintain a symmetric tuning. The influence of the sampling effect on the phase margin is clearly visible for the higher frequency range in the Bode-diagrams. This indicates that for a system with lower sampling frequency or for a faster system with a lower filter time constant, it will be even more important than in the presented case to use a discrete time equivalent of SO to maintain a symmetrical tuning and a reasonable phase margin. The transfer function that results from adding the term depending on the frequency difference to the phase error feedback signal is given by (2). It acts as a lead-lag block that can be utilized to increase the phase margin of the system. K d Td s Kd Td Tfd s h f (2) T s T s fd g Table PLL parameters for frequency domain analysis Filter time constant: T f ms Sampling time: T samp,µp 5 khz PI controller gain: K p 72.3 Hz/rad PI controller time constant: T i 4.4 ms Frequency term gain: K d,5 Frequency term filter: T fd ms The filtering time constant T fd gives the upper corner frequency of the lead-lag function, while the gain factor K d determines the lower corner frequency, given by T dl = K d T d +T fd. The frequency difference is found by pure differentiation, and the corresponding time constant is therefore fixed at T d = s. As differentiation of the phase angle difference magnifies high frequency noise, the amount of noise in the frequency signal gives a lower limit for the filtering time constant T fd, and also limits the gain factor K d. The maximum contribution to the amplitude and phase response from the lead-lag term occurs at the geometrical mean of the upper and lower corner frequencies, and the lead-lag function can be specified by the ratio between the corner frequencies given as b 2 = (K d T d +T fd )/T fd. A simple design approach is to place the lead-lag time constants symmetrically around the open loop crossover frequency of the PLL, resulting in the values of T fd and K d given by (3). To maintain the same crossover frequency of the PLL as given by (), the gain of the PI-controller is then reduced proportionally with the gain of the lead-lag block at the specified crossover frequency, as given by the fd EPE 29 - Barcelona ISBN: P.5

6 4 Bode Diagram Gm = 24.8 db (at 2.72e+3 rad/sec), Pm = 36.4 deg (at 46 rad/sec) 4 Bode Diagram Gm = 4.3 db (at 2.8e+3 rad/sec), Pm = 52.5 deg (at 972 rad/sec) 2 2 Magnitude (db) -2-4 Magnitude (db) Phase (deg) Frequency (rad/sec) Figure 5 Frequency response of PLL represented by continuous time transfer function and when including sampling effects Phase (deg) Frequency (rad/sec) Figure 6 Frequency response of PLL when the term depending on the frequency difference is included in the feedback loop expression for the new value of the PI-controller gain in (3). As long as there is not too much noise in the system, the parameter b can be chosen to be equal to a. a K 2 ' p T fd Tf Kd Td b Tfd Kp b b (3) The influence of the lead-lag function on the frequency response of the PLL with the parameters from Table is shown in Fig. 6. For this case, a small deviation between T fd. and T f, and between T i and K d T d +T fd is deliberately chosen in order to distinguish the time constants and to make the difference visible in the asymptotic bode plot of Fig. 6. The gain of the PI-controller is kept at the value found from (), in order to make the influence on the amplitude more visible in the figure. The frequency response of a standard continuous time PLL is shown by green dotted lines as a reference. The frequency response of the continuous time PLL with the frequency term is shown with blue solid lines while the corresponding asymptotic frequency response is shown by red dashed lines. The frequency response when taking the discrete time implementation into account is also shown in the figure by the black dashed lines. The Bode-plots show how the introduction of the frequency difference term improves the phase margin of the PLL, and also how the amplitude response is influenced. A simple tuning procedure for the PLL can now be summarized as: Select the filter time constant T f to attenuate noise and harmonics. Design the PI-controller by selecting a design factor a in range of 2-4 and calculate parameters for the PI-controller from (). Select the design factor b to be equal to a, and calculate the parameters for the frequency difference term and the modified PI-controller gain by using (3). The characteristics of the weighting factor mechanisms introduced into the loop must also be designed. The parameters used for these functions will however depend much on the application and what kind of purpose they should be designed to fulfil. One starting point can be to select the allowable range of frequency difference to be about 2 Hz, and then to linearly reduce the weight of the phase error to zero when the frequency difference is 3-5 times larger. For the weight factors depending on the voltage amplitude, it can be suitable to start reducing the weight factor W ampl when the voltage is below.2 pu, and to reduce it to zero when the grid voltage is below. pu. The ratio between the value of the integrator discharge factor K lim and the PI-controller integral time constant determines how quickly the VCO returns to the rated frequency when voltage is lost. This value should therefore depend on the tuning of the PI-controller, but a suitable starting point can be to set K lim to about.. The rise rate limit can be set to around 5 times T i. The Bode-plots in Fig. 8 show how the small signal behaviour of the loop changes for different values of the frequency, depending on the weight factor W f. The phase margin at the crossover frequency is increased as the phase feedback is reduced, and the loop is transformed into a frequency locked loop, so there is no risk for small signal instability. In a similar way, the curves in Fig 9 show how the frequency response changes when the voltage based weight factor W ampl is decreased and the PI- EPE 29 - Barcelona ISBN: P.6

7 Magnitude (db) 5 Bode Diagram Normal operation W f =.9 W f =.5 W f =. W f = - Frequency tracking Magnitude (db) 5-5 Normal operation W =. lim W =.5 lim W =.9 lim Bode Diagram W lim = - Open loop operation Phase (deg) Phase (deg) Frequency (rad/sec) Figure 7 Frequency response when the frequency based weight factor is reducing the feedback from the phase angle difference Frequency (rad/sec) Figure 8 Frequency response when the voltage based weight factor is reducing the gain of the PLL (K lim =.) controller is transformed into a lead-lag function during the transition to open loop operation. Although the phase margin is slightly reduced when the gain is reduced, the curves show that there is no risk for instability when the weighting mechanism based on voltage is activated. Verification by time-domain simulations and laboratory experiments The behaviour of the presented PLL structure is further investigated by time domain simulation and laboratory experiments. The time-domain simulations are carried out by PSCAD/EMTDC, and the simulation model is designed to include all the nonlinear and trigonometric functions of the PLL. The model also includes the sampling effect of the microprocessor. The parameters used for the simulations are given in Table 2, together with a set of parameters used for laboratory experiments with a slower PLL. Figure 9 shows three series of simulation results with different PLL configurations. The results in Fig. 9 a) are showing the response to a 3º phase shift in the grid voltage, while Fig. 9 b) gives the response to a simultaneous 5% voltage drop and 3º phase shift, and Fig 9 c) shows the response to a Hz step in the grid voltage from 5Hz to 6 Hz. In all these cases the weighting factors were disabled, by setting the thresholds outside the operating range. The following configurations are compared: A basic PLL structure using the q-axis voltage component as feedback to the PI-controller. A PLL with an arc-tan-function to generate the phase angle feedback to the PI-controller. A PLL with arc-tan and frequency difference term, without reduced PI controller gain. A PLL with arc-tan and frequency difference term, and parameters tuned according to the presented tuning procedure. The results in Fig. 9 show that there is little influence of the arc-tan-function when the PLL is exposed to grid voltage phase shifts and grid frequency variations. When the PLL is exposed to a voltage drop together with another disturbance, it can be clearly seen by comparing Fig. 9 a) and b) that the dynamics of the basic PLL changes significantly, while the PLLs with arc-tan-function are insensitive to changes in the grid voltage. The results in Fig. 9 also show the effect of adding the frequency difference term to the PLL, and how this term speeds up the frequency tracking while the damping of the response in the phase angle error is improved. If the frequency term is included without reducing the gain of the PI-controller, the total gain in the loop is increased, resulting in higher overshoot in the response. When the gain of the PI-controller is reduced, in order to keep the crossover frequency constant, the closed loop bandwidth of the PLL is slightly reduced, but the response both in phase error and frequency is well damped, as can be seen by the longer settling time for the phase error signal. The combined result of using the arctan-function and the frequency term is robustness against voltage variations, improved frequency tracking performance and a well damped response. Laboratory measurements verify that the practical implementation of the PLL obtains the same Table 2 Parameters used for simulation and laboratory experiments Parameters: T s T f T i K p T fd K d Example PLL,2 ms 5 ms 2,4 ms 5.6 (7.8) Hz/rad 5 ms.5 Slow PLL,2 ms 5ms 2 ms (.6).8 Hz/rad 5 ms.5 EPE 29 - Barcelona ISBN: P.7

8 and frequency term 5 and frequency term 3 and frequency term Estimated phase error [deg] 5-5 Estimated phase error [deg] 5-5 Estimated phase error [deg] Estimated frequency [Hz] and frequency term Estimated frequency [Hz] and frequency term Estimated frequency [Hz] and frequency term a) Simulation of 3º step in grid voltage phase angle b) Simulation of step in grid voltage from. to.5 pu, and 3 º step in phase angle c) Simulation of step in grid frequency from 5Hz to 6 Hz. Figure 9 Simulation results comparing the transient response of different PLL configurations and tunings performance as the time-domain simulations. The phase angle signal from the arc-tan function and the PI controller output signal were made available for oscilloscope measurements via a DA-converter on the processor board. A sinusoidal signal generated from the output phase angle from the PLL, was also made available for comparison with the input voltage signal. Fig. shows the response of the laboratory setup to a 3º phase shift in input signal. In this case the input signals were generated by a three-phase, electronically controlled signal source. Comparison of the measurements in Fig. with the simulation results in Fig. 9 a) shows that the response of the practical implementation replicates the simulation result with good accuracy. Figure shows the response to a real event in a 4V laboratory grid. A 55 kw resistive load is disconnected from an inductive grid with a grid inductance of approximately.7 pu referred to the this load. This figure shows a response similar to the response from the 3º phase shift in Fig., although with less amplitude in phase error and frequency. This is as expected, since the phase shift in this case is only about º. The three-phase inductance emulating the weak grid is slightly unbalanced, resulting in slightly unbalanced voltages, when the load is connected. This is seen by the small second harmonic ripple that is present when the system is fully loaded. The weighting mechanisms are considered most relevant for slow PLL structures, and hence the behaviour is illustrated with measurements on a PLL with the parameter set given in the last row of Table 2. For these experiments, an electronically controlled three-phase signal source with variable Figure Measured response to a 3º step in phase. ch: Input phase A, ch2: generated sinusoidal signal, ch3: Estimated frequency [2 Hz/div], ch4: arctan angle[5º/div] Figure Measured response to disconnection of passive load. ch: Input phase A, ch2: generated sinusoidal signal, ch3: Estimate frequency [ Hz/div], ch4: arctan angle[5º/div] EPE 29 - Barcelona ISBN: P.8

9 Figure 2 Abrupt engagement of phase locked loop. ch:amplitude weighting factor, ch2:frequency weighting factor ch3:vco frequency [5 Hz/div], ch4:arctan angle[5º/div] amplitude running at 55 Hz was used as the input to the PLL. The input voltage was initially set below the lower amplitude threshold of the voltage weighting mechanism, and this keeps the PLL in open loop mode at the nominal frequency. The frequency difference is seen by the 5 Hz saw-tooth waveform of the phase angle signal. For the results in Fig. 2, the frequency weighting mechanism is disabled, and there is no rate-limiter on the voltage weighting mechanism. When the signal amplitude is stepped up to. pu just before the arc-tan phase signal reaches 8º, a step in the frequency signal can be seen immediately because of the gain of the PI-controller. Since the PLL is not fast enough to lock on to the frequency and phase angle before the phase signal reaches 8º, the frequency signal makes a step down when the phase angle difference goes negative, before the PLL starts tracking the frequency and the phase angle in a normal way. Such a discontinuous response in the frequency can be unwanted, and the weighting mechanisms can be used to limit this influence on the loop. The effect of the weighting mechanisms and the rise rate limiters is illustrated by figure 3. In this figure it is shown how the amplitude weighting factor first rises gradually to %, allowing the PLL to start smoothly in frequency tracking mode without influence of discontinuities in the phase angle signal. The PLL operates in this mode until the frequency difference reaches the outer threshold of the frequency weighting mechanism, 3 Hz in this case, and the phase difference comes within the specified range of 45. Then the frequency based weighting factor is ramped up and the PLL starts locking on to the grid voltage phase angle. In this way, the frequency signal can be kept smooth and without sudden uncontrolled changes. It should be noted that there can be a challenge to achieve proper settings of the parameters for the frequency weighting mechanism, but the presented results illustrate how the behaviour of the loop can be shaped and adapted for different applications and requirements. Conclusion Figure 3 Gradual transition from open loop to phase tracking ch:amplitude weighting factor,ch2:frequency weighting factor ch3: VCO frequency [5 Hz/div], ch4: arctan angle[5º/div] A modified three-phase PLL structure implemented in the synchronously rotating dq-reference frame has been presented and discussed. The performance of the PLL is enhanced compared to the traditional implementation by the use of an arcus tangens-function to calculate the estimated phase error, making the performance independent of variations in the grid voltage. The PLL is further modified by adding a term based on the frequency difference in the feedback loop. This improves the frequency tracking performance of the PLL. Another modification is to include a set of weighting mechanisms that can change the operating mode of the PLL into a frequency tracking loop in case of large frequency deviations, or into open loop operation in case of loss of grid voltage. The presented PLL structure has been investigated by frequency domain analysis, and the influence of the digital implementation has been discussed. A discrete time equivalent to the Symmetrical Optimum tuning criteria has been applied to design the PI-controller of the PLL, while taking the sampling effects into account. On this basis, a general tuning procedure that can easily be applied for applications with different dynamic requirements has been proposed for selecting the main parameters EPE 29 - Barcelona ISBN: P.9

10 of the PLL. Frequency domain analysis also shows that the weighting mechanisms introduced to the PLL structure do not compromise the small signal stability of the loop. The functionality and the tuning, of the proposed PLL structure is verified by time-domain simulations in PSCAD/EMTDC and by laboratory measurements. The results from the practical implementation of the system are corresponding well with the theoretical analysis and the results from time-domain simulations. The presented PLL structure is generic and flexible, and can easily be adapted to different applications or different operating conditions by tuning the parameters according to the corresponding requirements. References [] A. V. Timbus, R. Teodorescu, F. Blaabjerg, M. Liserre, Synchronization Methods for Three Phase Distributed Power Generation Systems, An Overview and Evaluation, in Proceedings of the 36 th IEEE Power Electronics Specialists Conference, PESC 5, Recife, Brazil, 2-8 June 25 [2] S. K. Chung, Phase-locked loop for grid-connected three-phase power conversion systems, IEE Proceedings on Electric Power Applications, Vol. 47, No. 3, May 2 [3] V. Kaura, V. Blasko, Operation of a Phase Locked Loop System Under Distorted Utility Conditions, IEEE Transactions on Industry Applications, Vol 33, No., January/February 997 [4] P. Rodriguez, J. Pou, J. Bergas, J. I. Candela, R. P. Burgos, D. Boroyevich, Decoupled Double Synchronous Reference Frame PLL for Power Converters Control, IEEE Transactions on Power Electronics, Vol. 22, No. 2, March 27 [5] L. R. Limongi, B. C. Pica, F. Profumo, A. Tenconi, Analysis and Comparison of Phase Locked Loop Techniques for Grid Utility Applications, in Proceedings of the Power Conversion Conference Nagoya 27, PCC 7, Nagoya, Japan, 2-5. April 27 [6] H. Awad, J. Svensson, M. J. Bollen, Tuning Software Phase-Locked Loop for Series-Connected Converters, IEEE Transactions on Power Delivery, Vol 2, No., January 25 [7] A. Ghoshal, V. John, A Method to Improve PLL Performance Under Abnormal Grid Conditions, in Proceedings of the National Power Electronics Conference 27, Banaglore, India, 7-9 Dec. 27 [8] E. Robles, S. Ceballos, J. Pou, J. Zaragoza, I. Gabiola, Grid Synchronization Method Based on a Quasi- Ideal Low Pass Filter Stage and a Phase-Locked Loop, in Proceedings of IEEE Power Electronics Specialists Conference, PESC 28, 5-9 June 28, pp [9] L. Norum, Microprocessor applications in power electronics, PhD-Thesis, Norwegian Institute of Technology, NTH, Trondheim, Norway, 986 [] J. A. Suul, M. Molinas, L. Norum, T. Undeland, Tuning of Control Loops for Grid Connected Voltage Source Converters, in Proceedings of the 2 nd IEEE International Conference on Power and Energy, PECon 8, -3 December, 28, Johur Baharu, Malaysia [] F. D. Freijedo, J. Doval-Gandoy, O. Lopez, J. Cabaleiro, Robust Phase Locked Loops Optimized for DSP Implementation in Power Quality Applications, in Proceedings of the 34 th IEEE Annual Conference on Industrial Electronics, IECON 28, -3 November 28, pp [2] H. Kolstad, Control of an Adjustable Speed Hydro utilizing Field Programmable Devices, PhD-Thesis, Norwegian University of Science and Technology, NTNU, Trondheim, Norway, 22 [3] K. Ljøkelsøy, Description of control system for active rectifier, (In Norwegian), SINTEF Energy research, Technical report, TR F549, February 24 [4] S. Muyulema, E. J. Bueno, F. J. Rodríguez, S. Cóbreses, D. Díaz. Response of the grid converters synchronization using p.u. magnitude in the control loop, in Proceedings of IEEE International Symposium on Industrial Electronics, ISIE 27, 4-7 June 27, Vigo, Spain [5] P. B. F. Stavenes, Transistor converters integrated in the AC-grid Control strategy with use of phase reference vector, Master Thesis (In Norwegian), Norwegian University of Science and Technology, 2 [6] K. Ljøkelsøy, FPGA based processor board for control of power electronics converters, SINTEF Energy Research, Technical Report, TR A676, December 28 [7] K. Ljøkelsøy, O. Mo, Fast current controllers using FPGAs, in Proceedings of the th European Conference on Power Electronics and Applications, EPE 23, 2-4 September 23, Tolouse, France [8] ilinx Virtex-5 FT FPGA, Product information: [9] W. Leonhard, Control of Electric Drives, Springer-Verlag Berlin, Heidelberg, Germany, 985 [2] S. A. O. da Silva, E. A. A. Coelho, Analysis and Design of a Three-Phase PLL Structure for Utility Connected Systems under Distorted Utility Conditions, in Proceedings of the 9 th IEEE International Power Electronics Congress, CIEP 24, 7-22 October 24, Calaya, Mexico [2] S. A. O. da Silva, P. Donoso-Garcia, P. C. Cortizo, P. F. Seixas, A Three-Phase Line-Interactive UPS System Implementation with Series-Parallel Active Power-Line Conditioning Capabilities, IEEE Transactions on Industry Applications, Vol. 38, No. 6, November/December 22 EPE 29 - Barcelona ISBN: P.