PS12034 PS MITSUBISHI SEMICONDUCTOR <Application Specific Specific Intelligent Power Power Module> FLAT-BASE TYPE TYPE INSULATED TYPE TYPE

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1 MITSUBISHI SEMICONDUCTOR <pplication Specific Specific Intelligent Power Power Module> PS4 PS4 FLT-BSE TYPE TYPE INSULTED TYPE TYPE PS4 INTEGRTED FUNCTIONS ND FETURES Converter bridge for phase C-to-DC power conversion. phase IGBT inverter bridge configured by the latest rd. generation IGBT and diode technology. Inverter output current capability IO (Note ): Type Name Motor Rating IO (%) IO (5%; 6sec) PS4.75 kw/4 C.4rms 5.rms (Note ) : The inverter output current is assumed to be sinusoidal and the peak current value of each of the above loading cases is defined as : IOP = IO, TC < INTEGRTED DRIE, PROTECTION ND SYSTEM CONTROL FUNCTIONS: P-Side IGBTs : Drive circuit, high-level-shift circuit, Bootstrap circuit supply scheme for single control-power-source drive, and Under voltage (U) protection, N-Side IGBTs : Drive circuit, DC-Link current sense and amplifier circuits for over-current protection, Control-supply under-voltage (U) protection, and fault output (FO) signaling circuit. Fault Output : N-side IGBT short circuit (SC), over-current (OC), and control supply under-voltage (U). Inverter nalog Current Sense : N-Side IGBT DC-Link Current Sense. Input Interface : 5 CMOS/TTL compatible, Schmitt Trigger input, and rm-shoot-through interlock protective function. PPLICTION coustic noise-less.75kw/4 C Class phase inverters, motor control applications, and motors with built-in small size inverter package PCKGE OUTLINES () () () (4) (5) (6) (7) (8).5 (5) () () () 4-R () (9) (8) R 4-R φ ± Terminals ssignment :. P. P. R 4. S 5. T 6. N 7. N 8. U 9.. W. FO. amp. GND 4. WN 5. N 6. UN 7. WP 8. P 9. UP. TH. D. NC. CBW 4. CBW+ 5. CB 6. CB+ 7. CBU 8. CBU+.4 95±..4 (.4) (Fig. ) Mar.

2 MITSUBISHI SEMICONDUCTOR <pplication Specific Intelligent Power Module> PS4 FLT-BSE TYPE INSULTED TYPE INTERNL FUNCTIONS BLOCK DIGRM D UP P WP UN N WN FO (amp) TH U Protection Input signal conditioning (Interlock circuit) Fo Circuit + OC/SC Protection U Protection Level shifter Drive circuit Drive circuit P R S T N P U W GND N (Fig. ) MXIMUM RTINGS (Tj = 5) INERTER PRT CC CC(surge) P or N P(S) or N(S) ±Ic(±Icp) (surge) Each IGBT collector-emitter static voltage Each IGBT collector-emitter switching voltage Each IGBT collector current pplied between P-N pplied between P-N, Surge-value pplied between P-U..W, U..W-N pplied between P-U..W, U..W-N (Pulse) TC = 5, ( ) means IC peak value 9 ± (±) CONERTER PRT RRM Ea IO IFSM I t Repetitive peak reverse voltage Recommended C input voltage DC output current Surge (non-repetitive) forward current I t for fusing φ rectifying circuit cycle at 6Hz, peak value non-repetitive alue for one cycle of surge current rms s CONTROL PRT D, DB.5 ~ CIN Input signal voltage.5 ~ +7.5 FO Fault output supply voltage.5 ~ +7.5 IFO Fault output current 5 Iamp DC-Link IGBT current signal mp output current Mar.

3 MITSUBISHI SEMICONDUCTOR <pplication Specific Intelligent Power Module> PS4 FLT-BSE TYPE INSULTED TYPE TOTL SYSTEM Tj Junction temperature (Note ) ~ +5 Tstg Storage temperature 4 ~ +5 TC Module case operating temperature (Fig. ) ~ + ISO Isolation voltage 6 Hz sinusoidal C applied between all terminals and the base plate for minute. 5 rms Mounting torque Mounting screw: M.5.78 ~.7 N m (Note ) : The indicated values are specified considering the safe operation of all the parts within the SIPM. The max. ratings for the SIPM power chips (IGBT & FWDi) is Tj < 5. CSE TEMPERTURE MESUREMENT POINT LBEL (Fig. ) TC THERML RESISTNCE Rth(jc)Q Rth(jc)F Rth(jc)FR Rth(cf) Junction to case Thermal Resistance Contact Thermal Resistance Inverter IGBT (/6) Inverter FWDi (/6) Converter Di (/6) Case to fin, thermal grease applied ( Module) Min. Typ. Max ELECTRICL CHRCTERISTICS (Tj = 5, D = 5, DB = 5 unless otherwise noted) CE(sat) EC FR IRRM ton tc(on) toff tc(off) trr Short circuit endurance (Output, rm, and Load, Short Circuit Modes) Switching SO Collector-emitter saturation voltage FWDi forward voltage Converter diode voltage Converter diode reverse current Switching times FWDi reverse recovery time Tj = 5, Input = ON, Ic =, D = DB = 5 (Shunt voltage drop not included) Tj = 5, IC = Tj = 5, IFR = R = RRM, Tj = 5 / Bridge inductive, Input = 5 CC = 6, IC =, Tj = 5 D = 5, DB = 5 Note: ton, toff include delay time of the internal control 8, Input = 5 (One-Shot) C Tj(start) 5,.5 D = DB 8, Input = 5, Tj 5 IC < OC trip level,.5 D = DB 6.5 Min. Typ. Max No destruction FO output by protection operation No destruction No protecting operation No FO output Mar.

4 MITSUBISHI SEMICONDUCTOR <pplication Specific Intelligent Power Module> ELECTRICL CHRCTERISTICS (Tj = 5, D = 5, DB = 5 unless otherwise noted) ID IDB th(on) th(off) Ri fpwm tdead tint amp(%) amp(%) amp(5%) amp() OC toc SC tsc UD UDr UDB UDBr td tfo IFo(H) IFo(L) RTH B Circuit current Circuit current Input on threshold voltage Input off threshold voltage Input pull-up resistor PWM input frequency rm shoot-through blocking time Input interlock sensing Inverter DC-Link IGBT current sense voltage output signal Inverter DC-Link IGBT current sense voltage output limit Over current trip level Over current delay time Short circuit trip level Short circuit delay time D U trip level Fault output pulse width Fault output current Thermistor Resistance Thermistor B constant D U reset level DB U trip level DB U reset level U delay time Tj = 5, D = 5, in = 5 Tj = 5, D = DB = 5, in = 5 pplied between input terminal-inside power supply TC, Tj 5 Relates to corresponding inputs TC = ~ + (Note ) Relates to corresponding input (Fig. 6) IC = IOP(%) D = 5 IC = IOP(%) Tj = 5 (Fig. 4) IC = IOP(5%) D = 5 IC = (Fig. 4) Tj = 5 (Fig. 5) Tj = 5 (Fig. 5) Tj = 5 (Fig. 5) Tj = 5 (Fig. 5) ~ TC = Tj = 5 Tj = 5 (Note 4) Open drain output (Note 4) Tc = 5 Resistance at 5, 5 PS4 FLT-BSE TYPE INSULTED TYPE Typ (Note ) : The dead-time has to be set externally by the CPU; it is not part of the SIPM internal functions. (Note 4) : Fault output signaling is given only when the internal OC, SC, & U protection circuits are activated. The OC, SC and U protection (and fault output) operate for the lower arms only. The OC and SC protection Fault output is given in a pulse format while that of U protection is maintained throughout the duration of the under-voltage condition. RECOMMENDED OPERTING CONDITIONS CC D DB D, DB CIN(ON) CIN(OFF) tdead TC fpwm txx Supply circuit under voltage protection ripple Input on voltage Input off voltage rm shoot-through blocking time Module case operating temperature PWM Input frequency llowable input on-pulse width pplied across P-N terminals pplied between D-GND pplied between CBU+ & CBU, CB+ & CB, CBW+ & CBW pplied between UP P WP UN N WN and GND Relates to corresponding inputs TC, Tj 5 Min Max Min. Typ. Max kω khz ns m ms µ kω K / khz INERTER DC-LINK IGBT CURRENT NLOGUE SIGNLING OUTPUT (TYPICL) 5 amp 4 D = 5 Tj = 5 amp (%) amp () amp (%) DC-LINK IGBT Current (%), (IC = IO ) (Fig. 4) Mar.

5 MITSUBISHI SEMICONDUCTOR <pplication Specific Intelligent Power Module> PS4 FLT-BSE TYPE INSULTED TYPE CURRENT BNORMLITY PROTECTIE FUNCTIONS Ic() Short circuit trip level SC Over current trip level Protection is achieved by monitoring and filtering the N-side DC-Bus current. When a current trip-level is exceeded all the N-side IGBTs are intercepted (turned OFF) and a fault-signal is output. fter the fault-signal output duration (.8m sec (typ.)@5), the interception is Reset at the following OFF input signal level (more than 4.). OC Collector current tw () (Fig. 5) RM-SHOOT-THROUGH INTER-LOCK PROTECTIE FUNCTION P-Side Input Signal : CIN(p) ON a b4 N-Side Input Signal : CIN(n) ON a4 b P-Side IGBT Gate : GE(p) a a b N-Side IGBT Gate : GE(n) b (Fig. 6) Description: () During the ON-State of either of the upper-arm or the lower-arm IGBT, the inter-lock protection circuit blocks any erroneous ON pulses (resulting from input noise) from triggering the other arm IGBT and thus it prevents the arm-shoot-through situation. () When two ON-signals are received for both the upper and the lower arms, the signal received first will be passed to the IGBT and the second signal will be blocked. The second signal will be passed to its corresponding IGBT immediately after the first signal is OFF. Note: This protective function provides no fault signaling output. The Dead-Time has to be set using the micro-controller (CPU). Operation: a. P-side normal ON-signal P-side IGBT gate turns ON. a. N-side erroneous ON-signal N-side IGBT gate remains OFF. a. While P-side ON-signal remains P-side IGBT gate remains ON. a4. N-side normal ON-signal N-side IGBT gate turns ON. b. N-side normal ON-signal N-side IGBT gate turns ON. b. Simultaneous ON-signals P-side IGBT gate remains OFF. b. N-side receives OFF-signal N-side IGBT gate turns OFF. b4. Immediately after (b) P-side IGBT gate turns ON. RECOMMENDED I/O INTERFCE CIRCUIT kΩ D(5) SIPM Up, p, Wp, Un, n, Wn CPU.nF kω FO amp GND (Fig. 7) Mar.

6 This datasheet has been download from: Datasheets for electronics components.