PS21661-RZ/FR PS21661-FR. APPLICATION AC100V~200V, three-phase inverter drive for small power motor control.

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1 MITSUBISHI SEMICONDUCTOR <Single-In-Line Package Intelligent Power Power Module> TYPE TYPE PS21661-RZ PS21661-FR INTEGRATED POWER FUNCTIONS 600/3A low-loss 5th generation IGBT inverter bridge for 3 phase DC-to-AC power conversion. INTEGRATED DRIE, PROTECTION AND SYSTEM CONTROL FUNCTIONS For upper-leg IGBTS :Drive circuit, High voltage isolated high-speed level shifting, Control circuit under-voltage protection (U). For lower-leg IGBTS : Drive circuit, Control circuit under-voltage protection (U), Short circuit protection (SC). Fault signaling : Corresponding to an SC fault (Lower-side IGBT) or a U fault (Lower-side supply). Input interface : 5 line CMOS/TTL compatible Schmitt Trigger receiver circuit (Active high), Arm-short-through interlock protection. APPLICATION AC100~200, three-phase inverter drive for small power motor control. Fig. 1 PS21661-RZ PACKAGE OUTLINES Dimensions in mm q~#5 : pins numbers. The terminals array, please reference to the Fig.5.

2 Fig. 2 PS21661-FR PACKAGE OUTLINES Dimensions in mm q~#5 : pins numbers. The terminals array, please reference to the Fig.7. MAXIMUM RATINGS (Tj = 25 C, unless otherwise noted) INERTER PART Parameter Ratings Unit CC CC(surge) CES ±IC ±ICP PC Tj Supply voltage Supply voltage (surge) Collector-emitter voltage Collector current Collector current (peak) Collector dissipation Junction temperature Applied between P-N Applied between P-N Tf = 25 C Tf = 25 C, tw 1msec Tf = 25 C, per 1 chip (Note 1) ~+150 Note 1 : The maximum junction temperature rating of the power chips integrated within the SIP-IPM is 150 C (@ Tf 100 C) however, to insure safe operation of the SIP-IPM, the average junction temperature should be limited to Tj(ave) 125 C (@ Tf 100 C). A A W C CONTROL (PROTECTION) PART Parameter Ratings Unit D DB IN I SC Control supply voltage Control supply voltage Input voltage Fault output supply voltage Fault output current Current sensing input voltage Applied between N1-NC Applied between UFB-U (UFS), FB- (FS), WFB-W (WFS) Applied between UP, P, WP-NC, UN, N, WN-NC Applied between -NC Sink current at terminal Applied between -NC ~D 0.5~D ~D

3 TOTAL SYSTEM Parameter Ratings Unit CC(PROT) Self protection supply voltage limit D = 13.5~16.5, Inverter part (short circuit protection capability) Tj = 125 C start, non-repetitive, less than Tf Tstg Heatsink operation temperature Storage temperature (Note 2) 20~ ~+125 C C 60Hz, Sinusoidal, AC 1 minute, connection iso Isolation voltage pins to heat-sink plate 1500 rms Note 2 : Tf MEASUREMENT POINT THERMAL RESISTANCE CE(sat) EC ton trr Rth(j-f)Q Rth(j-f)F tc(on) toff tc(off) ICES AI Board Specification : Dimensions mm, finishing 12s, warp 50~+100µm Control AI Board Terminals SIP-IPM Parameter IGBT Chip Temp. measurement point (inside the AI board) FWD Chip Junction to fin thermal resistance Parameter 10.5mm 15mm 25mm 100~200µm of evenly applied Silicon-Grease Tj = 25 C Tj = 125 C Temp. measurement point (inside the AI board) Inverter IGBT part (per 1/6 module) (Note 3) Inverter FWD part (per 1/6 module) (Note 3) Note 3 : Grease with good thermal conductivity should be applied evenly about +100µm ~ +200µm on the contact surface of SIP-IPM and a heat-sink. ELECTRICAL CHARACTERISTICS (Tj = 25 C, unless otherwise noted) INERTER PART Collector-emitter saturation voltage FWD forward voltage Switching times Collector-emitter cut-off current CONTROL (PROTECTION) PART ID IDB H L IIN SC(ref) UDBt UDBr UDt UDr t th(on) th(off) Circuit current Parameter Fault output voltage Input current Short circuit trip level Supply circuit under-voltage protection Fault output pulse width ON threshold voltage OFF threshold voltage D = DB = 15 IC = 3A, Tj = 25 C IN = 5 IC = 3A, Tj = 125 C Tj = 25 C, IC = 3A, IN = 0 CC = 300, D = 15 IC = 3A, Tj = 125 C Inductive load (upper-lower arm) IN = 0 5 CE = CES D = 15, IN = 0 D = 15, IN = 5 DB = 15, IN = 0 DB = 15, IN = 5 Total of N1-NC (U,, W) UFB-U (UFS), FB- (FS), WFB-W (WFS) SC = 0, circuit : 1kΩ to 5 pull-up SC = 1, I = 10 IN = 5 Tj = 25 C, D = 15 (Note 4) Trip level Reset level Tj 125 C Trip level Reset level (Note 4) Applied between: UP, P, WP-NC, UN, N, WN-NC 1.5mm Min. 10mm Limits Typ. Limits Max Min. Typ. Max. Note 4 : Short circuit protection is functioning only at the low-arms. Please select the value of the external shunt resistor such that the SC triplevel is less than 5.1A Limits Min. Typ. Max Unit C/W Unit Unit

4 MECHANICAL CHARACTERISTICS AND RATINGS Parameter Min. Limits Typ. Max. Unit Mounting torque Weight Heat-sink flatness Mounting screw : (M3) (Note 5) N m g µm Note 5: Measurement point of heat-sink flatness SIP-IPM + Measurement Range 3mm Heat-sink + Heat-sink REMENDED OPERATION CONDITIONS Parameter Limits Min. Typ. Max. Unit CC D DB D, DB tdead fpwm IO NC txx Supply voltage Control supply voltage Control supply voltage Control supply variation Arm shoot-through blocking time PWM input frequency Allowable r.m.s current NC terminal voltage minimum on pulse width Applied between P-N Applied between N1-NC Applied between UFB-U (UFS), FB- (FS), WFB-W (WFS) Relates to corresponding input signal for blocking arm shoot-through Tj 125 C, Tf 100 C CC = 300, D = 15, fc = 15kHz, P.F = 0.8, sinusoidal Tj 125 C, Tf 100 C Applied between NC-N (include surge voltage) UP, P, WP, UN, N, WN terminal / khz Arms

5 Fig. 3 THE SIP-IPM INTERNAL CIRCUIT U(UFS) UFB SIP-IPM P N1 CC B UP UN (FS) FB S NO N N1 CC B P N S NO W(WFS) WFB N1 NC WP WN Fo CC B S NO

6 Fig. 4 PS21661-RZ PACKAGE OUTLINES q~#5 : pins numbers. Terminals array Terminal No N P NC N1 WN WFB WP W(WFS) N1 N FB P (FS) N1 UN UFB UP U(UFS) Description Inverter DC-link negative (GND) terminal Inverter DC-link positive terminal Fault output terminal Control GND terminal Short-circuit trip voltage sensing terminal W-phase N-side control input terminal W-phase P-side drive supply terminal W-phase P-side control input terminal W-phase inverter output terminal (W-phase P-side drive supply GND terminal) -phase N-side control input terminal -phase P-side drive supply terminal -phase P-side control input terminal -phase inverter output terminal (-phase P-side drive supply GND terminal) U-phase N-side control input terminal U-phase P-side drive supply terminal U-phase P-side control input terminal U-phase inverter output terminal (U-phase P-side drive supply GND terminal) The following pins are dummy pins are therefore should not be connected. 4,8,13,14,16,21,22,24,29,30~35 (30~35 are the high voltage side pins.) M ar k i n g s i d e q N P w y WFB!0 W(WFS)!2 FB!8 e t NC u N1 o WN!1 WP!5 N1!7 N!9 UP Fig. 5

7 Fig. 6 PS21661-FR PACKAGE OUTLINES q~#5 : pins numbers. Terminals array Terminal No N P NC N1 WN WFB WP W(WFS) N1 N FB P (FS) N1 UN UFB UP U(UFS) Description Inverter DC-link negative (GND) terminal Inverter DC-link positive terminal Fault output terminal Control GND terminal Short-circuit trip voltage sensing terminal W-phase N-side control input terminal W-phase P-side drive supply terminal W-phase P-side control input terminal W-phase inverter output terminal (W-phase P-side drive supply GND terminal) -phase N-side control input terminal -phase P-side drive supply terminal -phase P-side control input terminal -phase inverter output terminal (-phase P-side drive supply GND terminal) U-phase N-side control input terminal U-phase P-side drive supply terminal U-phase P-side control input terminal U-phase inverter output terminal (U-phase P-side drive supply GND terminal) The following pins are dummy pins are therefore should not be connected. 4,8,13,14,16,21,22,24,29,30~35 (30~35 are the high voltage side pins.) M ar k i n g s i d e q N P w y WFB!0 W(WFS)!2 FB!8 WP!5 N1!7 N!9 UP Fig. 7 e t NC u N1 o WN

8 Fig. 8 TIMING CHARTS OF THE SIP-IPM PROTECTIE FUNCTIONS [A] Short-Circuit Protection (Lower-arms only) a1. Normal operation : IGBT ON and carrying current. a2. Short circuit current detection (SC trigger). a3. Hard IGBT gate interrupt. a4. IGBT turns OFF. a5. output (20~80). a6. Input L : IGBT OFF state. a7. Input H : IGBT ON state, but during the active signal the IGBT doesn t turn ON. a8. IGBT OFF state. Lower-arms control input a6 a7 Protection circuit state SET Internal IGBT gate a3 a2 Output current Ic a1 SC a4 a8 Sense voltage of the shunt resistance Error output Fo a5 SC reference voltage CR circuit time constant DELAY (Note) Note : The CR time constant safe guards against erroneous SC signal resulting from di/dt generated voltages when IGBT turns ON. The optimum setting for the CR circuit time constant is 1.5~2.0. [B] Under-oltage Protection (Lower-arms, UD) a1. Control supply voltage rises : After the voltage level reaches UDr, the circuits start to operate when the next input is applied. a2. Normal operation : IGBT ON and carrying current. a3. Under voltage trip (UDt). a4. IGBT OFF in spite of control input condition. a5. output (20~80). a6. Under voltage reset (UDr). a7. Normal operation : IGBT ON and carrying current. Control input Protection circuit state SET Control supply voltage D UDBr a1 UDBt a3 a6 Output current Ic a2 a4 a7 Fault output Fo a5

9 [C] Under-oltage Protection (Upper-arms, UDB) a1. Control supply voltage rises : After the voltage level reaches UDBr, the circuits start to operate when the next input is applied. a2. Normal operation : IGBT ON and carrying current. a3. Under voltage trip (UDBt). a4. IGBT OFF in spite of control input condition, but there is no signal output. a5. Under voltage reset (UDBr). a6. Normal operation : IGBT ON and carrying current. Control input Protection circuit state SET UDBr Control supply voltage DB a1 UDBt a3 a5 a2 a4 a6 Output current Ic Error output Fo High-level (no fault output) [D] Simultaneous input signal prevention function a1 a3. Normal operation : IGBT ON and outputing IGBT gate voltage. a2 a4. Normal operation : IGBT ON and outputing IGBT gate voltage. a5. Abnormal pulse input. a6. IGBT OFF state. a7. No fault output. Upper-arm control input a1 a5 Lower-arm control input a2 Internal upper-arm IGBT gate voltage a3 a6 Internal lower-arm IGBT gate output a4 Protection circuit state SET Fault output a7

10 Fig. 9 TYPICAL SIP-IPM APPLICATION CIRCUIT EXAMPLE R2 C3 C2 C1 UFB U(UFS) N1 IC1 CC B SIP-IPM P UP S UN M R2 C3 C2 C1 FB (FS) N1 IC2 CC NO B N A R1 C4 Shunt resistor CPU UNIT 5 line R3 R2 C3 C2 C1 P N WFB W(WFS) N1 NC IC3 CC S NO B N1 WP S WN NO 15 line Note 1 : Input signal lines are pulled-down with 4.7kΩ (min.) internal resistor. If these input lines are susceptible to noise, an RC coupling at each input is recommended. Input signal voltage is determined by the values of internal pull-down resistor and the external connected resistor. Set the external resistance value so that input signal voltage exceeds the on-threshold voltage. To prevent the input signals oscillation, the wiring of each input should be as short as possible. 2:By virtue of integrating the specific type HIC inside the module, direct coupling to CPU terminals without any opto-coupler or transformer isolation is possible. 3: output is open collector type. This signal line should be pulled up to the positive side of the 5 power supply with approximately 1kΩ resistance. 4:Approximately a 0.1~2µF by-pass capacitor should be used across each power supply connection terminals. 5:To prevent errors of the protection function, the wiring of A should be as short as possible. 6:Each capacitor should be located as close to the pins of the SIP-IPM as possible. 7:In the recommended protection circuit, please select the R1C4 time constant in the range of 1.5~2. 8:To prevent surge destruction, the wiring between the smoothing capacitor and the P&N1 pins should be as short as possible. Approximately a 0.1~0.22µF snubber capacitor between the P&N1 pins is recommended.