Time-Code Reception. Table of Contents

Transcription

1 Time-Code Reception

2 Time-Code Reception Table of Contents General Information Introduction Time-Code Transmitters Time-Code Signals and their Reception Time-Code Receivers TEMIC Devices for Time-Code Reception U3B U6B T5B INCOR - the TEMIC Software Microcontrollers M3C MC Design of a Time-Code Receiver with UxB U3B Circuit Technology Board Layout Antenna Circuit Application Decoding Algorithm The Use of the TCO Signal Layout Example Data Sheets U3B: Time-Code Receiver with A/D Converter UB: Time-Code Receiver with Digitized Serial Output U6B: Time-Code Receiver with TC Output T5B: Low-Cost Time-Code Receiver M3C505 Low-Current 3- and 5-V Solution for Consumer Applications MC5 Versatile High-End Controller for General Purposes

3 General Information Introduction From time to time, time deviations or power fails occur to clocks and watches which must be corrected. For correct time setting, an atomic clock can be used as a reference clock. Several transmission stations situated worldwide send coded signals based on the atomic reference clock with information on the precise time via long waves. To receive and decode these signals, a special receiver is necessary. The most convenient and exact method of time synchronization for the customer is the receiver being integrated into the watch, automatically monitoring the time. An essential requirement for such a time-code receiver is a small design and low current consumption at minimum voltage supply. TEMIC was one of the industry s first suppliers of timecode receivers and manufactured as soon as 96 receiver circuits for general time-code applications in highvolume production. Time-Code Transmitters For precise time synchronization, there are four transmitters worldwide. One transmitter is located in the USA, its reception area is more or less the entire area of North America. Another transmitter, located near London, covers UK, and a transmitter in Germany is delivering the time information for Europe. Additionally, there is one transmitter in Japan. Amplitude-modulated time-code transmitters deliver the data to decode the present time (based on an atomic time normal), the day, the month and the year. They provide also information about summer- and winter time if relevant. The information is transmitted via a long-wave transmitter in the frequency range of 0 to 0 khz. This frequency range is the best solution to construct receivers with low power consumption and high sensitivity. Time-code transmitter Atomic-based time Present time Day Month Year Daylight saving hour Long-wave transmitter Figure. Time-code transmission Table. The most important time-code transmitters worldwide Type Location Frequency Power Modulation ÁÁÁÁ Mainflingen/ 77.5 khz ÁÁÁÁÁÁÁ Frankf. a.m. (FRG) ÁÁÁÁ ÁÁÁÁÁÁ Carrier reduced by db for 0 or 00 ÁÁÁÁÁÁ ÁÁÁÁ DCF77 ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 50 kw ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ JGAS ÁÁÁÁÁÁÁ Sanwa (J) ÁÁÁÁ 0 khz ÁÁÁÁÁÁ kw ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Carrier switched off for 00, 500 or 00 ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ MSF Teddington (GB) 60 khz 50 kw Carrier switched off for, 00 or 300 ÁÁÁÁ WWVB ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ Fort Collins (USA) 60 khz ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 50 kw Carrier reduced by db for 00, 500 or ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ (unconfirmed)

4 Time-Code Signals and their Reception Time-code transmitters on long waves are best suited for clocks with radio-controlled synchronization because they have good propagation characteristics and their receivers can be dimensioned with low power consumption. The four most important transmitters worldwide (with regard to commercial clocks) are summarized in table. Figure shows the propagation distances of DCF77, figure 3 the information distributed by the transmitter. The field strength measured in the reception area consists of two components: the ground wave and the space wave which arises from reflections in the ionosphere. The most predominant reception possibility exists up to a distance of 000 km from the transmitter. From figure, it can be seen that the ground wave is still dominant up to a distance of almost 600 km from the transmitter and the field strength is at least 60 dbv/m ( mv/m). Ground waves and space waves become entangled at distances between 600 and 000 km. Reception is then less stable due to interferences. In long distances, longest stable field strengths can be expected at night time. While in short waves, the transmission time of a deletion takes seconds or a fraction of a second, in long waves, this can take several minutes up to half an hour. A well-constructed radio-controlled clock with a ferrite antenna has high sensitivity and can pick up signals of up to some 30 dbv/m. By using the U3B with ADU, values of about 0 dbv/m can be achieved. Even wrist watches with their complex antenna construction can be designed so to operate at up to approximately 0 dbv/m. In low-cost products only 50 dbv/m were measured. Therefore, radio-controlled clocks which receive the DCF77 signal can operate without any proble in Germany up to a distance of 600 km from the transmitter s location (Mainflingen/ Frankfurt am Main). Within this area, the field strength is more than mv/m which is sufficient enough to guarantee good reception. At a distance of more than 600 km and less than 000 km from the transmitter (see figure ), radio-controlled clocks can only operate with several restrictions because ground waves and space waves become entangled. This may cause interferences and therefore deletion of the signal. Radio-controlled reception is nevertheless possible in this area by using highly efficient antennas and receivers as well as intelligent decoding software. Best reception time is the night time as a lot of interference sources are then switched off Ground wave 0 Field strentgh ( db V ) Night Winter day Space waves 30 0 Summer day Distance ( km ) Figure. Propagation distances of the time-code transmitter DCF

5 Time frame minute Time frame ( index count second ) Coding when required Minutes Hours Calendar Day Month day of the week Example: 9.35 h s 0 0 P 0 P Year Sec Minutes Hours Start bit Parity bit P Parity bit P e Figure 3. The German transmitter DCF77: a typical time-code example 000 km 600 km Figure. The propagation area of the time-code transmitter DCF77 Time-Code Receivers Radio-controlled clocks receive time-code signals from regional time-code transmitters around the world in the VLF area. The signal is received and decoded by the radio-controlled system. TEMIC offers two different solutions to receive timecode transmissions. Both solutions have the same receiving concept. The first approach is a straight-through receiver which obtains the signal from a ferrite antenna (tuned to the desired frequency) and amplifies it. The selectivity is achieved by using one or two crystal filters. The AM modulation is toggling the decoder stage. At the output of the decoder stage (TCO), a rectangular signal, following the amplitude modulation, is present. The second solution is using the U3B which delivers a -bit digitized signal to the microcontroller. By means of TEMIC s software INCOR, an improved overall sensitivity of more than 6 db can be achieved

6 TEMIC Devices for Time-Code Reception U3B TEMIC launched a new era in precise and user-friendly radio-controlled clocks when the first TEMIC ICs for radio-controlled consumer clocks were introduced in 96 and has remained a leader in this field since then. The U3B family was developed to achieve constant high sensitivity rates with low voltage and power consumption. Therefore, radio-controlled clocks as well as all other clocks and wrist watches can be used with standard batteries and have very long operating times. Radio-controlled clocks consist of an antenna, a receiver circuit, a microcontroller as well as various display and input elements. The U3B is a very efficient receiver circuit which can be universally applied for receiving the time-code signals in the VLF area. Furthermore, the TEMIC MARC microcontroller family can be used in applications with the U3B and U6B for radiocontrolled syste. The radio-controlled clock is constantly set precisely. Therefore, the internal crystal clock is then set precisely to the second by the received signal. Switching from summer- to winter time is also carried out in each individual country if the information from the transmitter is available. The U3B family offers high sensitivity and low power consumption. The circuit can be used for universal applications due to its supply voltage of. V to 5.5 V. With its typical power consumption of 3 µa to 0 µa, it is particularly suitable for long-life battery applications. Features Very low power consumption Very high sensitivity ( V typical) Choice of selectivity by use of one or two crystal filters Power-down mode available Few external components necessary -bit parallel output AGC hold mode for bridging over known interferences (e.g., stepper motor) SSO0 package Time-code receiver U3B UB U6B T5B Figure 5. Time-code reception 07.97

7 VCC GND 3 PON CLK D3 D D D Power supply ADC Decoder Impulse circuit e 9 FLB FLA DEC IN AGC amplifier Rectifier & integrator 3 SL SB QA QB QA QB REC INT Figure 6. U3B block diagram +V CC Control lines Ferrite Antenna f res = 77.5 khz 77.5 khz ) U3B nf nf nf nf 77.5 khz D0 D D D3 PON 3) Microcomputer 9 96 C 6. nf C 33 nf C 3 nf SL ) CLK ) Display Keyboard ) If SL is not used, SL is connected to VCC ) 77.5-kHz crystal can be replaced by pf 3) If IC is activated, PON is connected to GND ) Voltage swing 0 mv pp at Pin Figure 7. Application circuit U3B for 77.5 khz

8 U6B AGC hold mode for bridging over known interferences (e.g., stepper motor) Extremely low power consumption Very high sensitivity Power-down mode Digitized serial output signal SSO0 package Selectivity choice by use of one or two crystal filters T5B Same specifications as U6B but only available as die (wafer form, die-on-foil and die-in-trays) PON TCO e GND VCC Power Supply Decoder FLB FLA 9 DEC IN SB AGC Amplifier Rectifier & Integrator QA QB QA QB REC INT SL Figure. U6B block diagram + V CC Control lines Ferrite Antenna f res = 77.5 khz 0 NC 9 NC TCO 3 7 NC NC PON 3) SL ) Microcomputer Keyboard 77.5 khz ) 5 6 U6B 6 5 Display C 6. nf 7 C 33 nf khz C 3 nf ) If SL is not used, SL is connected to VCC ) 77.5 khz crystal can be replaced by pf 3) If IC is activated, PON is connected to GND Figure 9. Application circuit U6B for 77.5 khz 07.97

9 INCOR - the TEMIC Software INCOR is a special software program for microcontrollerbased time signal decoders. In combination with a special ADC hardware interface on the U3B chip, it is possible to improve the time-code readability at weak input signals of more than 6 db. INCOR is written in C language and fits into the MC5. INCOR can only be used together with the U3B. It reduces time-code reception proble in areas with difficult receiving conditions especially in areas with very weak field strength conditions or noisy environments (e.g., USA, Japan, Spain, Italy, Scandinavia). Microcontrollers TEMIC offers a complete family of cost-effective, singlechip CMOS microcontrollers, based on a -bit CPU core designed for the voltage range of. up to 6. V applications. The modular MARC architecture is HARVARD-like, high-level language oriented and best designed for analog, digital watch and clock applications with time-code receiver functions. The MARC controller s low-voltage and low-power consumption suits the requirements of watches and clocks. M3C505 -Bit, Low-End, Low-Power Microcontroller CPU with -MHz RC clock generator -KByte ROM 56 -bit RAM I/ O lines + inputs Liquid-crystal display driver with 0 segment drives Buzzer output driver 3-kHz crystal oscillator Low-power consumption (.5 A sleep) Voltage range of. V to 5.5 V This microcontroller can be programmed in a high-level language (qforth) with an optimizing compiler. A power-saving and a sleep mode is a standard in the MARC family. The M3C505 has also a separate watch crystal oscillator for the time-keeping function. The built-in LCD voltage generation with temperature compensation completes the features for this solution. MC5 -Bit, High-End, Low-Power Microcontroller CPU with programmable system clock 9-KByte ROM 56 bit internal and 56 bit external RAM 0 fixed I/ O lines + 6 optional Liquid crystal display driver with up to 3 segment outputs to 3 watch-motor drivers buzzer output drivers 3-kHz crystal oscillator Low-power consumption (3 A sleep) Large voltage range from. V to 6. V The MC5 as any member of the MARC family can be programmed in a high-level language (qforth) with an optimizing compiler. It has a compact, RISC-like instruction set with a ROM look-up table. A unique AUTOSLEEP function is available. The MARC has a built-in self-check routine in a separate k -bit ROM area. An economical, PC-based development system is available

10 V EE V EE C C OSCIN OSCOUT AV DD V SS V DD NRST TE SCLIN SCLOUT V REG S7...S3 (bidir. I/O) S...S6 COM0.. COM3 LCD 3 x and 6 I/O PRAM 56 x bit Real time clock Low voltage detect ROM RAM 9K x bit 56 x bit Watch dog MARC bit CPU core Master reset Prescaler Interval Timer Test Sleep Timer/ counter Timer Timer 0 System clock I/O Port (high drive) I/O bus I/O I/O I/O Interrupt & reset I/O Interrupt I/O serial Buzzer Port 0 Port Port B Port Figure. MC5 (for INCOR software) TST TST TCL NRST V DD V SS System-clock generation Sleep Power-on reset RAM address registers ROM X 096 x bit Y SP Program counter RP Memory bus Instruction bus Interrupt controller Instruction decoder CCR TOS RAM 53 x bit ALU I/O I/O + strobe Inputs key int. I/O I/O bus External interrupts Oscillator Prescaler 3 khz LCD driver C C V EE V EE V REG PORT PORT 0 OD PORT 5 PORT INT7 AV DD INT, BUZZER 3 khz AV SS COM0...3 S Figure. M3C

11 Table. TEMIC products for time-code receivers Product Function Key Features Benefits Package Availa bility Time-code receiverááááááááááá Extremely low-power ÁÁÁÁÁÁÁ Sensitivity increased ÁÁÁÁ SSO0 ÁÁÁÁ Now with A/D converter consumption by INCOR software ÁÁÁÁ U3B ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Very high sensitivity ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Very high selectivity by using ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ two crystals ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ -bit ADC output ÁÁÁÁÁÁÁÁÁÁÁÁÁ T5BÁÁÁÁÁÁÁ Time-code receiverááááááááááá Die version ÁÁÁÁÁÁÁ Low-cost solution ÁÁÁÁ Die form ÁÁÁÁ Now ÁÁÁÁÁÁÁÁÁÁ with TCO ÁÁÁÁÁÁÁÁÁÁÁ Extremely low-power ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ consumption ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Very high sensitivity ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Very high selectivity by using ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ two crystals ÁÁÁÁÁÁÁÁÁÁÁÁÁ U6BÁÁÁÁÁÁÁ Time-code receiverááááááááááá Extremely low-power ÁÁÁÁÁÁÁ Flexible to different ÁÁÁÁ SSO0 ÁÁÁÁ Now with TCO consumption applications ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Very high sensitivity ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Very high selectivity by using ÁÁÁÁÁÁÁÁÁÁÁÁÁ two crystals ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ UB Time-code receiver Extremely low-power Flexible to different ÁÁÁÁÁÁÁ with TCO ÁÁÁÁÁÁÁÁÁÁÁ consumption ÁÁÁÁÁÁÁ applications ÁÁÁÁ ÁÁÁÁ SO6L Now ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Very high sensitivity ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Very high selectivity by using ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ two crystals ÁÁÁÁÁÁÁÁÁÁÁÁÁ MC5ÁÁÁÁÁÁÁ -bit low-power ÁÁÁÁÁÁÁÁÁÁÁ Up to segments LCD drive ÁÁÁÁÁÁÁ For INCOR software ÁÁÁÁ Die form ÁÁÁÁ Q3/97 ÁÁÁÁÁÁÁÁÁÁ microcontroller ÁÁÁÁÁÁÁÁÁÁÁ 5 bit RAM ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 9-KByte ROM ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mask-programmable ÁÁÁÁ M3C505 ÁÁÁÁ ÁÁÁÁÁÁÁ -bit low-power ÁÁÁÁÁÁÁÁÁÁÁ Up to 0 segments LCD drive ÁÁÁÁÁÁÁ Low-cost solution ÁÁÁÁ Die form ÁÁÁÁÁÁÁ microcontroller ÁÁÁÁÁÁÁÁÁÁÁ 56 ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Now ÁÁÁÁ -bit RAM ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ -KByte ROM ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Mask-programmable

12 Design of a Time-Code Receiver with UxB U3B Circuit Technology The radio-controlled receiver chip U3B and its modifications combine high sensitivity and low power consumption with a broad range of applications. The supply voltage range of. V to 5.5 V enables various applications such as battery supply or supply of standard logic circuits. The IC s power consumption of typically 3 µa to 0 µa fits for long life-battery applications, e.g., wrist watches. The sensitivity in this case, however, is near to the physical limit. The signal-to-noise ratio and thus the overall sensitivity can be improved by means of an internal A/D converter and special software for signal analysis. Several innovations were needed in circuit technology to achieve these improvements. The operating resistances of amplification stages become larger, the lower the supply currents. For this reason, integration limits, preventing further decrease of the supply current, show up very soon. This difficulty is overcome by using active, electronic resistances (figures a and b). Figure a shows a conventional differential stage. In figure b, the circuit with T 3 T 7 replaces the operating resistances R and R. The values of the operating resistances are determined by the differential resistance of the transistor diodes T 5 and T 6. The transistor current sources T 3 and T are controlled via the control loop (T 7 ). The amplification of this circuit is approximately: I /I. The non-linearity of the diodes T 5 and T 6 is completely compensated by the non-linearity of a similar subsequent stage, thus resulting in very low-distorted amplifiers. As a disadvantage, additional noise is generated due to the current sources T 3 and T. The bandwidth of 0 khz at an amplification factor of is identical to a conventional differential stage. V i T T 3 T I A T T 5 T 6 T 7 V o I 0. A Figure b. Differential stage with electronic load V S Figure. Figure 3a shows the principle diagram of a crystal filter. An undesired signal is generated at high frequencies due to the parallel capacitance (load capacitance) C b. C a L C b R R Figure 3a. Principle of a crystal-filter circuit I I R R R 00 k 00 k V i T V o V e Q C p T V S. p I.5 A Figure a. Conventional differential stage V S Figure 3b. Crystal filter with capacitance compensation Figure

13 A new crystal-filter circuit was developed (figure 3b) which enables the compensation of parallel capacitance of the crystal and additionally easy adjustability of the bandwidth. Selectivity was improved by using two filters. The circuit consists of two differential stages connected crosswise at the outputs. The first stage has a crystal filter between the emitters. The second differential stage with C p produces an equal capacitive current which compensates the undesired output current. The resistance of the pinch resistors P and P increases according to the voltage control used. Depending on the technology applied, a factor of about 3 in the range of 0 V to 5 V is normal. In the circuit as shown in figure 5, the pinch resistances serve as controllable emitter resistances. By means of the transistors T T 3, the output voltage V out tracks the input voltage V in and the pinch resistances are made equal to one another. The input electrode I n acts as a diode in reverse direction, i.e., it hardly picks up any current flow. T times Ve T T 5 times T 6 T T 3 times T 7 T I out In T I I I A 0.5 A P 500 k P T Out Figure 5. Decoupling amplifier based on controlled pinch resistances T A I I 0.5 A T 9 T Figure. Rectifier circuit with asymmetrical differential stages Improved bandwidth-to-current-consumption ratio is achieved by using a new type of rectifier circuit (see figure ). Two asymmetrical differential stages are built into this new rectifier stage. By means of this circuitry, a bandwidth of more than 0 khz at only.5 µa current consumption can be achieved. To design with small capacitances in the external circuitry, largest possible modulation and smallest possible creepage currents have to be gained. This is achieved by using controlled pinch resistances instead of field-effect transistors (figure 5). The decoding by means of a normal Schmitt trigger is somewhat disadvantageous, because only logic 0 or are available as output signal. The U3B s integrated A/D converter, however, provides the processor with a -bit signal. A special software achieves a signal-to-noise ratio which is approximately 6 db better than that when using a Schmitt-trigger (TCO) signal, and thus also a gain in sensitivity of up to 6 db. The converter especially developed for TCO handling requires only a current supply of approximately.7 A. The input signal generates a current of 0 µa to 0 A. A/D conversion is triggered off by an external clock signal. After a downward slope of the clock signal, a value appears at the -bit output which corresponds to the variation in the mean value of the antenna voltage. The time-code signal can be decoded by means of a series of such sampling values in a time sequence of approximately. After the upward slope of the clock signal, a value appears which approximately corresponds to the level of the antenna voltage (fieldstrength signal). By means of this value, an indication of receiving conditions can be derived

14 Board Layout When designing a board layout, certain guidelines have to be maintained to achieve high sensitivity and minimum parasitic effects. The wires connected to the antenna have to be shielded or twisted and should be very short in size on the board. The filter crystals have to be placed very close to the IC pins in order to avoid additional capacitances. Even circuit capacitances of a few tenths pf diminish the far-off selectivity and thus the sensitivity of the system. Pulsing currents, for example for a stepper motor, can activate the antenna by means of the magnetic field. Electro-magnetic fields can also be generated by the circuit. It should be therefore as small, as narrow as possible. Ground loops as well as metal covers near the ferrite antenna can mute the antenna due to induced eddy currents. This can be avoided if the axes of the antenna rod are on level with the circuit path. At lower frequencies, the radio-controlled clock IC has very good interference suppression so that the supply voltage interference can be easily avoided by sieving via an RC filter. Television sets interfere above all in the fifth harmonic of the line frequency. If the clock is on top of a television set it only receives if the television set is switched off. Gas discharge lamps (fluorescent tubes) operating at 50 Hz inductively are weak interference factors as long as the discharge is stable and the interference suppression is effective. Energy-saving lamps operating at high frequencies have (in contrast to the interference factors mentioned above) a stronger interference spectrum which is, however, according to measurements carried out by TEMIC, below 77.5 khz. In case the moment of the beginning of an interference impulse is known, the SL function can be used. If there is a logic 0 at the SL input, the operating stage of the receiver is memorized. After interference decreases and after the reset of the SL input (logic 0 ), the receiver carries on operation. A main application is the suppression of self distortion that may occur due to the impulse of the stepper motor. Antenna Circuit The receiver input is dimensioned for the normal use of a tuned ferrite antenna. An aerial or ferrite antenna can be used. However, a tuned input circuit has to be available where the throw antenna can be coupled onto it, either inductively or by means of a tap. Optimum signal-tonoise ratio is achieved for a resonant resistance of the antenna circuit of 00 to 00 k. However, using a resonant resistance of more than 00 k is disadvantageous due to internal and external interference sources. This is because the capacitive or inductive influential effect of an interference on the antenna circuit causes an interference voltage which is proportional to the resonant resistance, while the signal voltage generated by the transmitter field is proportional to the root of the resonant resistance. This means that when the resonant resistance is decreased, sensitivity is also decreased somewhat. It is more important in most cases, however, that the efficiency-to-noise ratio is improved than taking care of the input voltage only. 0 k is recommended as a standard value. The resonant Q factor of the ferrite antenna should be as high as possible as sensitivity increases proportionally to the root of the resonant Q factor and the suppression of interferences generated near the antenna is improved. Higher resonant Q factors can nevertheless be influenced in a negative way by temperature and environmental conditions. Therefore, resonant Q factor values of more than 0 are critical. To avoid serial resistances which reduce the Q factor, the antenna-circuit capacitor should be placed as close as possible to the antenna coil. Measuring the resonant resistance is complicated as the resonant circuit should neither be muted nor detuned by the measuring instrument. The resonant circuit can be activated without interference by a wire loop which is near the antenna rod. By using an indicator which has sufficiently high impedance and low capacitance (the test probe : of a typical oscillograph usually has M and approximately pf which is not sufficient), the resonant resistance R res can be determined by the resonant circuit capacitance, C, and a measurement of the bandwidth, b, to R res = / ( bc). Another method of defining the resonant resistance value is to halve the resonant voltage by parallel switching a resistor (the value has to be tested). The resistance is then equal to the resonant resistance. The resonant Q factor (Q = f res / b ) can be determined by the bandwidth, b, and the resonant frequency, f res. Application Figure 6 shows the dimensioning of the external components for European receiving conditions, i.e., for receiving the time-code signal DCF77 from Mainflingen/ Frankfurt a.m. Other transmitters, for example the American WWVB (60 khz) in Fort Collins, the English MSF (60 khz) in Teddington or the Japanese JGAS (0 khz) in Sanwa need different component layouts because their modulation differs from each other (see table ), and different crystals because their transmission frequency differs from each other. The crystal bandwidth can be influenced by the resistance R sb for different types of time-code frequencies

15 The crystal Q can be replaced by a capacitance of pf (respectively pf for 0 khz). This causes a loss in selectivity and somewhat sensitivity. Figure 6 shows a block diagram of the U3B with external circuitry for -bit decoding. Apart from the connections to the microprocessor, there is no difference with regard to circuitry between TCO decoding or -bit decoding. In order to avoid negative effects of the output pulses on the antenna circuit, the digital outputs are smoothed by nf each. Highest sensitivity is achieved by using an antenna which operates symmetrically. This means that a central tap of the antenna coil is connected with V CC instead of the connection shown in figure 6. Table 3. Transmitter Frequency C C C 3 C * R ÁÁÁÁÁÁ sb DCF ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ 77.5 khz 6. nf 33 nf nf 0 pf o ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ WWVB MSF 60 khz 5 nf 7 nf nf 0 pf k ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ 0 khz 60 pf 0 nf nf 0 pf ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ JGAS * = C improves the sensitivity in some designs to a certain extent nf nf Microprocessor 77.5 khz nf nf +VCC Ferrite antenna D 0 VCC ) IN IN ) C sometimes helpful ) TCO und IN only accessible in T3B D D D 3 TCO PON QB QA Analog-digital converter Stabilization Amplifier GND SB QA QB REC ) Rsb ) U3B Clock control INT Q C C C 0 p 6. n 33 n 77.5 khz REC INT DEC for JGAS R C 60 p M C 0 n Q Rectifier Decoder DEC SL CLK FLB FLA C 3 nf Figure 6. U3B with external circuitry for bit decoding Decoding Algorithm The T3B (T means chip form) offers two possibilities for decoding: The TCO (Time-Code Output) output and the -bit output. In the packaged IC U3B, only the -bit output is possible due to the pin number. The devices UB to U6B only have a TCO output. The signals of both outputs are basically generated by the current via the integrating capacitor C which is picked up by the input DEC of the decoder (figure 6). If the RF amplitude changes, the voltage at the capacitor C also changes because the variable gain amplifier is continuously self-regulating (see figure 7). During charging and decharging of the integrating capacitor C, positive and negative currents occur

16 These currents are transferred into a voltage which triggers the TCO via a comparator with hysteresis (Schmitt trigger). The Schmitt-trigger s output reflects the transmitter s modulation. The time constants of the system are adjusted so that the output voltage (which adjusts the amplification of the control amplifier) of the integrator at Pin INT follows the input signal within approximately 0. Figure 7 shows the reactions (modulation) on two pulses of approximately 0 and 00. After the input voltage decreases, the output voltage of the integrator increases rapidly and sets the control amplifier to a higher level of amplification until the previous signal level at the rectifier is reached once again. Then the process is repeated, but in the opposite direction. The current through the integration capacitor corresponds to the differential quote of the voltage and shows a positive and negative wave. The current is picked up from the decoder and fed to a Schmitt trigger. At the TCO, the Schmitt trigger generates high potential after a positive wave and low potential after a negative wave. At the -bit output, the integration converter splits up the current into 6 stages by means of an A/D converter. This enables better recognition of the modulation when interference or noise is present. A sequence of -bit values is fed to the microprocessor and analyzed with a special program. In this case, the decoding requires a very effective procedure and a powerful microcontroller with at least 3 k ROM and about byte RAM. By using TEMIC s software INCOR, the signal-to-noise ratio is improved by more than 6 db. Figure 7. Principle of dynamic procedures The Use of the TCO Signal In the following explanation it is assumed that the processor uses the TCO signal for decoding the time-code signal DCF77. The TCO output has to be checked regularly in order to recognize any changes. A sampling rate of 50 Hz 0 Hz is adequate enough to be able to differentiate clearly between the incoming pulse lengths of 0 and 00. When using the existing clock crystal of 376 Hz, a sampling rate of 6 Hz is recommended. First of all, a software meter which counts from 0 63 every second is synchronized with the rising slope of the TCO signal. Then, the rising slope is acknowledged by the internal clock and does not have to be observed any longer. Errors at the beginning of the slope are suppressed by this procedure. Before being able to begin with single-bit recognition, the beginning of a new minute has to be obtained from the input data. The modulation of DCF therefore ignores the 59th second pulse which is indicated by the absence of a TCO decrease. To verify this, the 0th pulse which should be 00 long can then be checked. When the minute-synchronization has been completed, single-bit recognition starts. Due to the internal / 6-s clocking, the program recognizes a slope of approximately 6. clocks as being logic 0 and a slope of approximately. clocks as being logic. The data sheet provides recommendations for the time windows to be used. Slopes outside the time window are caused by interferences and can be ignored. If there is no slope present then the time code can not be decoded and there has to be a pause to wait for the next minute to begin. After the end of a minute, the data of a complete time-code telegram has come in and the bit pattern generated can be converted into commands for controlling the display or the clock hand. In order to avoid a false display, the parity bits in the time-code telegram should also be checked. Best reception (as expected from a time-controlled watch) is guaranteed if the following time-code telegram is also decoded and compared with the one which has been decoded previously. Only if both time-code telegra differ by exactly a minute, will the result be accepted. If there are no correct results even from a longer receiving time of, for example, minutes, the receiver will be switched off and another attempt will be started after one or two hours. In current-critical applications, the decoding can only be started after a day has elapsed. The Use of the -Bit Output The use of a -bit output is more difficult than the use of the TCO signal. The microprocessor has to provide a -bit wide input port and an output lead for the clock signal. To suppress interferences caused by steep impulse slopes, the four signal leads should be blocked by capacitors

17 Every high-low transition of the clock signal starts a conversion of the ADU (6 conversions per second). The conversion is completed and the result can be read from the processor after at the very latest. With regard to the decoding process, there is no difference between -bit-and TCO-signal decoding. However, if -bit decoding is carried out, a 6-value sampling rate (instead of simple modulation changes) has to be analyzed. Then, according to the result, a decision has to be made whether the sequence corresponds to a short pulse, a long pulse or no pulse at all. TEMIC provides the customer with an effective decoding program, the INCOR software. Layout Example Figures and 9 show the design of a piggyback board (front side and reverse side). The layout contains the receiver IC U3B in an SO0L package for -bit decoding and a TEMIC MARC microcontroller. Depending on the programming, the processor can control an LCD display, the stepper motor of the clock hands etc. The connection for each application as well as for a keyboard is achieved by using the numerous pins. The supply voltage is 3 to 5 V (due to the microprocessor) and is fed to the reverse side. On the front side, a lowpass filter for the power supply of the receiver is applied with R v = k and C S =.7 F. The antenna supply is as short as possible and surrounded by shielding conductors (see figure 9). The connections of the filter crystals are also kept as short as possible. The output TCO and input INI are not available in this layout. In figures and 9, only a few important circuit elements are shown, the rest can be found by means of figure 6. The microcontroller M307EHP is used for controlling and signal evaluation. The clock signal CLK is fed to the receiver via a small capacitor of pf. This ensures that the slope s deviation at the receiver IC is only 0 mv which is sufficient for proper operation. At higher voltages, a distortion of the antenna circuit due to the bond wires can not be avoided. With a ferrite antenna of 0 mm, placed cm near to the board and with TEMIC s INCOR software, improved field sensitivity of more than V/ m is gained. This can be proven under laboratory conditions in the Faraday cage. In normal cases, a sensitivity value as mentioned above is not necessary, but the advantage of improved interference suppression is obvious. Rv k.7 n n n n sb R Q C C C p Figure. The front side of a board layout Figure 9. The reverse side of a board layout

18 U3B Time-Code Receiver with A/D Converter Description The U3B is a bipolar integrated straight-through receiver circuit in the frequency range of 0 to 0 khz. The device is designed for radio-controlled clock applications. Features Very low power consumption Very high sensitivity High selectivity by using two crystal filters Only a few external components necessary -bit digital output AGC hold mode Power-down mode available Block Diagram PON CLK D3 D D D e VCC GND Power supply ADC Decoder Impulse circuit 9 FLB FLA DEC IN AGC amplifier Rectifier & integrator 3 SL SB QA QB QA QB REC INT Figure. Rev. A3, 0-Jun-97

19 U3B Pin Description VCC 0 D0 (LSB) Pin Symbol Function VCC Supply voltage IN 9 D IN Amplifier Input 3 GND Ground GND 3 D SB Bandwidth control 5 QA Crystal filter SB 7 D3 (MSB) 6 QB Crystal filter 7 REC Rectifier output QA QB 5 6 U3B 6 5 PON QB INT Integrator output 9 DEC Decoder input FLA Lowpass filter FLB Lowpass filter REC 7 QA CLK Clock input for ADC 3 SL AGC hold mode INT 3 SL QA Crystal filter 5 QB Crystal filter DEC FLA 9 CLK FLB 6 PON Power ON/OFF control 7 D3 Data out MSB D Data out e 9 D Data out 0 D0 Data out LSB Figure. Pinning IN A ferrite antenna is connected between IN and VCC. For high sensitivity, the Q factor of the antenna circuit should be as high as possible. Please note that a high Q factor requires temperature compensation of the resonant frequency in most cases. Specifications are valid for Q>30. An optimal signal-to-noise ratio will be achieved by a resonant resistance of 50 to 00 k. VCC SB A resistor R SB is connected between SB and GND. It controls the bandwidth of the crystal filters. It is recommended: R SB = 0 for DCF 77.5 khz, R SB = k for 60 khz WWVB and R SB = open for JGAS 0 khz. 9 3 IN SB Figure Figure. GND Rev. A3, 0-Jun-97

20 U3B QA, QB In order to achieve a high selectivity, a crystal is connected between the pins QA and QB. It is used with the serial resonant frequency of the time-code transmitter (e.g., 60 khz WWVB, 77.5 khz DCF or 0 khz JGAS). The equivalent parallel capacitor of the filter crystal is internally compensated. The compensated value is about 0.7 pf. If full sensitivity and selectivity are not needed, the crystal filter can be substituted by a capacitor of pf. SL AGC hold mode: SL high (V SL = V CC ) sets normal function, SL low (V SL = 0) disconnects the rectifier and holds the voltage V INT at the integrator output and also the AGC amplifier gain. VCC SL QA QB 9 37 REC 9 3 Figure 5. GND Rectifier output and integrator input: The capacitor C between REC and INT is the lowpass filter of the rectifier and at the same time a damping element of the gain control INT Figure. Integrator output: The voltage V INT is the control voltage for the AGC. The capacitor C between INT and DEC defines the time constant of the integrator. The current through the capacitor is the input signal of the decoder Figure 6. REC GND Figure 9. INT GND DEC Decoder input: Senses the current through the integration capacitor C. The dynamic input resistance has a value of about 0 k and is low compared to the impedance of C. FLA, FLB Lowpass filter: A capacitor C 3 connected between FLA and FLB suppresses higher frequencies at the trigger circuit of the decoder. DEC FLB FLB GND Figure 7. Figure. Rev. A3, 0-Jun-97 3

21 U3B QA, QB According to QA/QB, a crystal is connected between the Pins QA and QB. It is used with the serial resonant frequency of the time-code transmitter (e.g., 60 khz WWVB, 77.5 khz DCF or 0 khz JGAS). The equivalent parallel capacitor of the filter crystal is internally compensated. The value of the compensation is about 0.7 pf. PON QA QB 9 33 GND Figure. If PON is connected to GND, the receiver will be activated. The set-up time is typically 0.5 s after applying GND at this pin. If PON is connected to VCC, the receiver will switch to power-down mode. A sequence of the digitalized time-code signal can be analyzed by a special noise-suppressing algorithm in order to increase the sensitivity and the signal-to-noise ratio (more than db compared to conventional decoding). Details about the time-code format are described separately. Decimal Gray VCC PON VCC PON D0... D3 Figure Figure 3. GND D0, D, D, D3 The outputs of the ADC consist of PNP-NPN push-pull stages and can be directly connected to a microcomputer. In order to avoid any interference of the output into the antenna circuit, we recommend terminating each digital output with a capacitor of nf. The digitalized signal of the ADC is Gray coded (see table). It should be taken into account that in power-down mode (PON = high), D0, D, D and D3 will be high. CLK The input of the ADC is switched to the AGC voltage by the rising slope of the clock. When conversion time has passed (about. at 5 C), the digitalized fieldstrength signal is stored in the output registers D0 to D3 as long as the clock is high and can be read by a microcomputer. The falling slope of the clock switches the input of the ADC to the time-code signal. In the meantime, the digitalized time-code signal is stored in the output registers D0 to D3 as long as the clock is low (see figure ). Rev. A3, 0-Jun-97

22 V clk mv t/ Now, the time-code signal can be read Falling edge initiates time-code conversion Now, the AGC value can be read Rising edge initiates AGC signal conversion Figure U3B Thus, the first step in designing the antenna circuit is to measure the bandwidth. Figure 7 shows an example for the test circuit. The RF signal is coupled into the bar antenna by inductive means, e.g., a wire loop. It can be measured by a simple oscilloscope using the : probe. The input capacitance of the probe, typically about pf, should be taken into consideration. By varying the frequency of the signal generator, the resonant frequency can be determined. RF signal generator 77.5 khz Probe : M Scope In order to minimize interferences, we recommend a voltage swing of about 0 mv. A full supply-voltage swing is possible but reduces the sensitivity. VCC CLK GND Figure Please note: The signals and voltages at the Pins REC, INT, FLA, FLB, QA, QB, QA and QB cannot be measured by standard measurement equipment due to very high internal impedances. For the same reason, the PCB should be protected against surface humidity. Design Hints for the Ferrite Antenna The bar antenna is a very critical device of the complete clock receiver. Observing some basic RF design rules helps to avoid possible proble. The IC requires a resonant resistance of 50 k to 00 k. This can be achieved by a variation of the L/C-relation in the antenna circuit. It is not easy to measure such high resistances in the RF region. A more convenient way is to distinguish between the different bandwidths of the antenna circuit and to calculate the resonant resistance afterwards. wire loop C res Figure e At the point where the voltage of the RF signal at the probe drops by 3 db, the two frequencies can then be measured. The difference between these two frequencies is called the bandwidth BW A of the antenna circuit. As the value of the capacitor C res in the antenna circuit is known, it is easy to compute the resonant resistance according to the following formula: R res BW A C res where R res is the resonant resistance, BW A is the measured bandwidth (in Hz) C res is the value of the capacitor in the antenna circuit (in Farad). If high inductance values and low capacitor values are used, the additional parasitic capacitances of the coil (0 pf) must be considered. The Q value of the capacitor should be no problem if a high Q type is used. The Q value of the coil differs more or less from the DC resistance of the wire. Skin effects can be observed but do not dominate. Therefore, it should not be a problem to achieve the recommended values of the resonant resistance. The use of thicker wire increases the Q value and accordingly reduces bandwidth. This is advantageous in order to improve reception in noisy areas. On the other hand, temperature compensation of the resonant frequency might become a problem if the bandwidth of the antenna circuit is low compared to the temperature variation of the resonant frequency. Of course, the Q value can also be reduced by a parallel resistor. Rev. A3, 0-Jun-97 5

23 U3B Temperature compensation of the resonant frequency is a must if the clock is used at different temperatures. Please ask your supplier of bar antenna material and of capacitors for specified values of the temperature coefficient. Furthermore, some critical parasitics have to be considered. These are shortened loops (e.g., in the ground line of the PCB board) close to the antenna and undesired loops in the antenna circuit. Shortened loops decrease the Q value of the circuit. They have the same effect like conducting plates close to the antenna. To avoid undesired loops in the antenna circuit, it is recommended to mount the capacitor C res as close as possible to the antenna coil or to use a twisted wire for the antenna-coil connection. This twisted line is also necessary to reduce feedback of noise from the microprocessor to the IC input. Long connection lines must be shielded. A final adjustment of the time-code receiver can be carried out by pushing the coil along the bar antenna. The maximum of the integrator output voltage V INT at Pin INT indicates the resonant point. But attention: The load current should not exceed na, that means an input resistance G of the measuring device is required. Therefore, a special DVM or an isolation amplifier is necessary. Absolute Maximum Ratings Parameters Symbol Value Unit Supply voltage V CC 5.5 V Ambient temperature range T amb 5 to +75 C Storage temperature range R stg 0 to +5 C Junction temperature T j 5 C Electrostatic handling ± V ESD 000 V (MIL Standard 3 D), except Pins 5, 6, and 5 Thermal Resistance Parameters Symbol Maximum Unit Thermal resistance R thja 70 K/W Electrical Characteristics V CC = 3 V, reference point Pin 3, input signal frequency 0 khz, T amb = 5 C, unless otherwise specified Parameters Test Conditions / Pin Symbol Min Typ Max Unit Supply voltage range Pin V CC. 5.5 V Supply current Pin Without reception signal I CC 30 A with reception signal = 00 V OFF mode A A Set-up time after V CC ON V CC =.5 V t s AGC amplifier input; IN Pin Reception frequency range f in 0 0 khz Minimum input voltage R res = 0 k, Q res > 30 V in.5 V Maximum input voltage V in 0 0 mv Input capacitance to GND C in.5 pf 6 Rev. A3, 0-Jun-97

24 U3B 3 Parameters Test Conditions / Pin Symbol Min Typ Max Unit ADC; D0, D, D, D3 Pins 7,, 9 and 0 Output voltage HIGH R LOAD = 70 k to GND V OH V CC -0. V LOW R LOAD = 650 k to VCC V OL 0. V Output current HIGH V TCO = V CC / I SOURCE LOW V TCO = V CC / I SINK Input current into DEC Falling slope of CLK I decs 3 5 na (first bit) Input current into DEC Falling slope of CLK I dece 35 na (last bit) Input current into DEC Falling slope of CLK I decst.75 7 na (step range) Input voltage at IN (first bit) RF generator at IN, without modulation rising slope of CLK V min dbv Input voltage at IN (last bit) RF generator at IN, without modulation rising slope of CLK V max 60 dbv Input voltage at IN (step range) RF generator at IN, without modulation rising slope of CLK V step.7 dbv Clock input; CLK Pin Input voltage swing V swing 50 0 V CC mv Clock frequency f clk 0 5 Hz Dynamical input resistance R dyn. 0 k Power-ON/OFF control; PON Pin 6 Input voltage HIGH Required I IN 0.5 A V CC -0. V LOW V CC -. V Input current V CC = 3 V V CC =.5 V V CC = 5 V I IN A A A Set-up time after PON t 0.5 s AGC hold mode; SL Pin 3 Input voltage HIGH Required I IN 0.5 A V CC -0. V LOW V CC -. V Input current V in = V CC 0. A V in = GND.5 A Rejection of interference signals 7f d f ud 7 = 65 Hz V d = 3 V, f d = 77.5 khz using crystal filters using crystal filter a f 3 a f db db Rev. A3, 0-Jun-97 7

25 U3B Test Circuit (for Fundamental Function) Vd.657V 300k 300k 300k 300k Ipon Test point: DVM with high and low input line for measuring a voltage Vxx or a current Ixx by conversion into a voltage Sd0 Sd Sd Sd3 Vd0 Vd Vd Vd3 Spon M p M Isl D D3 PON QB QA Ssl Ivcc D D0 0k VCC ANALOG DIGITAL CONVERTER STABILISATION ÎÎÎÎ U3B TIME CONTROL DECODING SL CLK FLB M Iclk Vclk Iin FLA Sdec M M IN AGC AMPLIFIER RECTIFIER DEC 0M Idec GND SB QA QB REC INT Vcc 3V ~ Vin Ssb p Vrec 60p 3.3n Srec Sint 0k Vdec Vsb M M M Vint Isb Irec Vrec Iint Vint 9 99 Figure 7. Rev. A3, 0-Jun-97