TI Designs: Verified Design Isolated Auto-Polarity RS-485 Transceiver

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1 TI esigns: Verified esign Isolated Auto-Polarity S-485 Transceiver TI esigns TI esigns are analog solutions created by TI s analog experts. Verified esigns offer theory, component selection, simulation, complete PCB schematic and layout, bill of materials and measured performance of useful circuits. Circuit escription This reference design demonstrates an isolated S- 485 bus node with automatic correction of a reversed bus signal polarity caused by cross-wire faults. The design provides transient protection protecting the signal path against ES, EFT, and surge transients specified in the IEC 6000 family of transient immunity standards. esign esources esign Archive SN65HV888 ISO764FM SN650 TPS7650 All esign Files Product Folder Product Folder Product Folder Product Folder An isolated C-C converter provides power supply across the isolation barrier utilizing the push-pull converter principle. Ask The Analog Experts WEBENCH esign Center V IN GN GN V CC GN ISO-BAIE IN OUT GN EN FB V CC SN650 TPS7650 V CC V CC V CC V CC EN EN V CC V CC V CC GN GN V CC /E GN V CC E GN /E E A B GN GN SN65HV888 ISO764FM An IMPOTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and other important disclaimers and information. TINA-TI is a trademark of Texas Instruments WEBENCH is a registered trademark of Texas Instruments TIU40-June 04 Isolated Auto-Polarity S-485 Transceiver Copyright 04, Texas Instruments Incorporated

2 esign Summary The S-485 transceiver node is designed to meet the following specifications: 6kV peak isolation IEC up to 6kV IEC up to 4kV IEC up to kv ata rate up to 50kbps esign Considerations. S-485 Transceiver The SN65HV888 is a low-power S-485 transceiver with bus-polarity correction and transient protection. Upon hot plug-in the device detects and corrects the bus polarity within the first 76ms of bus idling. Onchip transient protection protects the device against IEC 6000 ES and EFT transients. The device automatically corrects a wrong bus signal polarity caused by a cross-wire fault. In order to detect the bus polarity, all three of the following conditions must be met: A failsafe biasing network (commonly at the master node) that defines the signal polarity of the bus, A slave node must have its receiver enabled and its driver disabled (/E = E = low), The bus must be idling for the failsafe time, t FS-max. After the failsafe time has passed, the polarity correction is complete and applied to both receive and transmit data. The status of the bus polarity is latched within the transceiver and maintained for all following data transmissions. That is, switching between drive and receive mode will not reset the bus polarity status. x I Tx E E V S-Master Vcc Master node A B V SM FS T (opt.) FS Slave node A B V S-Slave Vcc POLCO E E x I Tx GN GN Figure : Point-to-point data link with cross-wire fault Figure shows a simple point-to-point data link between a master and a slave node. Because the failsafe biasing network at the master node determines the signal polarity on the bus, a standard S-485 transceiver without polarity correction, such as the SN65HV8, may be used as a master. All slave nodes, however, require the SN65HV888 transceiver with polarity correction. Isolated Auto-Polarity S-485 Transceiver TIU40-June 04-evised June 04 Copyright 04, Texas Instruments Incorporated

3 Im Master signals m high Z VAm 0V VFS -Vod +Vod VBm VBs 0V VFS +Vid -Vid VAs Slave signals VSs Is low s tfs Undetermined output Corrected output: is reversed due to wrong VI polarity Figure : Polarity correcting timing prior to data transmission Figure shows the timing diagram for the transceiver control and bus terminals during polarity correction. uring power-up a slave node with polarity correction can assume correct or incorrect bus polarity. Following power-up, a bus-idle period of 76ms must pass in order for the slave to detect the correct polarity status. uring bus-idling, the slave receiver detects the reversed polarity of the bus failsafe voltage and, after the maximum correction time of t FS-max = 76ms, turns S high. From this point on all incoming bus data with reversed polarity are reversed within the transceiver. Because polarity correction is also applied to the transmit path, the data sent by the slave MCU are reversed by the POLCO logic and then fed into the driver. The reversed data from the slave node are reversed again by the cross-wiring fault in the bus, and the correct bus signal polarity is reestablished at the master end. Long strings of ones and zeros exceeding the minimum polarity correction time of 44ms can also trigger a polarity correction. In order to prevent such incidents, it is recommended to include encoding /decoding schemes to the data stream. Typical coding schemes are clock-encoded, such as Manchester coding, or simply add/subtract fixed data patterns to and from the transmit data. If a slave node is plugged in during an ongoing data transmission, the polarity status is undetermined, and the receiver output may provide correct or incorrect data. In order to allow for hot plug-in, a bus-idle period of 76ms between transmissions is advised. TIU40-June 04-evised June 04 Isolated Auto-Polarity S-485 Transceiver Copyright 04, Texas Instruments Incorporated

4 . igital Isolator The control side of the SN65HV888 is isolated from the node controller via a four-channel, digital isolator, ISO764FM, providing up to 6kV peak isolation. This isolator utilizes capacitive isolation with silicon dioxide (SiO ) as dielectric. igital capacitive isolators are industry s most reliable and most precise, lowpower isolators.. Transient Protection The SM7 transient voltage suppressor (TVS) provides ES, EFT, and Surge protection for data ports meeting IEC (ES), IEC (EFT), and IEC (Surge) requirements. The device comprises two bidirectional TVS diodes rated for 400W peak power at an 8/0 µs peak pulse current of 7A. Its high clamping voltage of 6V, however, can trigger the internal ES diode structure of the transceiver. When this happens, the internal ES structure shunts the external TVS and absorbs the entire transient energy. This can lead to latch-up and transceiver damage. To prevent this from happening, 0Ω, pulseproof, thick-film resistors are inserted between the TVS diodes and the transceiver A and B bus terminals. These resistors provide sufficient voltage drop during a transient event to maintain the external TVS turned on. A high-voltage capacitor (C8) provides an AC connection between ISO-ground and Protective-Earth (PE). Implemented here as a banana jack, this allows for the connection of a low-inductance cable between the surge generator and ground. The high-impedance resistor (0) parallel to C8 functions as a bleeder resistor to prevent the build-up of electrostatic charges on the bus lines..4 Power Supply The isolated C-C power supply converter utilizes the push-pull converter principle. The transformer driver SN650 drives an isolated transformer with center-tap. The transformer output is rectified by two Schottky diodes (, ) and capacitor (C). The subsequent low dropout regulator, TPS7650, provides a regulated 5V output for up to 50mA output current. For best stability and lowest ripple, a low-es, 4.7µF ceramic capacitor (C4) buffers the regulator output. 4 Isolated Auto-Polarity S-485 Transceiver TIU40-June 04-evised June 04 Copyright 04, Texas Instruments Incorporated

5 Measurement. ata Transmission Bus Figure : Eye diagram - 50kbps at 000m Bus Figure 4: Eye diagram - 50kbps at 00m TIU40-June 04-evised June 04 Isolated Auto-Polarity S-485 Transceiver 5 Copyright 04, Texas Instruments Incorporated

6 . Polarity Correction Bus +V O Bus +V O V CC (slave) V CC (slave) (slave) t FS (slave) Figure 5: Polarity correction with (left) and without (right) cross-wire fault 6 Isolated Auto-Polarity S-485 Transceiver TIU40-June 04-evised June 04 Copyright 04, Texas Instruments Incorporated

7 4 PCB esign Figure 6: PCB layout top Figure 7: PCB layout ground TIU40-June 04-evised June 04 Isolated Auto-Polarity S-485 Transceiver 7 Copyright 04, Texas Instruments Incorporated

8 Figure 8: PCB layout power Figure 9: PCB layout bottom 8 Isolated Auto-Polarity S-485 Transceiver TIU40-June 04-evised June 04 Copyright 04, Texas Instruments Incorporated

9 5 eferences. The S-485 esign Guide, Kugelstadt 008, SLLA7B 6 Appendix 6. Schematic VIN TB VIN C uf VIN C Terminal Block x uf U T U GN VCC IN OUT 4 MB050L GN C4 C EN FB/NC uF SN650 uf TPS GN GN VCC :. MB050L GN JMP VIN Header x JMP JMP 4 Header 4x VIN Header x NI 4 5 NI E /E VIN k C5 0.uF U VCC 4 INA 5 INB 6 INC 7 OUT 8 EN C6 0.uF GN ISO784 GN 6 VCC 5 GN OUTA 4 OUTB OUTC IN 0 EN 9 GN VCC k GN GN GN 0 M 00 C k GN 0.uF U 8 VCC 7 /E B 6 4 E A 5 GN SN65HV k GN J BLK PE C8 4.7n VCC VCC GN TVS GN GN GN 4 JMP4 Header 4x GN Figure 0: Isolated auto-polarity S-485 transceiver schematic TIU40-June 04-evised June 04 Isolated Auto-Polarity S-485 Transceiver 9 Copyright 04, Texas Instruments Incorporated

10 6. Bill of Materials Table : Isolated auto-polarity S-485 transceiver Bill of Materials Item Quantity eference Part Footprint Manufacturer Manufacturer Part Number C.0µF 040 Taiyo Yuden LMK05BJ05KV-F C.0µF TK Corporation C608X7C05K C.0µF TK Corporation C608X7C05K 4 C4 4.7µF TK Corporation C608X50J475K/ C5, C6, C7 0.µF Murata Electronics North America GM887H04KA9 6 C8 4700pF 8 Novacap 8B47K0NT 7, MB050LTG SO- ON Semiconductor MB050LTG 8 CSO-T4C-SL SOT-- Bourns Inc CSOT-SM7 9 6 JMP, JMP HTSW G-S 0." Samtec Inc HTSW G-S 0 8 JMP, JMP4 HTSW G-S 0." Samtec Inc HTSW G-S J Banana Jack BLACK 4 MM Alectron ST-5B BLACK, 560 Venkel C-0W-5600FT 0 Panasonic Electronic Components EJ-EKF00V 4 4, 5 NI NI NI NI 5 6, 7 0 Vishay ale CCW00FKEAHP 6 8, K ohm Semiconductor MC0ETF M 00 Vishay ale CCW00M00FKEF 8,.00K Yageo CF-07KL 9 TB Pin Female /A.54mm TE Connectivity T :. SMT Wurth Electronics U ISO764FMW 6-SOIC Texas Instruments ISO764FMW U SN65HV888 8-SOIC Texas Instruments SN65HV888 U SN650BV SOT--5 Texas Instruments SN650BV 4 U4 TPS7650BV SOT--5 Texas Instruments TPS7650BV 0 Isolated Auto-Polarity S-485 Transceiver TIU40-June 04-evised June 04 Copyright 04, Texas Instruments Incorporated

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