SEPIC, added CC charging by additional current ctr ( via TLC272) TPS40210 and CSD18563Q5A

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1 1 Startup 3 2 Shutdown 5 3 Efficiency 7 4 Load Regulation 8 5 Line Regulation 9 6 Output Ripple Voltage 10 7 Input Ripple Voltage 10 8 Load Transients 11 9 Control Loop Frequency Response Resistive Load Ah Battery Load Miscellaneous Waveforms Switchnode (drain-source) Gate to Source Voltage D3 (referenced to VOUT) Thermal Image 26 Topology: Device: SEPIC, added CC charging by additional current ctr ( via TLC272) TPS40210 and CSD18563Q5A Unless otherwise indicated, resistive load was applied, load current was set to 1.5A; For charger verification battery YUASA NP 5-12 (= 12V, 5Ah, AGM) was used; here load current has been set to 1.0A 20%). Static measurements: Fsw 302kHz OK ON 8.8V OK OFF 7.6V OK Page 1 of 26

2 Picture A shows the 20W SEPIC power stage controlled by TPS40210 and driven by CSD18563: Picture B shows the test setup electronic load, resistive load and here - lead acid battery 5Ah: Page 2 of 26

3 1 Startup The CV startup waveform is shown in the Figure 1. The input voltage was set to 9V, Css 220nF. Ch1=> input voltage Ch2=> output voltage 10ms/div 20MHz bw Figure 1 The CV startup waveform is shown in the Figure 2. The input voltage was set to 24V. Ch1=> input voltage 10V/div Ch2=> output voltage 10ms/div 20MHz bw Figure 2 Page 3 of 26

4 The CV startup waveform is shown in the Figure 3. The input voltage was set to 36V. Ch1=> input voltage 10V/div Ch2=> output voltage 10ms/div 20MHz bw Figure 3 Page 4 of 26

5 2 Shutdown The CV shutdown waveform is shown in the Figure 4. The input voltage was set to 9V. The power supply was disconnected. Ch1=> input voltage Ch2=> output voltage 5ms/div 20MHz bw Figure 4 The CV shutdown waveform is shown in the Figure 5. The input voltage was set to 24V. The power supply was disconnected. Ch1=> input voltage 10V/div Ch2=> output voltage 5ms/div 20MHz bw Figure 5 Page 5 of 26

6 The CV shutdown waveform is shown in the Figure 6. The input voltage was set to 36V. The power supply was disconnected. Ch1=> input voltage 10V/div Ch2=> output voltage 5ms/div 20MHz bw Figure 6 Page 6 of 26

7 3 Efficiency The CV efficiency is shown in the Figure 7 below. The input voltage was set to 9V, 24V and 36V (resistive load). Figure 7 Page 7 of 26

8 4 Load Regulation The CV load regulation of the output is shown in the Figure 8 below. The input voltage was set to 9V, 24V and 36V (resistive load). Figure 8 Page 8 of 26

9 5 Line Regulation The CV line regulation is shown in Figure 9. The output current was set about 1.5A. Figure 9 With the same setup efficiencies were calculated. This is shown in Figure 10 Figure 10 Page 9 of 26

full bw 1µs/div 7 Input Ripple Voltage The input ripple voltage is shown in Figure 12.

10 6 Output Ripple Voltage The CV output ripple voltage at full load 1.5A is shown in Figure 11. output ripple with 36V Vin Ch2 => output ripple with 24V Vin Ch3 => output ripple with 9V Vin 50mV/div AC coupled full bw 1µs/div 7 Input Ripple Voltage The input ripple voltage is shown in Figure 12. Figure 11 input ripple with 36V Vin Ch2 => input ripple with 24V Vin Ch3 => input ripple with 9V Vin 50mV/div AC coupled 20MHz bw 1µs/div Figure 12 Page 10 of 26

11 8 Load Transients The Figure 13 shows the response to load transients with 9V input voltage. The load is switching from 0.75A to 1.5A with 30Hz. N3305 load was used. output voltage 50mA/div AC coupling Ch2 => output current 500mA/div 20MHz bw 5ms/div Figure 13 The Figure 14 shows the response to load transients with 24V input voltage. The load is switching from 0.75A to 1.5A with a frequency of 30Hz (load N3305A). output voltage 50mV/div AC coupled Ch2 => output current 500mA/div 20MHz bw 5ms/div Figure 14 Page 11 of 26

12 The Figure 15 shows the response to load transients with 36V input voltage. The load is switching from 0.75A to 1.5A with a frequency of 30Hz. (N3305 load) output voltage 50mV/div AC coupled Ch2 => output current 500mA/div 20MHz bw 5ms/div Figure 15 Page 12 of 26

13 9 Control Loop Frequency Response Input voltage was set worst case to 9V input, so at maximum duty cycle RHPZ is lowest. 9.1 Resistive Load Figure 16 shows the closed loop voltage controlled = CV at a load current of 500mA. Figure 16 Figure 17 shows the closed loop current controlled = CC at a load current of 1A. Figure 17 Page 13 of 26

9.2 True C/V Battery Loading @ 12V 5Ah Figure 18, first - current controlled loading at 1A constant current, voltage rises:

14 9.2 True C/V Battery 12V 5Ah Figure 18, first - current controlled loading at 1A constant current, voltage rises: Figure 18 Figure 19, second transfer current control to voltage control, loading now at 13.8V/700mA Figure 19 Page 14 of 26

15 Figure 20, further voltage control, charging current drops, shown 700mA 200mA 70mA Figure 20 Figure 21 shows comparison voltage control (ye/or) and current control 900mA (rd/bl) Figure 21 Page 15 of 26

16 Table summarizes the results of the Bode measurements: R Load 5Ah Battery Vin V ctrl I ctr I ctr Vctrl V ctr Bandwidth (Hz) Phase margin slope (20dB/decade) (1000mA) (900mA) (700mA) gain margin (db) slope (20dB/decade) freq (Hz) Table 1 Vin V ctrl 700mA 5Ah Battery Vctr 200mA V ctr 70mA Bandwidth (Hz) Phase margin slope (20dB/decade) Table 2 CC/CV loading has been verified at true battery; current control charges battery with constant current set point 1000mA and voltage at battery increases = CC loading. Touching the voltage set point at 13.8V voltage control takes over and charges the battery further at constant voltage 13.8V while current drops continuously = CV loading. Continuously load current decreases to 5mA holdup current. Page 16 of 26

17 10 Miscellaneous Waveforms 10.1 Switchnode (drain-source) The waveform of the voltage on switchnode (drain to source) is shown in Figure 22. Input voltage was set to 9V. 500ns/div full bandwidth 20ns/div Figure 22 Page 17 of 26

18 The waveform of the voltage on switchnode (drain to source) is shown in Figure 23. Input voltage was set to 24V. 10V/div 500ns/div full bandwidth 10V/div 20ns/div Figure 23 Page 18 of 26

19 The waveform of the voltage on switchnode (drain to source) is shown in Figure 24. Input voltage was set to 36V. 500ns/div full bandwidth 20ns/div Figure 24 Page 19 of 26

20 10.2 Gate to Source The waveform of the voltage on the gate to source is shown in Fig. 25. Input voltage was set to 9V. 2V/div 500ns/div full bandwidth 2V/div 20ns/div Figure 25 Page 20 of 26

21 The waveform of the voltage on gate to source is shown in Figure 26. Input voltage was set to 24V. 2V/div 500ns/div full bandwidth 2V/div 20ns/div Figure 26 Page 21 of 26

22 The waveform of the voltage on gate to source is shown in Figure 27. Input voltage was set to 36V. 2V/div 500ns/div full bandwidth 2V/div 20ns/div Figure 27 Page 22 of 26

23 10.3 Voltage D3 (referenced to VOUT) The waveform of the voltage is shown in Figure 28. Input voltage was set to 9V. 500ns/div full bandwidth 20ns/div Figure 28 Page 23 of 26

24 The waveform of the voltage is shown in Figure 29. Input voltage was set to 24V. 10V/div 500ns/div full bandwidth 10V/div 20ns/div Figure 29 Page 24 of 26

25 The waveform of the voltage is shown in Figure 30. Input voltage was set to 36V. 10V/div 500ns/div full bandwidth 10V/div 20ns/div Figure 30 Page 25 of 26

26 11 Thermal Image Figure 31 shows the thermal image at 24V input voltage and full load 1.5A for >1hr. Figure 31 Name D3 L2 R14 R13 Q2 Temperature 58.0 C 56.1 C 53.0 C 54.3 C 52.3 C Page 26 of 26

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Topology: Active Clamp Forward Device: UCC2897A Unless otherwise mentioned the measurements were done with about 2A output current.

Topology: Active Clamp Forward Device: UCC2897A Unless otherwise mentioned the measurements were done with about 2A output current. 1 Startup... 2 2 Shutdown... 4 3 Efficiency... 6 4 Load Regulation... 7 5 Line Regulation... 8 6 Output Ripple Voltage... 9 7 Input Ripple Voltage... 10 8 Load Transients... 11 9 Control Loop Frequency