CMOS Integrated Transformers: Coming of Age

Transcription

1 CMOS Integrated Transformers: Coming of Age D. J. Allstot et. al. Department of Electrical Engineering, University of Washington, Seattle WA 98195, USA * allstot@u.washington.edu Abstract This paper presents a survey of some of the currently active research areas involving the use of transformers in CMOS technology. A brief review of transformer concepts and topologies is given, followed by discussions on the use of transformers for power and area reduction, bandwidth enhancement, and modeling issues. Finally, conclusions are drawn on future research directions for the use of transformers in CMOS circuit design. (a) (b) 1. Introduction The rapid growth of wireless applications has led to a growth in the demand for low cost radio frequency (RF) integrated circuits. The scaling of CMOS technology has enabled increases in operating frequencies, making CMOS implementations viable in domains previously dominated by high performance semiconductors. As the speed of CMOS transistors has increased to rival high performance semiconductors, integrated passive components in CMOS have lagged behind. This is due to the conductive silicon substrate which leads to higher losses than processes with insulating substrates (e.g., GaAs). Another handicap in scaled CMOS is the low supply voltage which results in reduced headroom and signal swings. These impairments necessitate the development of new design techniques to allow CMOS to rival the performance of more expensive processes. One technique that has emerged in recent years is the use of monolithic transformers in CMOS. Transformers have been used VCOs to enable low voltage operation (4), in mixers for reductions in power consumption and noise figure (5), and in LNAs for reductions in power consumption (2), and noise figure (7). Transformers have also been employed in bandpass filters (8) for Q-enhancement, and they are commonly used in passive circuits such as impedance transformation networks and integrated baluns (10). 2. Monolithic Transformers A transformer is a magnetically coupled system of one or more inductors. For the simplest case of two inductors, they are referred to as the primary and secondary coils. For an ideal 1:n transformer, n refers to the secondary-to-primary turns ratio, and the magnetic flux coupling between the inductors causes a changing voltage across the primary to generate n times the voltage across the secondary. A real transformer has (c) Fig. 1 Monolithic transformer configurations include (a) tapped, (b) interleaved, (c) stacked and (d) series-parallel interleaved. imperfect flux coupling, and the coupling coefficient is defined as k 2 = M 2 /L 1L 2 where M is the mutual inductance and L 1 and L 2 are the self inductances of the primary and secondary coils. A number of topologies have been proposed for monolithic inductors, and the most common ones are illustrated in Fig. 1. The tapped transformer in Fig. 1 (a) uses separate regions for the two inductors to minimize the port-to-port capacitance and allow a high resonant frequency at the cost of a lower coupling coefficient. The interleaved transformer in Fig. 1(b) permits higher coupling at the cost of reduced self-inductance. The stacked transformer in Fig. 1(c) uses additional metal layers to exploit both vertical and lateral magnetic coupling, enabling high self-inductance and coupling at the cost of a low self-resonant frequency. The self-resonant frequency of this design can be improved by increasing the vertical coil separation (12). The series-parallel interleaved topology is shown in Fig. 1(d). A number of comprehensive overviews on monolithic CMOS transformers have been published (13, 14) covering analysis and modeling techniques such as multi-section lumped element models, compact models, 3-D electro-magnetic field solvers, and custom CAD tools such as ASITIC (14). 3. Circuit Applications of Monolithic Transformers A. gm-boosted LNA Poor noise and gain performance have traditionally (d)

2 limited the use of CMOS common-gate LNA, in spite of good linearity, stability, robustness, and lower power consumption. A 1:n transformer (e.g., Fig. 1(d)) can be utilized to couple the source to the gate (Fig. 2), realizing an inverting gain proportional to nk, and boosting the effective g m by (1nk). The current consumption is further reduced by (1nk), and the noise performance is improved notably [7]. Assuming k=1 and an optimal turns-ratio of ω T 5γ ( ) 2 n = opt 1 ω δα, the noise factor for this g m-boosted LNA is: ω ( ) δγ F opt 1 2, 5 ω T a significant improvement over the conventional common-gate LNA, ( ) 2 γ δα F = 1 ω. α 5 ω T Losses associated with the parasitics and the self-resonant frequency limit the turn-ratio to 2~3 [15]. the weight amplifiers (WA) of Fig. 3(b) and produce current outputs. Currents from the WA s in each channel are summed to combine the antenna signals. This current must be coupled into the coupled into I and Q Gilbert mixers. Although this may be accomplished by an all-transistor approach at the cost of an additional I-V and a V-I conversion, the use of the transformer obviates this, and also facilitates operation at a low supply voltage of 1.4V. The combined current is fed into the 4-turn primary and appears at the symmetric 2-turn secondaries, whose outputs in turn are fed directly into the Gilbert quad. The supply voltage of the WA s is provided through the center-tap of the primary while the center-taps of the secondaries are used to provide bias currents to the mixer. This structure was evaluated through EM simulations, and a compact model was generated similar to that discussed in Section 5. A r1 A i1 A r2 - x IF(t) A i2 (a) Fig. 2 (a) A g m-boosted common-gate LNA B. The Cartesian Combiner for a Beamforming Receiver Multiple-antenna techniques (MIMO) are expected to be a key element in all upcoming wireless systems. The three broad classes of MIMO systems use spatial multiplexing, spatial diversity or beamforming. A CMOS-friendly, area and power-efficient solution for the latter two forms is presented in (15) and uses a multi-layer, multi-winding transformer to achieve low-voltage operation in a 90nm CMOS process. The operation of the multi-antenna combiner of Fig. 3 is described by: xi () t = x() t Ar cos( 2π flot) Ai sin( 2π flot) xq () t = x() t Ai cos( 2π flot) Ar sin( 2π flot) j2 flot xif () t = x() t ( Ar jai ) e π which indicates that the each complex weight can be realized using two VGA s followed by a quadrature downconversion. The magnitude and phase of the weight are given by 2 2 A = A r A i and 1 A= tan ( Ai Ar) respectively, which is the signal processing functionality to implement the beamforming function. The programmable weights Ar and Ai are implemented using LO I Weight Amplifier #1 Weight Amplifier #2 LO Q (b) Fig. 3 (a) The Cartesian beamforming receiver and (b) low-voltage circuit implementation of the dashed portion using a transformer. C. Matching in Power Amplifiers Transformers have proven to be very effective for use in power amplifiers in applications such as biasing, matching, unbalanced-to-balanced conversion and signal combination [16, 27]. Fig. 5 illustrates a power amplifier utilizing two monolithic transformers, one located at the input to the driver and one located interstage, between the driver and the output stage. The transformers are acting in all of the aforementioned roles; for brevity only the matching role will now be discussed.

3 Primary (M7) Secondaries (M5-M4 shunt) S1 S2 P1 S3 P3 140µm P2 S=4µm W=6µm T1 T3 T2 constant for a given power, a popular method to increase the BW while maintaining the gain is to use inductive peaking techniques [9]. A conventional peaking technique that gives a large BW extension ratio (BWER) is bridged T-coil (BTC) peaking, which utilizes a symmetric transformer. Fig. 6(a) shows a common-source amplifier with BTC peaking. Neglecting the drain parasitic capacitance (C 1), the un-peaked BW of the amplifier (ω 0) is 1/RC 2, where R is the load resistance, and C 2 is the load capacitance. Choosing L = 3R 2 C 2/8, k = -1/3, and C B = C 2/8 gives a Butterworth response and a theoretical BWER of Fig. 4 Structural details of the transformer Fig. 5 Integrated silicon PA block diagram Typically the input impedance of a power transistor is small (<50 Ω), due to the fact that the power transistor consists of several devices connected in parallel, thus in order for the transformer to provide matching it must have a turns ratio, n, less than unity. Several structures have been proposed which will provide non-unity turns ratios, such as the multi-layer, the tapped transformer, and the series-parallel interleaved [27], as shown in Fig. 1. In the case of power-amplifiers, it is most desirable to use an interleaved transformer, because the coupling and insertion loss are better than the tapped transformer, while the self-resonant frequency is typically larger than the multi-layer transformer. The drawback to using such structures is that the winding inductance is only a few hundred ph, and thus must be resonated with a shunt capacitor, such as C 1 in Fig. 5. The capacitor can absorb the parasitic capacitance associated with the input of the power transistor it is driving. Due to the relatively low Q of the transformer a bandwidth of several GHz is possible at microwave frequencies (17, 27). It is noted that lumped spiral transformers, such as the series-parallel interleaved structure, are too lossy to be used at the output of a power amplifier thus other approaches, such as the distributed active transformer, are necessary (16). D. Bandwidth Enhancement The design of wideband amplifiers for high-speed transmitters and receivers involves three critical challenges: large bandwidth (BW), high gain, and low power. As the gain-bw product for an amplifier stays Fig. 6 (a) A BTC-peaked amplifier (b) An ATC-peaked amplifier. Unfortunately, in most cases, the drain capacitance (C 1) is not negligible and BTC peaking fails to give the desired BW improvement. However, by actually incorporating C 1 into the design, and by using an asymmetric (1: n) T-coil (ATC), a BWER of more than 4 is possible through optimum capacitor-splitting and magnetic-coupling [S-3]. Capacitor splitting is achieved through C 1 (Fig. 6(b)) the transistor initially charges only the smaller capacitance (C 1) which leads to a faster rise-time and a higher BW. By properly sizing the transformer (L 1 L 2), the current flow due to the magnetic coupling is further optimized. Figure 8 shows the layout of an ATC used in the design of an ATC-peaked differential amplifier [S-3] with a measured BW of 10.4GHz, and a BWER of 4.1. P Fig. 7 Layout of an asymmetrical T-coil T E. Transformer couplers in image rejection circuits The tradeoff between image rejection and channel selection in heterodyne RF receivers causes difficulties in both frequency planning and circuit design. Image-reject mixing is one of techniques to relax this tradeoff. The challenge is to improve the image rejection S

4 without compromising other performance parameters. Image-reject mixing requires a quadrature mixer for downconverting the input signal, wherein the outputs at four different phases are combined in a way to distinguish between the desired and image signals. The image-rejection performance of the mixer strongly depends on the amplitude and phase balance of the quadrature signals. Different quadrature splitters can be used either RF and/or LO path for quadrature mixing. The two commonly-used quadrature mixers termed single quadrature down-converters use either quadrature input signals or quadrature LO inputs. To avoid signal losses, the later is more popular. Active quadrature generators increase the power consumption, add noise to the system and some of them are not suitable to use on the RF signal path (18). A RLC phase shifter circuit can be used to realize the RF quadrature generator (19). The single-stage RLC circuit can generate accurate quadrature signals without higher power consumption but noise figure degrades due to resistive loss. Quadrature hybrids can generate accurate quadrature signals with zero power consumption and lower loss. Quadrature hybrids for microwave and mm-wave integrated circuit applications are typically designed using different types of quarter wavelength transmission lines such as microstrips, striplines, and waveguides. A major drawback of a transmission line structure, however, is that it consumes a relatively large chip area for frequencies less than about 20GHz. For operation at a single frequency, area savings are realized by approximating transmission line behavior using a symmetrical lumped element π- or T-section (20). Because the lumped-element representation is accurate at only a single frequency, lumped-element hybrids are necessarily narrow-band networks. When designed on chip, however, they are susceptable to the performance degradations associated with process, voltage, and temperature variations. This is a very serious problem in view of the narrow-band nature of the response. Moreover, the performance of lumped-element couplers degrades significantly due to the losses associated with on-chip passives. Branch-line couplers are readily designed in lumped-element form (21). A major drawback of the branch-line coupler is its inherent narrow-band response due to the quarter-wavelength characteristic of each of its the branches. Consequently, variations in passive component values affect its performance dramatically. Bandwidth can be extented by inductive coupling via transformers. A Lange hybrid provides a larger bandwidth than its branch-line counterpart by exploiting both electrical and magnetic coupling between the in-phase and quadrature paths. Lumped-element versions of Lange and branch-line couplers are shown in Fig. 8 wherein the normalized element values are readily calculated using simple design equations (21, 22). Superior bandwidth charasteristic of transformer coupler lumped element hyrid is demonstrated in Fig. 9 and Fig. 8 Lumped-element couplers with normalized element values: (a)inductively-coupled (Lange), and (b) capacitively coupled (branch-line). Fig. 9 Calculated responses of ideal lumped-element capacitively- and inductively-coupled hybrids: Phase shifts between quadrature outputs (left) and corresponding path losses (right) (23). Bandwidth of the coupler can be extended further by cascading coupler stages. It is common practice to cascade identical lumped-element couplers to increase operational bandwidth (24). Because on-chip cascades give more signal loss, less isolation and more chip area, two sections is the practical maximum to maintain acceptable performance. A cascade of two different couplers was introduced in (25) and offers a major advantage. When implemented with low-q on-chip passives, there is cancellation of the positive phase errors of the capacitively coupled branch-line coupler and negative phase errors of the inductively coupled Lange coupler (). Thus, accurate quadrature outputs are generated that are robust when implemented with low-q on-chip passives in CMOS. The measured phase difference deviates from 90 by less than 0.86 (0.7 ) over a 400MHz (220MHz) bandwidth at 5.4GHz (25). A transformer with four-fold symmetrical windings (22) is chosen for the Lange coupler design because of the symmetry between its primary and secondary windings (Fig.12). Although the coupling coefficient of this design is lower than that of a nested spiral transformer, symmetry is of paramount importance in achieving quadrature accuracy.

5 Fig.10 Smulated responses of ideal lumped-element branch-line and Lange couplers: (a) Path losses; (b) return losses and phase shifts between quadrature outputs. Fig.11 Simulated phase responses for different couplers with finite inductor/transformer Q values: (a) Ideal, (b) branch-line, and (c) Lange couplers. Fig.12 Transformer chip micrograph. In summary, transformer-coupled hybrids provide image-rejection over a large bandwidth with zero power consumption and low loss. When realized in cascade with a capacitively-coupled hybrid they can improve on performance limitations imposed by on-chip passives with finite Q values. 4. High-value Miniature Inductors Section 3 discussed the use of inductors in bandwidth extension schemes at the cost of some pulse response fidelity. The quality factor requirements imposed on these inductors are often not stringent. This allows for freedom to make the structure considerably smaller and opens the doors for multi layered miniature inductor structures, which consume minimal on-chip area in return for big inductance values. Wideband LNAs in WCDMA receivers and high speed CML style blocks in wireline transceiver applications are examples of circuits that can benefit from these inductor structures. Multi-metal-layered inductor structures utilize the mutual inductance between vertically aligned metal layers separated by small oxide thicknesses to generate high inductance value. While the mutual inductance contributions scale up the inductance potentially by a square of the number of metal layers used, a reduction in on-chip area used could mean lower substrate parasitics and higher self-resonant frequencies compared to single layered structures giving similar inductance values. The first attempts at building multi-layered structures followed the Wind-in-Wind out scheme shown in Fig. 13(a). The main drawback with this scheme was a large metal-metal layer capacitance, which killed the quality factors and the resonant frequency parameters of the inductors. More recently (26) reported the Wind-Down-Wind-Up scheme shown in Fig. 13(b) where the winding scheme goes down first before spreading out horizontally and coming back up. For a given inductance value structures built following the two mentioned schemes occupy the same chip-area. However, a careful examination of the voltage profiles along the windings suggests that winding down first, rather than winding out, results in a smaller voltage difference between the same points on vertically aligned spirals on different metal layers. This manifests as a lower metal-metal capacitance that leads to higher Q and f SR values. These two schemes still suffer being asymmetric. A fully symmetric multi-layered inductor is shown in Fig. 13(c). The scheme of windings in this structure is actually a combination of the wind-in wind-out and the wind-down wind-up structures; that is, the spirals wind in and down alternately after every half turn. This style of winding has been applied previously to planar monolithic transformer structures for coupling the primary and secondary coils [2]. Its relationship to the wind-down wind-up scheme allows for good Q and f SR values, and its inherent geometric symmetry allows for an easy location of the common mode bias point in differential circuits. This structure avoids the need to have two separate inductor structures in a differential circuit and saves chip area. The location of the two ports on the same side of the spiral can also be an advantage in circuit layout. (a) (b) Fig. 13 (a) Wind-in-wind-out (b) Wind-down-wind-up and (c) A fully symmetric scheme 5. Transformer Modeling When simulating with transformers in the time (c)

6 domain, it is necessary to have a wideband compact model of the transformer, due to the lack of extrapolation in most transient simulators. The model must accurately represent the transformer for a wide frequency range and accommodate for things such as a center-tap, so that the transformer model can be used to provide bias and for use as a BALUN (27). In order to satisfy the above requirements, a double-π model is most appropriate, as an increase in the number of sections will approximate the distributed nature of the transformer, while providing access to a common mode point which can act as a center-tap. Further enhancements to the structure allow the bandwidth of the model to be extended to the first self-resonance of the transformer. Notably, a resistance ladder is added to model skin and proximity effects, and a coupled inductance in series with a resistance can be added in order to model effects of bulk eddy currents (28, 29). The proposed model is shown in Fig. 14. To extract the model, Grover calculations are made to estimate the winding and mutual inductances, while calculations for parasitics associated with the substrate are made according to (30). Next, the ladder structure is implemented and a fitting factor is used to scale the inductance and resistance in the ladder empirically. Depending on the accuracy necessary, elements can be added to and deleted from the ladder as needed. Finally, a large inductor is added in series with the substrate resistance and a mutual inductance is added to couple the transformer windings to this bulk inductance. The coupling factor is determined empirically to obtain a best fit for the model. In order to simplify calculations, an assumption of symmetry is made, but is not necessary. A comparison between a 2:1 transformer electromagnetic simulation and its equivalent compact model is shown in Fig. 15. Fig. 14 Transformer wideband compact model Fig. 15 Comparison of EM Simulation with compact model 6. Summary References 1. J. C. Rudell et al., Proc. Int. Symp. Low-Power Electronics and Design, 149 (1998). 2. J. J. Zhou, D. J. Allstot, IEEE J. Solid-State Circuits 33, 2020 (Dec. 1998). 3. K. Mayaram, D. O. Pederson, IEEE J. Solid-State Circuits 22, 1155 (Dec. 1987). 4. K. Kwok, H. C. Luong, IEEE J. Solid-State Circuits 40, 652 (Mar. 2005). 5. J. R. Long, M. A. Copeland, IEEE J. Solid-State Circuits 30, 1438 (Dec. 1995). 6. J. R. Long, M. Maliepaard, Proc. CICC, pp. 665 (May 1999). 7. X. Li, S. Shekhar, D. J. Allstot, IEEE J. Solid-State Circuits 40, 2609 (Dec. 2005). 8. J. Kulyk, J. Haslett, IEEE J. Solid-State Circuits 41, 362 (Feb. 1996). 9. T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits (Cambridge University Press, New York, 2004), pp. 10. D. L. Kaczman, IEEE J. Solid-State Circuits 41, 1122 (May 2006). 11. E. Frlan, S. Meszaros, M. Cuhaci, J. Wight, Proc. IEEE MTT-S, 661 (June 1989). 12. A. Zolfaghari, A. Chan, B. Razavi, IEEE J. Solid-State Circuits 36, 620 (Apr. 2001). 13. J. R. Long, IEEE J. Solid-State Circuits 35, 1368

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