Quad, 1 A, 5.5 V, Synchronous Step-Down Regulators with One RF LDO Regulator ADP5138

Transcription

1 Quad, A, 5.5 V, Synchronous Step-Down Regulators with One RF LDO Regulator ADP58 FEAURES PVINx voltage range: V to 5.5 V Continuous output current Channel to Channel (buck): A Channel 5 (LDO): 50 ma. MHz fixed PWM switching frequency Synchronization input function Buck regulators run at 90 out of phase Individual precision enable input Power-on reset output Integrated compensation Soft start and power-up sequencing reduce inrush current Active output discharge switch function Stable with low ESR output ceramic capacitors OVLO, UVM, and UVLO SD protection Qualified for automotive applications APPLICAIONS Automotive Industrial and instrumentation DC to dc point of load applications V IN = 5V ± 0% YPICAL APPLICAION CIRCUI C IN C IN C IN C IN C IN5 C AVIN AVIN ADP58 EN PVIN EN PVIN EN PVIN EN PVIN EN5 PVIN5 SYNC SW FB PGND SW FB PGND SW FB PGND SW FB PGND VOU5 FB5 GND POR V OU R OP5 R POR R OP R BO L R OP R BO5 L L R BO L POR V OU =.V V OU =.0V V OU =.5V V OU =.5V V OU5 =.8V C OU5 C OU C OU C OU C OU Figure. GENERAL DESCRIPION he ADP58 integrates four high performance synchronous step-down regulators and one low noise radio frequency (RF) low dropout (LDO) regulator. he device runs from PVINx input voltages of V to 5.5 V. he output voltage of each channel is factory set or can be programmed down to 0.8 V with a resistor. Each step-down regulator can provide up to A of continuous output current and the LDO can provide 50 ma of output current. he ADP58 runs at the fixed PWM switching frequency,. MHz, or can be synchronized to the external clock from.8 MHz to.5 MHz, which is outside the amplitude modulation (AM) band. he four buck regulators run at 90 out of phase to reduce the input ripple current and the input capacitor size, thereby helping to lower system electromagnetic interference (EMI). he ADP58 integrates internal compensation to simplify the design. he internal soft start circuitry and power-up sequencing help reduce the input inrush current. he ADP58 monitors the input voltage and provides input overvoltage lockout (OVLO), undervoltage monitor (UVM), and undervoltage lockout (UVLO) features. It also monitors the undervoltage and overvoltage of the outputs. he power-on reset (POR) signal is asserted when the input or output voltage fault occurs. Additional protection includes overcurrent protection (OCP) and thermal shutdown (SD). he ADP58 operates over the 0 C to +5 C operating temperature range (junction), and is available in a 8-lead LFCSP package. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. rademarks and registered trademarks are the property of their respective owners. One echnology Way, P.O. Box 906, Norwood, MA , U.S.A. el: Analog Devices, Inc. All rights reserved. echnical Support

2 ADP58 ABLE OF CONENS Features... Applications... ypical Application Circuit... General Description... able of Contents... Revision History... Functional Block Diagram... Specifications... Buck Regulator Specifications... 5 LDO Regulator Specifications... 6 Absolute Maximum Ratings... 7 hermal Resistance... 7 ESD Caution... 7 Pin Configuration and Function Descriptions... 8 ypical Performance Characteristics... 0 heory of Operation... 7 Control Scheme... 7 Precision Enable and Shutdown... 7 Oscillator and Phase Shift... 7 Synchronization... 7 Data Sheet Input Overvoltage Lockout (OVLO)... 7 Input Undervoltage Monitor (UVM)... 7 Input Undervoltage Lockout (UVLO)... 7 Output Voltage Power-Good... 7 Power-On Reset (POR)... 8 Soft Start and Power-Up Sequence... 8 Current-Limit and Short-Circuit Protection... 8 Active Output Discharge... 9 hermal Shutdown... 9 Applications Information... 0 Input Capacitor Selection... 0 Output Voltage Setting... 0 Inductor Selection... 0 Output Capacitor Selection... 0 Application Circuit... Factory-Programmable Options... Outline Dimensions... Ordering Guide... Automotive Products... REVISION HISORY 8/08 Rev. 0 to Rev. A Change to Figure... 5/08 Revision 0: Initial Version Rev. A Page of

3 ADP58 FUNCIONAL BLOCK DIAGRAM SLOPE RAMP CHANNEL : BUCK REGULAOR A CS HIGH-SIDE CURREN SENSE I LIM OCP PVIN PVIN SOF SAR VREF EA CMP DRIVER FB EN DIVIDER.V 0% V REF 95% V REF EN_BUF EN_DELAY SD PGOOD UVLO OVLO CLK CONROL LOGIC AND MOSFE DRIVER WIH ANICROSS PROECION PVIN DRIVER LOW-SIDE CURREN SENSE SW PGND FB EN CHANNEL : BUCK REGULAOR PVIN SW PGND FB EN CHANNEL : BUCK REGULAOR PVIN SW PGND FB EN CHANNEL : BUCK REGULAOR PVIN SW PGND PVIN5 EN5.V EN5_BUF EN_DELAY UVLO OVLO SD CHANNEL 5: LDO LDO CONROL EA5 V REF 0% V REF DIVIDER VOU5 FB5 PGOOD5 95% V REF AVIN EN_BUF EN_BUF EN_BUF EN_BUF EN5_BUF.8V.V EN_SYS UVLO UVM COMMON BLOCK VIN_OK CLK SLOPE RAMP CLK SLOPE RAMP CLK SLOPE RAMP CLK SLOPE RAMP OSC SYNC EN_BUF 5.8V OVLO HERMAL SD PGOOD SD POR DELAY IME AND CONROL LOGIC POR GND EN_BUF EN_BUF PGOOD PGOOD VOU_OK EN_BUF EN5_BUF PGOOD PGOOD5 ADP Figure. Rev. A Page of

4 ADP58 Data Sheet SPECIFICAIONS VAVIN = VPVIN = VPVIN = VPVIN = VPVIN = VPVIN5 = 5.0 V, J = 0 C to +5 C for minimum and maximum specifications, and A = 5 C for typical specifications, unless otherwise noted. VOUx is the output voltage on Channel x, where x is to 5. able. Parameter Symbol est Conditions/Comments Min yp Max Unit POWER INPU PVINx Voltage Range VPVINx PVIN, PVIN, PVIN, and PVIN pins 5.5 V PVIN5 pin V AVIN Voltage Range VAVIN AVIN pin 5.5 V Quiescent Current IQ No switching ma Shutdown Current ISHDN VEN = VEN = VEN = VEN = VEN5 = GND µa Input UVLO hreshold AVIN UVLO Rising.9 V AVIN UVLO Falling.7.8 V Input Undervoltage Monitor hreshold AVIN UVM Falling V AVIN UVM Hysteresis mv Input OVLO hreshold AVIN OVLO Rising V AVIN OVLO Hysteresis mv ENABLE ENx pins Rising hreshold..8 V Falling hreshold.0. V Pull-Down Resistance MΩ POWER-ON RESE (POR) POR pin Output Undervoltage hreshold Rising hreshold Percentage of normal VOUx % Falling hreshold Percentage of normal VOUx % Output Overvoltage hreshold Rising hreshold Percentage of normal VOUx 08 0 % Falling hreshold Percentage of normal VOUx % Deglitch ime POR Rising tpor_delay_r ms POR Falling tpor_delay_f 0 µs POR Leakage Current POR voltage (VPOR) = 5 V 0.05 µa POR Output Low Voltage POR current (IPOR) = ma 8 00 mv POR Effective hreshold Voltage on AVIN VAVIN_POR IPOR = ma, VPOR 0. V.6 V SAR-UP SEQUENCE DELAY IME tss_d Delay time during startup µs HERMAL SHUDOWN hreshold 50 C Hysteresis 5 C Guaranteed by design, but not production tested. Rev. A Page of

5 ADP58 BUCK REGULAOR SPECIFICAIONS VAVIN = VPVIN = VPVIN = VPVIN = VPVIN = 5.0 V, J = 0 C to +5 C for minimum and maximum specifications, and A = 5 C for typical specifications, unless otherwise noted. able. Parameter Symbol est Conditions/Comments Min yp Max Unit FEEDBACK FB to FB Regulation Voltage VFB to VFB Adjustable version V Fixed Output Accuracy VOU to VOU + % OUPU CHARACERISICS Pulse-width modulation (PWM) mode Load Regulation VOU/ IOU Output current (IOU) from 0 A to A, VAVIN = VPVINx = 5 V 0. %/A Line Regulation VOU/ VPVIN VAVIN = VPVINx = V to 5.5 V, IOU = A 0. %/V SWICH NODE High-Side On Resistance RDSON_H VAVIN = VPVINx = 5 V, ISWx = 0.5 A 0 00 mω Low-Side On Resistance RDSON_L VAVIN = VPVINx = 5 V, ISWx = 0.5 A 0 00 mω SWx Leakage Current ISW_LK VAVIN = VPVINx = 5 V, SWx = GND or SWx = VPVINx 0. µa CURREN LIMI High-Side Peak Current Limit A Low-Side Sink Current Limit A PWM SWICHING FREQUENCY fsw.. MHz PHASE SHIF Phase shift between channels 90 Degrees SYNC SYNC pin Synchronization Range.8.5 MHz SYNC Minimum On ime 00 ns SYNC Minimum Off ime 00 ns SYNC Input Voltage High. V Low 0. V OUPU DISCHARGE RESISANCE RDISCHARGE to 6 00 Ω RDISCHARGE SOF SAR IME tss to tss µs VOU to VOU are the output voltages on Channel to Channel. Bench characterization result. Pin to pin measurement. Rev. A Page 5 of

6 ADP58 Data Sheet LDO REGULAOR SPECIFICAIONS VAVIN = 5.0 V, VPVIN5 = (output voltage of Channel 5 (VOU5) V) or V (whichever is greater), input capacitance of Channel 5 (CIN5) = output capacitance of Channel 5 (COU5) = μf, J = 0 C to +5 C for minimum and maximum specifications, and A = 5 C for typical specifications, unless otherwise noted. able. Parameter Symbol est Conditions/Comments Min yp Max Unit CURREN Operating Quiescent Current IQ_LDO5 IOU5 = 0 µa, VOU5 =.8 V µa IOU5 = 00 ma, VOU5 =.8 V 6 00 µa Output Current IOU5 VPVIN5 V 50 ma.7 V VPVIN5 < V 00 ma Current Limit VOU5 drops 5% from nominal voltage ma FEEDBACK FB5 Regulation Voltage VFB5 Adjustable version V Fixed Output Voltage Accuracy VOU5 IOU5 = 0 ma, J = 5 C + % ma < IOU5 < 50 ma + % REGULAION Load Regulation IOU5 from ma to 50 ma %/ma Line Regulation IOU5 = 0 ma %/V DROPOU VOLAGE VDROPOU5 VOU5 =. V, IOU5 = 50 ma 7 mv VOU5 =.8 V, IOU5 = 00 ma mv OUPU DISCHARGE RESISANCE RDISCHARGE5 8 0 Ω SOF SAR IME tss5 VOU5 =.8 V, IOU5 = 50 ma µs OUPU NOISE OUNOISE5 0 Hz to 00 khz, VPVIN5 = 5 V, VOU5 =.8 V, IOU5 = 0 µv rms 50 ma, adjustable output option POWER SUPPLY REJECION RAIO PSRRLDO5 khz, VPVIN5 = 5 V, VOU5 =.8 V, IOU5 = 50 ma, adjustable output option 55 db Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. Bench characterization result. Rev. A Page 6 of

7 ABSOLUE MAXIMUM RAINGS able. Parameter PVIN, PVIN, PVIN, PVIN, PVIN5, AVIN, VOU5 SW, SW, SW, SW FB, FB, FB, FB, FB5, EN, EN, EN, EN, EN5, POR, SYNC PGND, PGND, PGND, PGND to GND Operating emperature Range (Junction) Storage emperature Range Soldering Conditions Electrostatic Discharge (ESD) Human Body Model Charged Device Model Rating 0. V to +6 V 0. V to +6 V 0. V to +6 V 0. V to +0. V 0 C to +5 C 65 C to +50 C JEDEC J-SD V 500 V Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. his is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ADP58 HERMAL RESISANCE hermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. able 5. hermal Resistance Package ype θja θjc Unit CP C/W θja is measured using natural convection on a JEDEC -layer board with the exposed pad soldered to the PCB and with thermal vias. ESD CAUION Rev. A Page 7 of

8 ADP58 Data Sheet PIN CONFIGURAION AND FUNCION DESCRIPIONS PVIN SW PGND PGND SW 5 PVIN 6 FB 7 PVIN 0 SW 9 PGND 8 PGND 7 SW 6 PVIN 5 FB FB 7 EN 6 AVIN 5 SYNC GND EN FB ADP58 OP VIEW (Not to Scale) EN POR PVIN5 FB5 VOU5 EN5 EN NOES. EXPOSED PAD. SOLDER HE EXPOSED PAD O AN EXERNAL GROUND PLANE. Figure. Pin Configuration able 6. Pin Function Descriptions Pin No. Mnemonic Description PVIN Power Input for Channel. Connect PVIN to the input power source, and connect a bypass capacitor between this pin and PGND. SW Switch Node for Channel. PGND Power Ground for Channel. PGND Power Ground for Channel. 5 SW Switch Node for Channel. 6 PVIN Power Input for Channel. Connect PVIN to the input power source, and connect a bypass capacitor between this pin and PGND. 7 FB Feedback Voltage Sense Input for Channel. Connect this pin to a resistor divider from VOU for the adjustable version. For the fixed output version, connect this pin to VOU directly. 8 EN Precision Enable Pin for Channel. Use an external resistor divider to set the turn-on threshold. o enable Channel automatically, connect the EN pin to PVIN. 9 POR Power-On Reset Output (Open Drain). 0 PVIN5 Power Input for Channel 5. Connect PVIN5 to the input power source, and connect a bypass capacitor between this pin and ground. FB5 Feedback Voltage Sense Input for Channel 5. Connect this pin to a resistor divider from VOU5 for the adjustable version. For the fixed output version, connect this pin to VOU5 directly. VOU5 Output of Channel 5. Connect a bypass capacitor between this pin and ground. EN5 Precision Enable Pin for Channel 5. Use an external resistor divider to set the turn-on threshold. o enable Channel 5 automatically, connect the EN5 pin to PVIN5. EN Precision Enable Pin for Channel. Use an external resistor divider to set the turn-on threshold. o enable Channel automatically, connect the EN pin to PVIN. 5 FB Feedback Voltage Sense Input for Channel. Connect this pin to a resistor divider from VOU for the adjustable version. For the fixed output version, connect this pin to VOU directly. 6 PVIN Power Input for Channel. Connect PVIN to the input power source, and connect a bypass capacitor between this pin and PGND. 7 SW Switch Node for Channel. 8 PGND Power Ground for Channel. 9 PGND Power Ground for Channel. 0 SW Switch Node for Channel. PVIN Power Input for Channel. Connect PVIN to the input power source, and connect a bypass capacitor between this pin and PGND. FB Feedback Voltage Sense Input for Channel. Connect this pin to a resistor divider from VOU for the adjustable version. For the fixed output version, connect this pin to VOU directly. EN Precision Enable Pin for Channel. Use an external resistor divider to set the turn-on threshold. o enable Channel automatically, connect the EN pin to PVIN. Rev. A Page 8 of

9 ADP58 Pin No. Mnemonic Description GND Analog Ground. Connect this pin to the ground plane. 5 SYNC Synchronization Input. Connect this pin to an external clock between.8 MHz and.5 MHz to synchronize the switching frequency to the external clock. If synchronization function is not used, connect this pin to GND. 6 AVIN Bias Voltage Input Pin. Connect AVIN to PVINx, and connect a bypass capacitor between AVIN and GND. 7 EN Precision Enable Pin for Channel. Use an external resistor divider to set the turn-on threshold. o enable Channel automatically, connect the EN pin to PVIN. 8 FB Feedback Voltage Sense Input for Channel. Connect this pin to a resistor divider from VOU for the adjustable version. For the fixed output version, connect this pin to VOU directly. EP Exposed Pad. Solder the exposed pad to an external ground plane. Rev. A Page 9 of

10 ADP58 Data Sheet YPICAL PERFORMANCE CHARACERISICS A = 5 C, VAVIN = VPVIN = VPVIN = VPVIN = VPVIN = VPVIN5 = 5.0 V, fsw =. MHz, unless otherwise noted. VOUx is the output voltage on a single channel. EFFICIENCY (%) V OU =.V V OU =.0V V OU =.5V V OU =.5V QUIESCEN CURREN (ma) V PVINx = V V PVINx = 5V V PVINx = 5.5V OUPU CURREN (A) Figure. Efficiency vs. Output Current at VPVINx = 5 V, fsw =. MHz Figure 7. Quiescent Current vs. emperature SHUDOWN CURREN (na) V PVINx = V V PVINx = 5V V PVINx = 5.5V AVIN UVLO HRESHOLD (V) RISING FALLING Figure 5. Shutdown Current vs. emperature Figure 8. AVIN UVLO hreshold vs. emperature RISING FALLING RISING FALLING AVIN UVM HRESHOLD (V).8..0 AVIN OVLO HRESHOLD (V) Figure 6. AVIN UVM hreshold vs. emperature Figure 9. AVIN OVLO hreshold vs. emperature Rev. A Page 0 of

11 ADP ENABLE HRESHOLD (V) EN RISING EN RISING EN RISING EN RISING EN5 RISING EN FALLING EN FALLING EN FALLING EN FALLING EN5 FALLING POR RISING DEGLICH IME (ms) Figure 0. Enable hreshold vs. emperature Figure. POR Rising Deglitch ime vs. emperature OUPU OVERVOLAGE RISING HRESHOLD (%) CH: FIXED.V CH: FIXED.0V 09. CH: FIXED.5V CH: FIXED.5V CH5: FIXED.8V Figure. Output Overvoltage Rising hreshold vs. emperature OUPU UNDERVOLAGE FALLING HRESHOLD (%) CH: FIXED.V 9.6 CH: FIXED.0V CH: FIXED.5V CH: FIXED.5V CH5: FIXED.8V Figure. Output Undervoltage Falling hreshold vs. emperature FEEDBACK VOLAGE OF BUCK REGULAORS (mv) FB 797 FB FB FB Figure. Feedback Voltage of Buck Regulators vs. emperature FEEDBACK VOLAGE OF LDO (mv) FB Figure 5. Feedback Voltage of LDO vs. emperature Rev. A Page of

12 ADP58 Data Sheet.. CHANNEL FIXED OUPU VOLAGE (V) V OU =.V SWICHING FREQUENCY (MHz) Figure 6. Channel Fixed Output Voltage vs. emperature Figure 9. Switching Frequency vs. emperature.0.90 CHANNEL, CHANNEL, AND CHANNEL FIXED OUPU VOLAGE (V) V OU =.0V V OU =.5V V OU =.5V CHANNEL 5 FIXED OUPU VOLAGE (V) V OU5 =.8V Figure 7. Channel, Channel, and Channel Fixed Output Voltage vs. emperature Figure 0. Channel 5 Fixed Output Voltage vs. emperature HIGH-SIDE MOSFE ON RESISOR (mω) CH 0 CH CH CH Figure 8. High-Side Metal-Oxide Semiconductor Field Effect ransistor (MOSFE) On Resistor vs. emperature LOW-SIDE MOSFE ON RESISOR (mω) CH 00 CH CH CH Figure. Low-Side MOSFE On Resistor vs. emperature Rev. A Page of

13 ADP58 BUCK REGULAORS SOF SAR IME (µs) CH CH CH CH LDO SOF SAR IME (µs) CH Figure. Buck Regulators Soft Start ime vs. emperature Figure 5. LDO Soft Start ime vs. emperature CURREN-LIMI HRESHOLD OF BUCK REGULAORS (A) CH CH CH CH CURREN LIMI OF LDO (ma) Figure. Current-Limit hreshold of Buck Regulators vs. emperature Figure 6. Current Limit of LDO vs. emperature LDO OUPU NOISE DENSIY (µv/ Hz) LDO PSRR (db) I OU5 = 50mA I OU5 = 0mA k 0k 00k M 0M FREQUENCY (Hz) Figure. LDO Output Noise Density vs. Frequency at VPVIN5 = 5 V, IOU5 = 50 ma, VOU5 =.8 V, Adjustable Output Option k 0k 00k M 0M FREQUENCY (Hz) Figure 7. LDO PSRR vs. Frequency at VPVIN5 = 5 V, VOU5 =.8 V, Adjustable Output Option Rev. A Page of

14 ADP58 Data Sheet 0 SW LDO OUPU NOISE RMS VALUE (µv) SW SW SW k 0k 00k M FREQUENCY (Hz) Figure 8. LDO Output Noise RMS Value vs. Frequency at VPVIN5 = 5 V, IOU5 = 50 ma, VOU5 =.8 V, Adjustable Output Option CH 5.00V CH 5.00V CH 5.00V 00ns CH.80V CH 5.00V 50.60% Figure. Phase Shift ENx V OU V OU V OU V OU V OU5 V OU POR CH 5.00V B W CH.00V B W.00ms CH.70V CH 500mV B W CH.00V B W 0.00% Figure 9. Startup with Full Load (ENx, VOU, VOU, and VOU) CH 5.00V B W CH.00V B W.00ms CH.70V CH.00V B W CH.00V B W 87.0% Figure. Startup with Full Load (VOU, VOU, VOU5, and POR) ENx V OU V OU V OU V OU V OU V OU5 POR CH 5.00V B W CH.00V B W CH.00V B W.00ms CH.70V CH.00V B W 0.00% CH 5.00V B W CH.00V B W CH.00V B W.00ms CH.70V CH.00V B W 0.00% Figure 0. Shutdown at No Load (ENx, VOU, VOU, and VOU) Figure. Shutdown at No Load (VOU, VOU, VOU5, and POR) Rev. A Page of

15 ADP58 V OU I L V OU5 (AC) SW I OU5 CH.00V B W CH.00V CH.00A Ω B W 00ns 9.60% CH.7V Figure. Overcurrent Protection (IL is Channel Inductor Current) CH 0.0mV B W CH 00mA Ω B W 00µs CH 60.0mA 0.00% Figure 7. Load ransient Response of Channel 5 (.8 V), 0 A to 0. A V OU (AC) V OU (AC) I OU I OU CH 50.0mV B W CH 500mA Ω B W 00µs CH 650mA 0.0% Figure 5. Load ransient Response of Channel (. V), 0. A to 0.9 A CH 50.0mV B W CH 500mA Ω B W 00µs 0.00% CH 60mA Figure 8. Load ransient Response of Channel (.0 V), 0. A to 0.9 A V OU (AC) V OU (AC) I OU I OU CH 50.0mV B W CH 500mA Ω B W 00µs CH 60mA 0.00% Figure 6. Load ransient Response of Channel (.5 V), 0. A to 0.9 A CH 50.0mV B W CH 500mA Ω B W 00µs 0.00% CH 60mA Figure 9. Load ransient Response of Channel (.5 V), 0. A to 0.9 A Rev. A Page 5 of

16 ADP58 Data Sheet PVIN PVIN V OU (AC) V OU (AC) CH 0.0mV CH.00V B W BW.00ms CH 5.0V 0.00% Figure 0. Line ransient Response of Channel (. V), PVIN from.5 V to 5.5 V, A Load Current CH 0.0mV CH.00V B W BW.00ms CH 5.0V 0.00% Figure. Line ransient Response of Channel (.0 V), PVIN from.5 V to 5.5 V, A Load Current PVIN PVIN V OU (AC) V OU (AC) CH 0.0mV CH.00V B W BW.00ms CH 5.0V 0.00% Figure. Line ransient Response of Channel (.5 V), PVIN from.5 V to 5.5 V, A Load Current CH 0.0mV CH.00V B W BW.00ms CH 5.V 0.00% Figure. Line ransient Response of Channel (.5 V), PVIN from.5 V to 5.5 V, A Load Current PVIN5 V OU5 (AC) CH 0.0mV CH.00V B W BW.00ms CH 5.0V 0.00% Figure. Line ransient Response of Channel 5 (.8 V), PVIN5 from.5 V to 5.5 V, 50 ma Load Current Rev. A Page 6 of

17 HEORY OF OPERAION he ADP58 is a power management IC that integrates four buck regulators and one low noise LDO in a 8-lead LFCSP package. he device can operate with a PVINx input voltage from V to 5.5 V and can regulate the output voltage down to 0.8 V or set by factory. It provides input UVLO, OVLO, and UVM features. he ADP58 also monitors the output voltage and provides the POR output. CONROL SCHEME he ADP58 uses a fixed frequency, peak current mode, PWM control architecture. At the start of each oscillator cycle, the high-side field effect transistor (FE) turns on, placing a positive voltage across the inductor. he inductor current increases until the current sense signal crosses the peak inductor current threshold that turns off the high-side FE and turns on the low-side FE, which, in turn, places a negative voltage across the inductor, causing the inductor current to reduce. he low-side FE stays on for the remainder of the cycle. PRECISION ENABLE AND SHUDOWN he ADP58 has five independent enable pins (ENx) for each channel. he ENx pins are precision analog inputs that enable the regulator when the voltage on ENx exceeds. V (typical). When the ENx voltage falls below. V (typical), the regulator turns off. An internal pull-down resistor ( MΩ) prevents the regulator from being accidentally enabled if ENx is left floating. o force the ADP58 to automatically start when the input power is applied, connect ENx to PVINx. OSCILLAOR AND PHASE SHIF he buck regulators in the ADP58 run at a. MHz fixed switching frequency. For Channel to Channel, the phase shift with respect to Channel is set to 90, which reduces the input ripple current and the input capacitance, thereby helping to lower system EMI. SW SW SW SW Figure 5. Even Phase Shift Between Channel and Channel SYNCHRONIZAION ADP58 o synchronize the ADP58, connect an external clock to the SYNC pin. he external clock frequency can be in the.8 MHz to.5 MHz range. During synchronization, Channel runs in phase with the external clock. If the synchronization function is not used, connect the SYNC pin to ground. INPU OVERVOLAGE LOCKOU (OVLO) he ADP58 integrates an input overvoltage lockout circuit on the input supply. When the input voltage, VAVIN, exceeds 5.8 V (typical), an OVLO event is detected, all the regulators are turned off, and the POR is pulled down to ground. When the input voltage falls back to 5.7 V (typical) or less, the OVLO releases and a soft start reinitializes. INPU UNDERVOLAGE MONIOR (UVM) he ADP58 integrates an input undervoltage monitoring circuit on the input supply. When the input voltage, VAVIN, drops below. V (typical), the POR pin pulls down to ground while the device still works until the input voltage drops down to the input voltage UVLO threshold. When the input voltage exceeds.8 V (typical), the POR pin pulls high after a POR rising delay time, tpor_delay_r, if all other conditions are met. INPU UNDERVOLAGE LOCKOU (UVLO) he ADP58 integrates an input undervoltage lockout circuit on the input supply. When the input voltage, VAVIN, drops below.8 V (typical), an input UVLO event is detected, all the regulators turn off, and the POR pin pulls down to ground. When the input voltage recovers from the UVLO event and the input voltage exceeds.9 V (typical), a soft start reinitializes. OUPU VOLAGE POWER-GOOD Each of the five regulators integrates an output voltage powergood monitoring circuit. When the output voltage drops below the undervoltage falling threshold (9% of the nominal output voltage), an output undervoltage event is detected, and the power-good signal becomes low. When the output voltage rises above the undervoltage rising threshold (95% of the nominal output voltage), the power-good signal becomes high. When the output voltage exceeds the overvoltage rising threshold (0% of the nominal output voltage), an output overvoltage event is detected. During the output overvoltage, the corresponding regulator stops switching, and the powergood signal becomes low. When the output voltage drops below the overvoltage falling threshold (08% of the nominal output voltage), the corresponding regulator recovers to normal operation, and the power-good signal becomes high. Rev. A Page 7 of

18 ADP58 POWER-ON RESE (POR) he ADP58 integrates the POR circuit to monitor the input voltage and output voltage of the regulators. he POR pin is an active high, open-drain output that requires a resistor to pull the pin up to a voltage. he ENx pin voltage determines which output voltage is monitored in the POR circuit. When the ENx pin voltage exceeds. V (typical), the POR circuit monitors the corresponding output voltage. When the ENx pin voltage is lower than. V (typical), the POR circuit does not monitor the corresponding output voltage. he POR pin does not pull high until all of the following conditions are met followed by a 5.7 ms (typical) delay: he input voltage is greater than the undervoltage lockout threshold and undervoltage monitor threshold. he input voltage is less than the input overvoltage threshold. No thermal shutdown. All the power-good signals are high for these monitored output voltages. he POR pin is pulled down when any of these conditions are not met with a 0 µs deglitch time. If all the channels are disabled, the POR pin pulls down to ground. he POR output is fully controlled when the voltage on AVIN is higher than VAVIN_POR. SOF SAR AND POWER-UP SEQUENCE he ADP58 has integrated soft start circuitry for each channel to limit the output voltage rising time and to reduce the inrush current during startup. he soft start time is fixed at 500 µs (typical) for the buck regulators and 570 µs (typical) for the LDO regulator. When the ADP58 exits the input UVLO, input OVLO, or thermal shutdown event, there is a fixed delay time on each enable signal. his delay time prevents all the regulators from powering up at the same time and reduces the input inrush current. able 7 shows the delay time for each channel. able 7. Enable Delay ime for Each Channel Channel Delay ime Channel 5 µs Channel tss_d Channel tss_d Channel tss_d Channel 5 tss_d Figure 6 shows the power-up sequence when the ENx pins are pulled up at the same time. Channel powers up first, followed by Channel, Channel, Channel, and Channel 5. Figure 7 shows the power-up sequence when the channels are enabled at different times. V PVINx, V AVIN ENx V OU V OU V OU V OU V OU5 POR t SS t SS t SS t SS t SS_D t SS_D t SS_D t SS_D Data Sheet Figure 6. Power-Up Sequence with All Channels Enabled at Same ime V PVINx, V AVIN EN, EN EN, EN, EN5 V OU V OU V OU V OU V OU5 POR t SS t SSt SS5 t SS_D t SS_D t POR_DELAY_R 95% Figure 7. Power-Up Sequence with Channels Enabled at Different imes CURREN-LIMI AND SHOR-CIRCUI PROECION he ADP58 integrates a cycle by cycle, peak current-limit protection circuit to prevent current runaway for each buck regulator. he high-side FE peak current is limited to.6 A (typical). When the peak inductor current reaches the currentlimit threshold, the high-side FE turns off, the low-side FE turns on, and the output reference voltage decreases. he low-side FE in the buck regulator can also sink current from the load. If the low-side sink current limit is exceeded, both the low-side and high-side FEs are turned off until the next cycle starts. t SS5 95% t SS t POR_DELAY_R t POR_DELAY_R 95% t SS_D t SS t SS_D Rev. A Page 8 of

19 he LDO is designed to current limit when the output load reaches the current-limit threshold. When the output load exceeds the current-limit threshold, the output voltage is reduced to maintain a constant current limit. ACIVE OUPU DISCHARGE Each of the five regulators in the ADP58 integrates a discharge switch from the switching node to ground. his switch is turned on when its associated ENx pin is low, which helps to discharge the output capacitor quickly. he typical value of the discharge ADP58 switch is 6 Ω for the buck regulators and 8 Ω for the LDO regulator. HERMAL SHUDOWN In the event that the ADP58 junction temperature exceeds 50 C, the thermal shutdown circuit turns off the device. A 5 C hysteresis is included so that the ADP58 does not recover from thermal shutdown until the on-chip temperature drops below 5 C. Upon recovery, a soft start and the power-up sequence are initiated prior to normal operation. Rev. A Page 9 of

20 ADP58 Data Sheet APPLICAIONS INFORMAION INPU CAPACIOR SELECION he input capacitor reduces the input voltage ripple caused by the switch current on PVINx. Place the input capacitor as close as possible to the PVINx pin. A ceramic capacitor in the 0 μf to 7 μf range is recommended. he loop composed of the input capacitor, the high-side MOSFE, and the low-side MOSFE must be kept as small as possible. he voltage rating of the input capacitor must be greater than the maximum input voltage. Ensure that the rms current rating of the input capacitor is larger than the value calculated from the following equation: I CIN _ RMS = I OU D ( D) where: IOU is the output current. D is the duty cycle (D = VOU/VIN). OUPU VOLAGE SEING he output voltage (VOU) of the ADP58 can be factory set or programmed by an external resistor divider. If the output voltage is factory set, connect the FBx pin to the output voltage directly. If the output voltage is programmable, use the following equation to set the output voltage: R = + OP VOU 0.8 R BO where: ROP is the top resistor of the resistor divider. RBO is the bottom resistor of the resistor divider. able 8. Resistor Divider Values for Various Output Voltages VOU (V) ROP ± % (kω) RBO ± % (kω) INDUCOR SELECION he inductor value is determined by the operating frequency, input voltage, output voltage, and inductor ripple current. Using a small inductor value leads to a faster transient response but degrades efficiency due to a larger inductor ripple current. Using a large inductor value leads to a smaller ripple current and better efficiency but results in a slower transient response. As a guideline, an inductor with its value in the range from 0.68 µh to. µh is recommended for the best balance between transient and efficiency performance. he inductor ripple current, ΔIL, is typically set to one-third of the maximum load current. Rev. A Page 0 of Use the following equation to calculate the inductor value: ( VIN VOU ) D L = I f L SW where: VIN is the input voltage. VOU is the output voltage. D is the duty cycle (D = VOU/VIN). ΔIL is the inductor current ripple. fsw is the switching frequency. Use the following equation to calculate the peak inductor current: I L I PEAK = IOU + he saturation current of the inductor must be larger than the peak inductor current. For ferrite core inductors with a quick saturation characteristic, the saturation current rating of the inductor must be higher than the current-limit threshold of the switch to prevent the inductor from reaching saturation. Use the following equation to calculate the rms current of the inductor: I L IRMS = IOU + Shielded ferrite core materials are recommended for low core loss and low EMI. OUPU CAPACIOR SELECION he output capacitor selection affects both the output voltage ripple and the loop dynamics of the regulator. he ADP58 operates with small ceramic capacitors that have low equivalent series resistance (ESR) and low equivalent series inductance (ESL) and can, therefore, easily meet the output voltage ripple specifications. When the regulator operates in continuous conduction mode, the overall output voltage ripple is the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by the charging and discharging of the output capacitor. V RIPPLE = IL + ESR C 8 f OU SW COU where: ΔVRIPPLE is the output voltage ripple. COU is the output capacitance. Capacitors with lower ESR are preferable to guarantee low output voltage ripple, as shown in the following equation: VRIPPLE ESRC OU I L Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over temperature and applied voltage. X5R or X7R dielectrics are recommended for best performance due to the low ESR and small temperature coefficients.

21 ADP58 APPLICAION CIRCUI ADP58 V OU V IN = 5V ± 0% C AVIN µf/6v C IN 0µF/6.V AVIN EN PVIN POR SW FB PGND R POR 00kΩ L µh POR V OU =.V C OU 0µF/6.V C IN 0µF/6.V EN PVIN SW FB PGND L µh R OP.6kΩ R BO 6.9kΩ V OU =.0V C OU 0µF/6.V C IN 0µF/6.V EN PVIN SW FB PGND L µh R OP 5.6kΩ R BO 9.5kΩ V OU =.5V C OU 0µF/6.V C IN 0µF/6.V EN PVIN SW FB PGND L µh V OU =.5V C OU 0µF/6.V C IN5 µf/6v EN5 PVIN5 SYNC VOU5 FB5 GND R OP5 8.7kΩ R BO5 5kΩ V OU5 =.8V C OU5 µf/6v Figure 8. Application Circuit Rev. A Page of

22 ADP58 FACORY-PROGRAMMABLE OPIONS he output of each buck regulator and the LDO can be preset to one of the options listed in able 9. here are 5 fixed options and one adjustable option. o order a device with options other Data Sheet than the default options listed in the Ordering Guide, contact a local Analog Devices, Inc., sales or distribution representative. able 9. Output Voltage Fuse-Selectable rim Options Parameter Output Voltage rim Options (V) Buck Regulator Adjustable, 0.9, 0.95,.0,.05,.,.5,.,.5,.5,.5,.8,.5,.65,.0,. Buck Regulator Adjustable, 0.9, 0.95,.0,.05,.,.5,.,.5,.5,.5,.8,.5,.65,.0,. Buck Regulator Adjustable, 0.9, 0.95,.0,.05,.,.5,.,.5,.5,.5,.8,.5,.65,.0,. Buck Regulator Adjustable, 0.9, 0.95,.0,.05,.,.5,.,.5,.5,.5,.8,.5,.65,.0,. LDO Adjustable,.0,.05,.,.5,.,.5,.,.5,.8,.5,.65,.8,.85,.0,. Rev. A Page of

23 ADP58 OULINE DIMENSIONS PIN INDICAOR.0.00 SQ BSC EXPOSED PAD 8 DEAIL A (JEDEC 95) PIN INDICAOR AR EA OPIONS (SEE DEAIL A) SQ ORDERING GUIDE,, Model Figure 9. 8-Lead Lead Frame Chip Scale Package [LFCSP] mm mm Body and 0.75 mm Package Height (CP-8-5) Dimensions shown in millimeters Output Voltage (V) Buck Buck Buck Buck LDO emperature Range Package Description Package Option ADP58WACPZ--R7. ADJ ADJ.5 ADJ 0 C to +5 C 8-Lead LFCSP CP-8-5 ADP58ACPZ--R7 ADJ ADJ ADJ ADJ ADJ 0 C to +5 C 8-Lead LFCSP CP-8-5 ADP58W--EVALZ. ADJ ADJ.5 ADJ Evaluation Board Z = RoHS Compliant Part. W = Qualified for Automotive Applications. o order a device with options other than the two default options listed in the ordering guide, contact a local Analog Devices sales or distribution representative. ADJ means adjustable. PKG SEAING PLANE OP VIEW SIDE VIEW MAX 0.0 NOM COPLANARIY REF 8 BOOM VIEW COMPLIAN OJEDEC SANDARDS MO-0-WGGE. 0.0 MIN FOR PROPER CONNECION OF HE EXPOSED PAD, REFER O HE PIN CONFIGURAION AND FUNCION DESCRIPIONS SECION OF HIS DAA SHEE B AUOMOIVE PRODUCS he ADP58W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for this model. 08 Analog Devices, Inc. All rights reserved. rademarks and registered trademarks are the property of their respective owners. D /8(A) Rev. A Page of