3 MHz, 600 ma, Low Quiescent Current Buck with 300 ma LDO Regulator ADP2140

Transcription

1 Data Sheet MHz, 6 ma, Low Quiescent Current Buck with ma LDO Regulator ADP4 FEAURES Input voltage range:. V to 5.5 V LDO input (VIN).65 V to 5.5 V Buck output voltage range:. V to. V LDO output voltage range:.8 V to. V Buck output current: 6 ma LDO output current: ma LDO quiescent current: μa with zero load Buck quiescent current: μa in PSM mode Low shutdown current: <. μa Low LDO dropout ma load High LDO PSRR 65 khz at VOU =. V 55 khz at VOU =. V Low noise LDO: 4 μv rms at VOU =. V Initial accuracy: ±% Current-limit and thermal overload protection Power-good indicator Optional enable sequencing -lead.75 mm mm mm LFCSP package APPLICAIONS Mobile phones Personal media players Digital camera and audio devices Portable and battery-powered equipment GENERAL DESCRIPION he ADP4 includes a high efficiency, low quiescent 6 ma stepdown dc-to-dc converter and a ma LDO packaged in a small -lead mm mm LFCSP. he total solution requires only four tiny external components. he buck regulator uses a proprietary high speed current-mode, constant frequency, pulse-width modulation (PWM) control scheme for excellent stability and transient response. o ensure the longest battery life in portable applications, the ADP4 has a power saving variable frequency mode to reduce switching frequency under light loads. he LDO is a low quiescent current, low dropout linear regulator designed to operate in a split supply mode with VIN as low as.65 V. he low input voltage minimum allows the LDO to be powered from the output of the buck regulator increasing efficiency and reducing power dissipation. he ADP4 runs from input voltages of. V to 5.5 V allowing single Li+/Li polymer PG EN EN PG EN EN V IN =.6V C IN µf kω YPICAL APPLICAION CIRCUIS V OU =.8V 6 C OU + µf V IN =.V C IN µf kω ADP4 VIN PGND PG SW EN AGND EN FB VOU VIN Figure. ADP4 with LDO Connected to VIN V OU =.V 6 C OU + µf ADP4 VIN PGND PG SW EN AGND EN FB VOU VIN µh V OU =.V + C OU µf µh V OU =.8V + C OU µf Figure. ADP4 with LDO Connected to Buck Output cell, multiple alkaline/nimh cell, PCMCIA, and other standard power sources. ADP4 includes a power-good pin, soft start, and internal compensation. Numerous power sequencing options are userselectable through two enable inputs. In autosequencing mode, the highest voltage output enables on the rising edge of EN. During logic controlled shutdown, the input disconnects from the output and draws less than na from the input source. Other key features include: undervoltage lockout to prevent deep battery discharge, soft start to prevent input current overshoot at startup, and both short-circuit protection and thermal overload protection circuits to prevent damage in adverse conditions. When the ADP4 is used with two 6 capacitors, one 4 capacitor, one 4 resistor, and one 85 chip inductor, the total solution size is approximately 9 mm resulting in the smallest footprint solution to meet a variety of portable applications Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. rademarks and registered trademarks are the property of their respective owners. One echnology Way, P.O. Box 96, Norwood, MA 6-96, U.S.A. el: Analog Devices, Inc. All rights reserved. echnical Support

2 ADP4 ABLE OF CONENS Features... Applications... General Description... ypical Application Circuits... Revision History... Specifications... Recommended Specifications: Capacitors and Inductor... 4 Absolute Maximum Ratings... 5 hermal Data... 5 hermal Resistance... 5 ESD Caution... 5 Pin Configuration and Function Descriptions... 6 ypical Performance Characteristics... 7 Buck Output... 7 LDO Output... 4 heory of Operation... 9 Buck Section... 9 Control Scheme... 9 PWM Operation... 9 PSM Operation... 9 Pulse Skipping hreshold... 9 Selected Features... Data Sheet Short-Circuit Protection... Undervoltage Lockout... hermal Protection... Soft Start... Current Limit... Power-Good Pin... LDO Section... Applications Information... Power Sequencing... Power-Good Function... 4 External Component Selection... 4 Selecting the Inductor... 4 Output Capacitor... 4 Input Capacitor... 4 Efficiency... 5 Recommended Buck External Components... 5 LDO Capacitor Selection... 6 LDO as a Postregulator to Reduce Buck Output Noise... 6 hermal Considerations... 8 PCB Layout Considerations... 9 Outline Dimensions... Ordering Guide... REVISION HISORY 9/ Rev. to Rev. A Updated Outline Dimensions... Changes to Ordering Guide... 6/ Revision : Initial Version Rev. A Page of

3 Data Sheet ADP4 SPECIFICAIONS V IN =.6 V, V IN = V OU +. V or.65 V, whichever is greater; 5 V EN = EN = V IN ; I OU = ma, I OU = ma, C IN = μf, C OU = µf, C OU = µf, L OU = μh; J = 4 C to +5 C for minimum/maximum specifications, and A = 5 C for typical specifications, unless otherwise noted. able. Parameter Symbol est Conditions/Comments Min yp Max Unit BUCK SECION Input Voltage Range V IN. 5.5 V Buck Output Accuracy V OU I OU = ma % V IN =. V or (V OU +.5 V) to 5.5 V, I OU = ma to 6 ma % ransient Load Regulation V R-LOAD V OU =.8 V Load = 5 ma to 5 ma, rise/fall time = ns 75 mv Load = ma to 6 ma, rise/fall time = ns 75 mv ransient Line Regulation V R-LINE Line transient = 4 V to 5 V, 4 μs rise time V OU =. V 4 mv V OU =.8 V 5 mv V OU =. V 5 mv PWM o PSM hreshold V IN =. V or (V OU +.5 V) to 5.5 V ma Output Current I OU 6 ma Current Limit I LIM V IN =. V or (V OU +.5 V) to 5.5 V ma Switch On Resistance PFE R PFE V IN =. V to 5.5 V 5 mω NFE R NFE V IN =. V to 5.5 V 5 mω Switch Leakage Current I LEAK-SW EN = GND, VIN = 5.5 V, and SW = V μa Quiescent Current I Q No load, device not switching μa Minimum On ime ON-IME MIN 7 ns Oscillator Frequency FREQ MHz Frequency Foldback hreshold V FOLD Output voltage where f SW 5% of nominal frequency 5 % Start-Up ime t SAR-UP V OU =.8 V, 6 ma load 7 µs Soft Start ime SS IME V OU =.8 V, 6 ma load 5 μs LDO SECION Input Voltage Range V IN V LDO Output Accuracy V OU I OU = ma, J = 5 C + % ma < I OU < ma, V IN = (V OU +. V) to 5.5 V, J % = 5 C ma < I OU < ma, V IN = (V OU +. V) to 5.5 V + % Line Regulation V OU / V IN V IN = (V OU +. V) to 5.5 V, I OU = ma %/V Load Regulation V OU / I OU I OU = ma to ma..5 %/ma Dropout Voltage 4 V DROPOU I OU = ma, V OU =.8 V 4 7 mv I OU = ma, V OU =.8 V mv Ground Current I AGND No load, buck disabled 5 μa I OU = ma 65 9 μa I OU = ma 5 μa Power Supply Rejection Ratio PSRR V IN = V OU + V, V IN = 5 V, I OU = ma PSRR on V IN khz, V OU =. V,.8 V,. V 65 db khz, V OU =. V 5 db khz, V OU =.8 V 54 db khz, V OU =. V 55 db Rev. A Page of

4 ADP4 Data Sheet Parameter Symbol est Conditions/Comments Min yp Max Unit Output Noise OU NOISE V IN = V IN = 5 V, I OU = ma Hz to khz, V OU =.8 V 9 µv rms Hz to khz, V OU =. V 4 µv rms Hz to khz, V OU =.8 V 5 µv rms Hz to khz, V OU =.5 V 66 µv rms Hz to khz, V OU =. V 88 µv rms Current Limit I LIM J = 5 C ma Input Leakage Current I LEAK-LDO EN = GND, V IN = 5.5 V and V OU = V μa Start-Up ime t SAR-UP V OU =. V, ma load 7 µs Soft Start ime SS IME V OU =. V, ma load μs ADDIIONAL FUNCIONS Undervoltage Lockout UVLO Input Voltage Rising UVLO RISE.. V Input Voltage Falling UVLO FALL.5.6 V EN Input EN, EN Input Logic High V IH. V V IN 5.5 V. V EN, EN Input Logic Low V IL. V V IN 5.5 V.7 V EN, EN Input Leakage I EN-LKG EN, EN = V IN or GND.5 µa EN, EN = V IN or GND µa Shutdown Current I SHU V IN = 5.5 V, EN, EN = GND, J = 4 C to +85 C.. μa hermal Shutdown hreshold S SD J rising 5 C Hysteresis S SD-HYS C Power Good Rising hreshold PG RISE 9 %V OU Falling hreshold PG FALL 86 %V OU Power-Good Hysteresis PG HYS 6 %V OU Output Low V OL I SINK = 4 ma. V Leakage Current I OH Power-good pin pull-up voltage = 5.5 V μa Buck to LDO Delay t DELAY PWM mode only 5 ms Power-Good Delay t RESE PWM mode only 5 ms Start-up time is defined as the time between the rising edge of ENx to V OUx being at % of the V OUx nominal value. Soft start time is defined as the time between V OUx being at % to V OUx being at 9% of the V OUx nominal value. Based on an endpoint calculation using ma and ma loads. 4 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. his applies only for output voltages above. V. RECOMMENDED SPECIFICAIONS: CAPACIORS AND INDUCOR able. Parameter Symbol est Conditions/Comments Min yp Max Unit MINIMUM INPU AND OUPU CAPACIANCE A = 4 C to +5 C Buck C MIN 7.5 µf LDO C MIN.7. µf CAPACIOR ESR A = 4 C to +5 C Ω Buck R ESR.. Ω LDO R ESR. Ω MINIMUM INDUCOR IND MIN.7 μh he minimum input and output capacitance should be greater than.7 μf over the full range of operating conditions. he full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R- and X5R-type capacitors are recommended, Y5V and Z5U capacitors are not recommended for use with any LDO. Rev. A Page 4 of

5 Data Sheet ABSOLUE MAXIMUM RAINGS able. Parameter VIN, VIN to PGND, AGND VOU to PGND, AGND SW to PGND, AGND FB to PGND, AGND PG to PGND, AGND EN, EN to PGND, AGND Storage emperature Range Operating Ambient emperature Range Operating Junction emperature Range Soldering Conditions Rating. V to +6.5 V. V to V IN. V to V IN. V to +6.5 V. V to +6.5 V. V to +6.5 V 65 C to +5 C 4 C to +85 C 4 C to +5 C JEDEC J-SD- Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. his is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. HERMAL DAA Absolute maximum ratings apply individually only, not in combination. he ADP4 can be damaged when the junction temperature limits are exceeded. Monitoring ambient temperature does not guarantee that J is within the specified temperature limits. In applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may need to be derated. In applications with moderate power dissipation and low printed circuit board (PCB) thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. he junction temperature ( J ) of the device is dependent on the ambient temperature ( A ), the power dissipation of the device (P D ), and the junction-to-ambient thermal resistance of the package (θ JA ). Maximum junction temperature ( J ) is calculated from the ambient temperature ( A ) and power dissipation (P D ) using the formula J = A + (P D θ JA ) ADP4 Junction-to-ambient thermal resistance (θ JA ) of the package is based on modeling and calculation using a 4-layer board. he junction-to-ambient thermal resistance is highly dependent on the application and board layout. In applications where high maximum power dissipation exists, close attention to thermal board design is required. he value of θ JA may vary, depending on PCB material, layout, and environmental conditions. he specified values of θ JA are based on a 4-layer, 4 in. in. circuit board. Refer to JESD 5-7 for detailed information on the board construction. For more information, see AN-77 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP). Ψ JB is the junction-to-board thermal characterization parameter with units of C/W. Ψ JB of the package is based on modeling and calculation using a 4-layer board. he JESD5-, Guidelines for Reporting and Using Package hermal Information, states that thermal characterization parameters are not the same as thermal resistances. Ψ JB measures the component power flowing through multiple thermal paths rather than a single path, as in thermal resistance, θ JB. herefore, Ψ JB thermal paths include convection from the top of the package as well as radiation from the package, factors that make Ψ JB more useful in real-world applications. Maximum junction temperature ( J ) is calculated from the board temperature ( B ) and power dissipation (P D ) using the formula J = B + (P D Ψ JB ) Refer to JESD5-8 and JESD5- for more detailed information about Ψ JB. HERMAL RESISANCE θ JA and Ψ JB are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. able 4. hermal Resistance Package ype θ JA Ψ JB Unit -Lead mm mm LFCSP C/W ESD CAUION Rev. A Page 5 of

6 ADP4 Data Sheet PIN CONFIGURAION AND FUNCION DESCRIPIONS PGND SW AGND FB VIN ADP4 9 OP VIEW 8 (Not to Scale) VIN PG EN EN VOU NOES. HE EXPOSED PAD ON HE BOOM OF HE LFCSP PACKAGE ENHANCES HERMAL PERFORMANCE AND IS ELECRICALLY CONNECED O GROUND INSIDE HE PACKAGE. I IS RECOMMENDED HA HE EXPOSED PAD BE CONNECED O HE GROUND PLANE ON HE CIRCUI BOARD. Figure. Pin Configuration 79- able 5. Pin Function Descriptions Pin Mnemonic Description PGND Power Ground. SW Connection from Power MOSFEs to Inductor. AGND Analog Ground. 4 FB Feedback from Buck Output. 5 VIN LDO Input Voltage. 6 VOU LDO Output Voltage. 7 EN Logic to Enable LDO or No Connect for Autosequencing. 8 EN Logic to Enable Buck or Initiate Sequencing. his is a dual function pin and the state of EN determines which function is operational. 9 PG Power Good. Open-drain output. PG is held low until both output voltages (which includes the external inductor and capacitor sensed by the FB pin) rise above 9% of nominal value. PG is held high until both outputs fall below 85% of nominal value. VIN Analog Power Input. EP Exposed Pad. he exposed pad on the bottom of the LFCSP package enhances thermal performance and is electrically connected to ground inside the package. It is recommended that the exposed pad be connected to the ground plane on the circuit board. Rev. A Page 6 of

7 Data Sheet ADP4 YPICAL PERFORMANCE CHARACERISICS BUCK OUPU V IN = 4 V, V OU =.8 V, I OU = ma, C IN = C OU = µf, A = 5 C, unless otherwise noted..8 QUIESCEN CURREN (µa) C 5 5 C +5 C +85 C +5 C INPU VOLAGE (V) Figure 4. Quiescent Supply Current vs. Input Voltage, Different emperatures 79-4 OUPU VOLAGE (V) LOAD CURREN = ma LOAD CURREN = ma LOAD CURREN = 5mA LOAD CURREN = ma LOAD CURREN = ma LOAD CURREN = 6mA JUNCION EMPERAURE ( C) Figure 7. Output Voltage vs. emperature, V IN =. V, Different Loads 79-7 FREQUENCY (MHz) C.6 4 C 5 C +85 C.5 +5 C INPU VOLAGE (V) Figure 5. Switching Frequency vs. Input Voltage, Different emperatures 79-5 CURREN LIMI (ma) JUNCION EMPERAURE ( C).V.V 4.V 5.V 5.5V Figure 8. Current Limit vs. emperature, Different Input Voltages 79-8 FREQUENCY (MHz) EMPERAURE ( C) 5.5V 4.6V.V.V Figure 6. Switching Frequency vs. emperature, Different Input Voltages 79-6 CURREN (ma) C 5 C +5 C +85 C +5 C INPU VOLAGE (V) Figure 9. PSM to PWM Mode ransition vs. Input Voltage, Different emperatures 79-9 Rev. A Page 7 of

8 ADP4 Data Sheet V IN = 4 V, V OU =.8 V, I OU = ma, C IN = C OU = µf, A = 5 C, unless otherwise noted..8.5 OUPU VOLAGE (V) LOAD CURREN = ma LOAD CURREN = ma LOAD CURREN = 5mA.77 LOAD CURREN = ma LOAD CURREN = ma LOAD CURREN = 6mA INPU VOLAGE (V) Figure. Line Regulation, V OU =.8 V, Different Loads 79- OUPU VOLAGE (V) LOAD CURREN (ma) Figure. Load Regulation, V OU =. V 79- OUPU VOLAGE (V) LOAD CURREN (ma) Figure. Load Regulation, V OU =.8 V, V IN =. V 79- EFFICIENCY (%) V.V 4.V 5.V 5.5V LOAD CURREN (ma) Figure 4. Efficiency vs. Load Current, V OU =.8 V, Different Input Voltages 79-4 OUPU VOLAGE (V) LOAD CURREN (ma) Figure. Load Regulation, V OU =. V, V IN =. V 79- EFFICIENCY (%) C 5 C +5 C +85 C +5 C LOAD CURREN (ma) Figure 5. Efficiency vs. Load Current, V OU =.8 V, Different emperatures 79-5 Rev. A Page 8 of

9 Data Sheet ADP4 V IN = 4 V, V OU =.8 V, I OU = ma, C IN = C OU = µf, A = 5 C, unless otherwise noted. EFFICIENCY (%) V.V 4.V 5.V 5.5V LOAD CURREN (ma) Figure 6. Efficiency vs. Load Current, V OU =. V, Different Input Voltages 79-6 EFFICIENCY (%) C 5 C +5 C +85 C +5 C LOAD CURREN (ma) Figure 9. Efficiency vs. Load Current, V OU =. V, Different emperatures 79-9 EFFICIENCY (%) C 5 C +5 C +85 C +5 C LOAD CURREN (ma) Figure 7. Efficiency vs. Load Current, V OU =. V, Different emperatures 79-7 EFFICIENCY (%) V 5.V 5.5V LOAD CURREN (ma) Figure. Efficiency vs. Load Current, V OU =. V, Different Input Voltages 79-8 INPU VOLAGE INPU VOLAGE OUPU VOLAGE OUPU VOLAGE SWICH NODE SWICH NODE CH.V CH 5.mV M.µs A CH 4.68V CH 5.V.6% Figure 8. Line ransient, V OU =.8 V, Power Save Mode, 5 ma, V IN = 4 V to 5 V, 4 μs Rise ime 79- CH.V CH.mV M.µs A CH 4.68V CH 5.V.6% Figure. Line ransient, V OU =.8 V, PWM Mode, 6 ma, V IN = 4 V to 5 V, 4 μs Rise ime 79- Rev. A Page 9 of

10 ADP4 Data Sheet V IN = 4 V, V OU =.8 V, I OU = ma, C IN = C OU = µf, A = 5 C, unless otherwise noted. INPU VOLAGE INPU VOLAGE OUPU VOLAGE OUPU VOLAGE SWICH NODE SWICH NODE CH.V CH 5.mV M.µs A CH 4.68V CH 5.V.6% Figure. Line ransient, V OU =. V, PSM Mode, 5 ma, V IN = 4 V to 5 V, 4 μs Rise ime 79- CH.V CH.mV M.µs A CH 4.68V CH 5.V.6% Figure 5. Line ransient, V OU =. V, PWM Mode, 6 ma, V IN = 4 V to 5 V, 4 μs Rise ime 79-5 INPU VOLAGE SWICH NODE LOAD CURREN OUPU VOLAGE SWICH NODE OUPU VOLAGE CH.V CH.mV M.µs A CH 4.V CH 5.V.8% Figure. Line ransient, V OU =. V, PWM Mode, 6 ma, V IN = 4 V to 5 V, 4 μs Rise ime 79- CH ma CH 5.mV M.µs A CH 88mA CH 5.V.4% Figure 6. Load ransient, V OU =.8 V, ma to 6 ma, Load Current Rise ime = ns 79-6 INPU VOLAGE SWICH NODE OUPU VOLAGE LOAD OUPU SWICH NODE OUPU VOLAGE CH.V CH 5.mV M.µs A CH 4.68V CH 5.V.6% Figure 4. Line ransient, V OU =. V, PSM Mode, 5 ma, V IN = 4 V to 5 V, 4 μs Rise ime 79-4 CH ma CH 5.mV M.µs A CH 6mA CH 5.V.4% Figure 7. Load ransient, V OU =.8 V, 5 ma to 5 ma, Load Current Rise ime = ns 79-7 Rev. A Page of

11 Data Sheet ADP4 V IN = 4 V, V OU =.8 V, I OU = ma, C IN = C OU = µf, A = 5 C, unless otherwise noted. SWICH NODE SWICH NODE LOAD CURREN LOAD CURREN OUPU VOLAGE OUPU VOLAGE CH 5.mA CH 5.mV M.µs A CH 5.mA CH 5.V.4% Figure 8. Load ransient, V OU =.8 V, ma to ma, Load Current Rise ime = ns 79-8 CH 5.mA CH.mV M.µs A CH 5.mA CH 5.V.4% Figure. Load ransient, V OU =. V, ma to ma, Load Current Rise ime = ns 79- SWICH NODE SWICH NODE LOAD CURREN LOAD CURREN OUPU VOLAGE OUPU VOLAGE CH ma CH.mV M.µs A CH 9mA CH 5.V.4% Figure 9. Load ransient, V OU =. V, ma to 6 ma, Load Current Rise ime = ns 79-9 CH.mA CH 5.mV M.µs A CH 76mA CH 5.V.4% Figure. Load ransient, V OU =. V, ma to 6 ma, Load Current Rise ime = ns 79- SWICH NODE SWICH NODE LOAD CURREN LOAD CURREN OUPU VOLAGE OUPU VOLAGE CH ma CH.mV M.µs A CH 8.mA CH 5.V.4% Figure. Load ransient, V OU =. V, 5 ma to 5 ma, Load Current Rise ime = ns 79- CH.mA CH 5.mV M.µs A CH 54mA CH 5.V.4% Figure. Load ransient, V OU =. V, 5 ma to 5 ma, Load Current Rise ime = ns 79- Rev. A Page of

12 ADP4 Data Sheet V IN = 4 V, V OU =.8 V, I OU = ma, C IN = C OU = µf, A = 5 C, unless otherwise noted. SWICH NODE SWICH NODE LOAD CURREN INDUCOR CURREN OUPU VOLAGE OUPU VOLAGE ENABLE CH 5.mA CH 5.mV M.µs A CH 48.mA CH 5.V.4% Figure 4. Load ransient, V OU =. V, ma to ma, Load Current Rise ime = ns CH 5mA CH.V CH 5.V CH4 5.V M4.µs A CH4.7V.4% Figure 7. Startup, V OU =. V, ma 79-7 SWICH NODE SWICH NODE INDUCOR CURREN INDUCOR CURREN OUPU VOLAGE OUPU VOLAGE ENABLE ENABLE 4 CH 5mA CH.V CH 5.V CH4 5.V Mµs A CH4.7V.4% Figure 5. Startup, V OU =.8 V, ma CH 5mA CH.V CH 5.V CH4 5.V M4.µs A CH4.7V.4% Figure 8. Startup, V OU =. V, 6 ma 79- SWICH NODE SWICH NODE INDUCOR CURREN INDUCOR CURREN OUPU VOLAGE OUPU VOLAGE ENABLE 4 CH 5mA CH.V CH 5.V CH4 5.V M4.µs A CH4.7V.4% Figure 6. Startup, V OU =.8 V, 6 ma CH ma CH.V CH 5.V CH4 5.V ENABLE Mµs A CH4.V.4% Figure 9. Startup, V OU =. V, ma 79-9 Rev. A Page of

13 Data Sheet ADP4 V IN = 4 V, V OU =.8 V, I OU = ma, C IN = C OU = µf, A = 5 C, unless otherwise noted. SWICH NODE BUCK OUPU LDO OUPU INDUCOR CURREN OUPU VOLAGE PG SIGNAL ENABLE ENABLE 4 CH 5mA CH.V CH 5.V CH4 5.V M4.µs A CH4.V.% Figure 4. Startup, V OU =. V, 6 ma CH.V CH.V CH 5.V CH4 5.V M.ms A CH4.V.% Figure 4. Startup, Autosequence Mode, V OU =.8 V, V OU =. V 79-4 Rev. A Page of

14 ADP4 Data Sheet LDO OUPU V IN = 5 V, V IN =. V, V OU =.8 V, I OU = ma, C IN = C OU = µf, A = 5 C, unless otherwise noted. OUPU VOLAGE (V) LOAD CURREN = ma LOAD CURREN = 5mA LOAD CURREN = ma LOAD CURREN = 5mA LOAD CURREN = ma LOAD CURREN = ma JUNCION EMPERAURE ( C) Figure 4. Output Voltage vs. Junction emperature, Different Loads 79-4 GROUND CURREN (µa) LOAD CURREN = ma LOAD CURREN = 5mA LOAD CURREN = ma LOAD CURREN = 5mA LOAD CURREN = ma LOAD CURREN = ma JUNCION EMPERAURE ( C) Figure 45. Ground Current vs. Junction emperature, Different Loads OUPU VOLAGE (V) GROUND CURREN (µa) LOAD CURREN (ma) Figure 4. Output Voltage vs. Load Current 79-4 LOAD CURREN (ma) Figure 46. Ground Current vs. Load Current OUPU VOLAGE (V) LOAD CURREN = ma.79 LOAD CURREN = 5mA LOAD CURREN = ma.785 LOAD CURREN = 5mA LOAD CURREN = ma LOAD CURREN = ma INPU VOLAGE (V) Figure 44. Output Voltage vs. Input Voltage, Different Loads GROUND CURREN (µa) LOAD CURREN = ma LOAD CURREN = 5mA LOAD CURREN = ma LOAD CURREN = 5mA LOAD CURREN = ma LOAD CURREN = ma INPU VOLAGE (V) Figure 47. Ground Current vs. Input Voltage, Different Loads Rev. A Page 4 of

15 Data Sheet ADP4 V IN = 5 V, V IN =. V, V OU =.8 V, I OU = ma, C IN = C OU = µf, A = 5 C, unless otherwise noted. SHUDOWN CURREN (µa) v.6v.4v.8v 4.6V 5.5V EMPERAURE ( C) Figure 48. Shutdown Current vs. emperature at Various Input Voltages GROUND CURREN (µa) I GND = ma I GND = 5mA I GND = ma I GND = 5mA I GND = ma I GND = ma INPU VOLAGE (V) Figure 5. Ground Current vs. Input Voltage (in Dropout) ma ma ma ma DROPOU VOLAGE (mv) 75 5 PSRR (db) OUPU VOLAGE (V) LOAD CURREN (ma) Figure 49. Dropout Voltage vs. Load Current.6 V DROP = ma.55 V DROP = 5mA V DROP = ma.5 V DROP = 5mA V DROP = ma V DROP = ma INPU VOLAGE (V) Figure 5. Output Voltage vs. Input Voltage (in Dropout) k k k M M FREQUENCY (Hz) Figure 5. Power Supply Rejection Ratio vs. Frequency V OU =. V, V IN = 5 V, V IN =. V PSRR (db) ma ma ma ma ma k k k M M FREQUENCY (Hz) Figure 5. Power Supply Rejection Ratio vs. Frequency V OU =. V, V IN = 5 V, V IN =.7 V Rev. A Page 5 of

16 ADP4 Data Sheet V IN = 5 V, V IN =. V, V OU =.8 V, I OU = ma, C IN = C OU = µf, A = 5 C, unless otherwise noted. ma ma ma ma ma ma ma ma ma PSRR (db) PSRR (db) k k k M M FREQUENCY (Hz) Figure 54. Power Supply Rejection Ratio vs. Frequency, V OU =. V, V IN = 5 V, V IN = 4. V k k k M M FREQUENCY (Hz) Figure 57. Power Supply Rejection Ratio vs. Frequency, V OU =. V, V IN = 5 V, V IN =.8 V ma ma ma ma ma ma ma ma ma PSRR (db) PSRR (db) k k k M M FREQUENCY (Hz) Figure 55. Power Supply Rejection Ratio vs. Frequency, V OU =.8 V, V IN = 5 V, V IN =.8 V k k k M M FREQUENCY (Hz) Figure 58. Power Supply Rejection Ratio vs. Frequency V OU =.8 V, V IN = 5 V, V IN =. V V.8V.5V.V 9 8.V.8V.5V.V 7 (µv/ Hz). NOISE (µv rms) k k k FREQUENCY (Hz) Figure 56. Output Noise Spectrum, V IN = 5 V, Load Current = ma n µ µ µ m m m LOAD CURREN (A) Figure 59. Output Noise vs. Load Current and Output Voltage V IN = 5 V 79-6 Rev. A Page 6 of

17 Data Sheet ADP4 V IN = 5 V, V IN =. V, V OU =.8 V, I OU = ma, C IN = C OU = µf, A = 5 C, unless otherwise noted. LOAD CURREN V IN V OU V OU CH ma CH mv M4.µs A CH 68mA.4% Figure 6. Load ransient Response, V IN = 4 V, V OU =. V, ma to ma, Load Current Rise ime = ns CH.V CH 5.mV M.µs A CH4 mv.% Figure 6. Line ransient Response, V OU =.8 V, Load Current = ma, V IN = 4 V to 5 V, μs Rise ime 79-6 LOAD CURREN V IN V OU V OU CH ma CH mv M4.µs A CH 68mA.4% Figure 6. Load ransient Response, V IN = 4 V, V OU =.8 V, ma to ma, Load Current Rise ime = ns 79-6 CH.V CH 5.mV M.µs A CH4 mv.% Figure 64. Line ransient Response, V OU =. V, Load Current = ma, V IN = 4 V to 5 V, μs Rise ime LOAD CURREN V IN V OU V OU CH ma CH mv M4.µs A CH 68mA.4% Figure 6. Load ransient Response, V IN = 4 V, V OU =. V, ma to ma, Load Current Rise ime = ns 79-6 CH.V CH 5.mV M.µs A CH4 mv.% Figure 65. Line ransient Response, V OU =. V, Load Current = ma, V IN = 4 V to 5 V, μs Rise ime Rev. A Page 7 of

18 ADP4 Data Sheet V IN = 5 V, V IN =. V, V OU =.8 V, I OU = ma, C IN = C OU = µf, A = 5 C, unless otherwise noted. V IN V IN V OU V OU CH.V CH 5.mV M.µs A CH4 mv.% Figure 66. Line ransient Response, V OU =.8 V, Load Current = ma, V IN = 4 V to 5 V, μs Rise ime CH.V CH 5.mV M.µs A CH4 mv.% Figure 68. Line ransient Response, V OU =. V, Load Current = ma, V IN = 4 V to 5 V, μs Rise ime V IN V OU CH.V CH 5.mV M.µs A CH4 mv.% Figure 67. Line ransient Response, V OU =. V, Load Current = ma, V IN = 4 V to 5 V, μs Rise ime Rev. A Page 8 of

19 Data Sheet ADP4 HEORY OF OPERAION SOF SAR UVLO VIN CURREN SENSE AMP FB VIN REFERENCE.5V Gm ERROR AMP MHz OSCILLAOR HERMAL SHUDOWN PWM/ PSM CONROL CURREN LIMI DRIVER AND ANISHOO HROUGH SW BUCK SECION AGND EN EN R R ENABLE/ SEQUENCING he ADP4 contains a step-down dc-to-dc converter that uses a fixed frequency, high speed current-mode architecture. he high MHz switching frequency and tiny -lead, mm mm LFCSP package allow for a small step-down dc-to-dc converter solution. he ADP4 operates with an input voltage from. V to 5.5 V. Output voltage options are. V,. V,. V,.5 V,.8 V,.875 V,.5 V, and. V. CONROL SCHEME he ADP4 operates with a fixed frequency, current-mode PWM control architecture at medium to high loads for high efficiency, but shifts to a variable frequency control scheme at light loads for lower quiescent current. When operating in fixed frequency PWM mode, the duty cycle of the integrated switches adjust to regulate the output voltage, but when operating in power saving mode (PSM) at light loads, the switching frequency adjusts to regulate the output voltage. he ADP4 operates in the PWM mode only when the load current is greater than the pulse skipping threshold current. At load currents below this value, the converter smoothly transitions to the PSM mode of operation. PWM OPERAION In PWM mode, the ADP4 operates at a fixed frequency of MHz set by an internal oscillator. At the start of each oscillator cycle, the P-channel MOSFE switch is turned on, putting a FB POWER GOOD Figure 69. Internal Block Diagram ZERO-CROSS COMPARAOR PGND PG EPAD positive voltage across the inductor. Current in the inductor increases until the current sense signal crosses the peak inductor current level that turns off the P-channel MOSFE switch and turns on the N-channel MOSFE synchronous rectifier. his puts a negative voltage across the inductor, causing the inductor current to decrease. he synchronous rectifier stays on for the remainder of the cycle, unless the inductor current reaches zero, which causes the zero-crossing comparator to turn off the N-channel MOSFE. PSM OPERAION he ADP4 has a smooth transition to the variable frequency PSM mode of operation when the load current decreases below the pulse skipping threshold current, switching only as necessary to maintain the output voltage within regulation. When the output voltage dips below regulation, the ADP4 enters PWM mode for a few oscillator cycles to increase the output voltage back to regulation. During the wait time between bursts, both power switches are off, and the output capacitor supplies the entire load current. Because the output voltage occasionally dips and recovers, the output voltage ripple in this mode is larger than the ripple in the PWM mode of operation. PULSE SKIPPING HRESHOLD he output current at which the ADP4 transitions from variable frequency PSM control to fixed frequency PWM control is called the pulse skipping threshold. he pulse skipping threshold has been optimized for excellent efficiency over all load currents Rev. A Page 9 of

20 ADP4 SELECED FEAURES SHOR-CIRCUI PROECION he ADP4 includes frequency foldback to prevent output current runaway on a hard short. When the voltage at the feedback pin falls below 5% of the nominal output voltage, indicating the possibility of a hard short at the output, the switching frequency is reduced to / of the internal oscillator frequency. he reduction in the switching frequency gives more time for the inductor to discharge, preventing a runaway of output current. UNDERVOLAGE LOCKOU o protect against battery discharge, undervoltage lockout circuitry is integrated on the ADP4. If the input voltage drops below the.5 V UVLO threshold, the ADP4 shuts down and both the power switch and synchronous rectifier turn off. When the voltage rises again above the UVLO threshold, the soft start period initiates and the part is enabled. HERMAL PROECION In the event that the ADP4 junction temperatures rises above 5 C, the thermal shutdown circuit turns off the converter. Extreme junction temperatures can be the result of high current operation, poor circuit board design, and/or high ambient temperature. A C hysteresis is included; thus, when thermal shutdown occurs, the ADP4 does not return to operation until the on-chip temperature drops below C. When emerging from a thermal shutdown, soft start initiates. SOF SAR he ADP4 has an internal soft start function that ramps the output voltage in a controlled manner upon startup, thereby limiting the inrush current. his prevents possible input voltage drops when a battery or a high impedance power source is connected to the input of the converter. CURREN LIMI he ADP4 has protection circuitry to limit the direction and amount of current to ma flowing through the power switch and synchronous rectifier. he positive current limit on the power switch limits the amount of current that can flow from the input to the output, and the negative current limit on the synchronous rectifier prevents the inductor current from reversing direction and flowing out of the load. Data Sheet he ADP4 also provides a negative current limit to prevent an excessive reverse inductor current when the switching section sinks current from the load in forced continuous conduction mode. Under negative current limit conditions, both the highside and low-side switches are disabled. POWER-GOOD PIN he ADP4 has a dedicated pin (PG) to signal the state of the monitored output voltages. he voltage monitor circuit has an active high, open-drain output requiring an external pull-up resistor typically supplied from the I/O supply rail, as shown in. he voltage monitor circuit has a small amount of hysteresis and is deglitched to ensure that noise or external perturbations do not trigger the PG line. LDO SECION he ADP4 low dropout linear regulator uses an advanced proprietary architecture to achieve low quiescent current, and high efficiency regulation. It also provides high power supply rejection ratio (PSRR), low output noise, and excellent line and load transient response with just a small μf ceramic output capacitor. he wide input voltage range of.65 V to 5.5 V allows it to operate from either the input or output of the buck. Supply current in shutdown mode is typically. µa. Internally, the LDO consists of a reference, an error amplifier, a feedback voltage divider, and a pass device. he output current is delivered via the pass device, which is controlled by the error amplifier, forming a negative feedback system ideally driving the feedback voltage to be equal to the reference voltage. If the feedback voltage is lower than the reference voltage, the negative feedback drives more current, increasing the output voltage. If the feedback voltage is higher than the reference voltage, the negative feedback drives less current, decreasing the output voltage. he positive supply for all circuitry, except the pass device, is the VIN pin. he LDO has an internal soft start that limits the output voltage ramp period to approximately µs. he LDO is available in.8 V,. V,. V,. V,. V,.5 V,.5 V,.8 V,. V, and. V output voltage options. Rev. A Page of

21 Data Sheet APPLICAIONS INFORMAION POWER SEQUENCING he ADP4 has a flexible power sequencing system supporting two distinct activation modes: Individual activation control is where EN controls only the buck regulator and EN controls only the LDO. A high level on Pin EN turns on the buck and a high level on Pin EN turns on the LDO. A logic low level turns off the respective regulator. Autosequencing is where the two regulators turn on in a specified order and delay after a low-to-high transition on the EN pin. Select the activation mode (individual or autosequence) by decoding the state of Pin EN. he individual activation mode is selected when the EN pin is driven externally or hardwired to a voltage level (VIN or PGND). he autosequencing mode is selected when the EN pin remains unconnected (floating). o minimize quiescent current consumption, the mode selection executes one time only during the rising edge of VIN. he detection circuit then activates for the time needed to assess the EN state, after which time the circuit is disabled until VIN falls below.5 V. When EN is unconnected, the internal control circuit provides a termination resistance to ground. he kω termination resistance is low enough to guarantee insensitivity to noise and transients. he termination resistor is disabled in the event that the EN pin is driven externally to a logic level high (individual activation mode assumed) to reduce the quiescent current consumption. When the autosequencing mode is selected, the EN pin is used to start the on/off sequence of the regulators. A logic high sequences the regulators on whereas a logic low sequences the regulators off. he regulator activation order is associated with the voltage selected for the buck regulator and the LDO. When the turn on or turn off autosequence starts, the start-up delay between the first and the second regulator is fixed to 5 ms in PWM mode (treg, as shown in Figure 7 and Figure 7). When the application requires activating and deactivating the regulators at the same time, use the individual activation mode, which connects the EN and EN pins together, as shown in Figure 75. ADP4 able 6. Power Sequencing Modes EN EN Description Individual mode: both regulators are off. Individual mode: buck regulator is on. Individual mode: LDO regulator is on. Individual mode: both regulators are on. NC Rising edge Autosequence: Buck regulator turns on, then the LDO regulator turns on. he LDO voltage is less than the buck voltage. NC Rising edge Autosequence: LDO regulator turns on, then the buck regulator turns on. he LDO voltage is greater than the buck voltage. NC Rising edge Autosequence: If the buck voltage is.875 V, then the LDO regulator always turns on first. NC Falling edge Autosequence: he LDO and buck regulators turn off at the same time. NC means not connected. Figure 7 to Figure 75 use the following symbols, as described in able 7. able 7. iming Symbols Symbol Description ypical Value tsar ime needed for the internal circuitry 6 μs to activate the first regulator tss Regulator soft start time μs trese ime delay from power-good 5 ms condition to the release of PG treg Delay time between buck and LDO activation 5 ms V EN V BUCK t SS EN V LDO PG 9% V BUCK t SS 9% V LDO 85% VLDO t RESE Figure 7. Individual Activation Mode IME Rev. A Page of

22 ADP4 Data Sheet V EN = UNCONNECED EN V BUCK 9% V BUCK 85% VBUCK EN EN V BUCK 9% V BUCK V LDO 9% V LDO 85% V LDO V LDO t SAR tss t REG 9% V LDO 85% V LDO PG t RESE 79-7 PG t SS t RESE Figure 7. Autosequencing Mode, Buck First hen LDO IME 79- Figure 74. Individual Activation Mode, One Regulator Only (Buck) Sensed EN V EN EN = UNCONNECED V BUCK V LDO 9% V BUCK 9% V LDO 85% V BUCK 85% V LDO EN V LDO V BUCK t SAR t SS 9% V LDO 9% V BUCK 85% V BUCK PG t RESE Figure 75. Individual Activation Mode, No Activation/Deactivation Delay Between Regulators, EN and EN Pins ied ogether PG t REG t SS t RESE Figure 7. Autosequencing Mode, LDO First hen Buck IME he PG responds to the last activated regulator. As described in the Power Sequencing section, the regulator order in the autosequencing mode is defined by the voltage option combination. herefore, if the sequence is buck first, the LDO and the PG signal are active low for trese after VLDO reaches 9% of the rated output voltage, at which time PG goes high and remains high for as long as VLDO is above 86% of the rated output voltage. When the sequencing is LDO first then buck, VBUCK controls PG. his control scheme also applies when the individual activation mode is selected. As soon as either regulator output voltage drops below 86% of the respective nominal level, the PG pin is forced low. 79- BUCK OUPU LDO OUPU EN CH 5mV CH 5mV M.ms A CH.6V CH.V.% Figure 76. Autosequence Mode urn On Behavior, Buck Voltage =.8 V, LDO Voltage =. V, Buck Load = 5 ma, LDO Load = ma BUCK OUPU 79- EN V BUCK 9% V BUCK 85% VBUCK 95% V BUCK 85% V BUCK EN LDO OUPU 9% V LDO 85% V LDO V LDO EN PG t RESE t RESE Figure 7. Individual Activation Mode, Both Regulators Sensed 79-7 CH 5mV CH 5mV M4.µs A CH.6V CH.V.% Figure 77. Autosequence Mode urn On Behavior, Buck Voltage =.8 V, LDO Voltage =. V, Buck Load = 5 ma, LDO Load = ma Rev. A Page of 79-

23 Data Sheet ADP4 LDO OUPU BUCK OUPU LDO OUPU BUCK OUPU EN EN CH 5mV CH 5mV M4.µs A CH.6V CH.V.% Figure 78. Autosequence Mode urn On Behavior, Buck Voltage =.8 V, LDO Voltage =. V, Buck Load = 5 ma, LDO Load = ma 79- CH 5mV CH.V M4.µs A CH.4V CH.V.% Figure 8. Autosequence Mode urn On Behavior, Buck Voltage =. V, LDO Voltage =. V, Buck Load = 5 ma, LDO Load = ma (Expanded Version of Figure 8) 79-6 BUCK OUPU LDO OUPU LDO OUPU BUCK OUPU EN CH.V CH.V Mms A CH.4V CH.V Figure 79. Autosequence Mode urn On Behavior, Buck Voltage =.8 V, LDO Voltage =. V, Buck Load = ma, LDO Load = ma 79-4 EN CH 5mV CH.V M4.µs A CH.4V CH.V.% Figure 8. Autosequence Mode urn Off Behavior, Buck Voltage =. V, LDO Voltage =. V, Buck Load = 5 ma, LDO Load = ma 79-7 LDO OUPU LDO OUPU BUCK OUPU BUCK OUPU EN EN CH 5mV CH.V M.ms A CH.4V CH.V.% Figure 8. Autosequence Mode urn On Behavior, Buck Voltage =. V, LDO Voltage =. V, Buck Load = 5 ma, LDO Load = ma 79-5 CH 5mV CH.V M.ms A CH.4V CH.V.% Figure 8. Autosequence Mode urn On Behavior, Buck Voltage =. V, LDO Voltage =. V, Buck Load = ma, LDO Load = ma 79-8 Rev. A Page of

24 ADP4 Data Sheet BUCK OUPU LDO OUPU EN CH 5mV CH 5mV M4.µs A CH.6V CH.V.% Figure 84. Individual Activation Mode, EN and EN Pins ied ogether POWER-GOOD FUNCION he ADP4 power-good (PG) pin indicates the state of the monitored output voltages. he PG function is the logical AND of the state of both outputs. he PG function is an active high, open-drain output, requiring an external pull-up resistor typically supplied from the I/O supply rail, as shown in. When the sensed output voltages are below 9% of their nominal value, the PG pin is held low. When the sensed output voltages rise above 9% of the nominal levels, the PG line is pulled high after t RESE. he PG pin remains high as long as the sensed output voltages are above 86% of the nominal output voltage levels. he typical PG delay when the buck is in PWM mode is 5 ms. When the part is in PSM mode, the PG delay is load dependent because the internal clock is disabled to reduce quiescent current during the sleep stage. PG delay varies from hundreds of microseconds at ma, up to seconds at current loads of less than μa. 4 CH.V CH.V CH.V CH4.V EN BUCK LDO PG M.ms A CH.V.% Figure 85. ypical PG iming EXERNAL COMPONEN SELECION he external component selection for the ADP4 application circuit that is shown in able 8, able 9, and Figure 86 is dependent on input voltage, output voltage, and load current requirements. Additionally, trade-offs between performance parameters such as efficiency and transient response can be made by varying the choice of external components SELECING HE INDUCOR he high frequency switching of the ADP4 allows the selection of small chip inductors. he inductor value affects the transition between CFM to PSM, efficiency, output ripple, and current limit values. Use the following equation to calculate the inductor ripple current: Δ I L V = ( VIN V V f L OU IN sw OU ) where: f SW is the switching frequency ( MHz typical). L is the inductor value. he dc resistance (DCR) value of the selected inductor affects efficiency, but a decrease in this value typically means an increase in root mean square (rms) losses in the core and skin. As a minimum requirement, the dc current rating of the inductor should be equal to the maximum load current plus half of the inductor current ripple, as shown by the following equation: ΔI L I PK = ILOAD( MAX) + ( ) OUPU CAPACIOR Output capacitance is required to minimize the voltage overshoot and ripple present on the output. Capacitors with low equivalent series resistance (ESR) values produce the lowest output ripple; therefore, use capacitors such as the X5R dielectric. Do not use the Y5V and Z5U capacitors; they are not suitable for this application because of their large variation in capacitance over temperature and dc bias voltage. Because ESR is important, select the capacitor using the following equation: VRIPPLE ESRCOU ΔI L where: ESR COU is the ESR of the chosen capacitor. V RIPPLE is the peak-to-peak output voltage ripple. Use the following equations to determine the output capacitance: VIN COU (π f ) L V C OU 8 f SW SW ΔI L ΔV OU RIPPLE Increasing the output capacitor has no effect on stability and increasing the output capacitance may further reduce output ripple and enhance load transient response. When choosing this value, it is also important to account for the loss of capacitance due to output voltage dc bias. INPU CAPACIOR Input capacitance is required to reduce input voltage ripple; therefore, place the input capacitor as close as possible to the VINx pins. As with the output capacitor, a low ESR X7R- or X5R-type Rev. A Page 4 of

25 Data Sheet capacitor is recommended to help minimize the input voltage ripple. Use the following equation to determine the minimum input capacitance: I CIN I LOAD( MAX) V OU ( VIN V V EFFICIENCY Efficiency is defined as the ratio of output power to input power. he high efficiency of the ADP4 has two distinct advantages. First, only a small amount of power is lost in the dc-to-dc converter package, which in turn, reduces thermal constraints. In addition, high efficiency delivers the maximum output power for the given input power, thereby extending battery life in portable applications. Power Switch Conduction Losses Power switch dc conduction losses are caused by the flow of output current through the P-channel power switch and the N-channel synchronous rectifier, which have internal resistances (RDS(ON)) associated with them. he amount of power loss can be approximated by P SW V where D V IN OU _ COND )) OU IN ( RDS( ON )_ P D RDS( ON )_ N ( D IOU he internal resistance of the power switches increases with temperature but decreases with higher input voltage. Inductor Losses Inductor conduction losses are caused by the flow of current through the inductor, which has an internal resistance (DCR) associated with it. Larger size inductors have smaller DCR, which can decrease inductor conduction losses. Inductor core losses relate to the magnetic permeability of the core material. Because the ADP4 is a high switching frequency dc-to-dc converter, shielded ferrite core material is recommended for its low core losses and low EMI. o estimate the total amount of power lost in the inductor, use the following equation: PL = DCR IOU + Core Losses ) ADP4 Switching Losses Switching losses are associated with the current drawn by the driver to turn on and turn off the power devices at the switching frequency. Each time a power device gate is turned on and turned off, the driver transfers a charge, ΔQ, from the input supply to the gate, and then from the gate to ground. Estimate switching losses using the following equation: PSW = (CGAE_P + CGAE_N) VIN fsw where: CGAE_P is the gate capacitance of the internal high-side switch. CGAE_N is the gate capacitance of the internal low-side switch. fsw is the switching frequency. ransition Losses ransition losses occur because the P-channel switch cannot turn on or turn off instantaneously. In the middle of an SW node transition, the power switch provides all of the inductor current. he source-to-drain voltage of the power switch is half the input voltage, resulting in power loss. ransition losses increase with both load current and input voltage and occur twice for each switching cycle. Use the following equation to estimate transition losses: PRAN = VIN/ IOU (tr + tf) fsw where: tr is the rise time of the SW node. tf is the fall time of the SW node. RECOMMENDED BUCK EXERNAL COMPONENS he recommended buck external components for use with the ADP4 are listed in able 8 (inductors) and able 9 (capacitors). PG EN EN V IN =.6V CIN µf kω V OU =.8V 6 COU + µf ADP4 VIN PGND PG SW EN AGND EN FB VOU VIN 4 5 µh V OU =.V + COU µf Figure 86. ypical Application Circuit with LDO Connected to Input Voltage able 8.. μh Inductors Vendor Model Case Size Dimensions ISA (ma) DCR (mω) Murata LQMPNRMCD 85. mm.5 mm.5 mm 8 9 Murata LQMPNRML 6. mm.6 mm.95 mm Murata LQMHPNRMJ 8.5 mm. mm.95 mm 5 9 FDK MIPSA5DR.5 mm. mm. mm 9 able 9. μf Capacitors Vendor ype Model Case Size Voltage Rating Murata X5R GRM9R6J V aiyo Yuden X5R JMKBJ V DK X5R C68X5RJ V Rev. A Page 5 of

26 ADP4 LDO CAPACIOR SELECION Output Capacitor he ADP4 LDO is designed for operation with small, spacesaving ceramic capacitors, but functions with most commonly used capacitors as long as care is taken about the effective series resistance (ESR) value. he ESR of the output capacitor affects stability of the LDO control loop. A minimum of.7 µf capacitance with an ESR of Ω or less is recommended to ensure stability of the ADP4. ransient response to changes in load current is also affected by output capacitance. Using a larger value of output capacitance improves the transient response of the ADP4 to large changes in load current. Figure 87 shows the transient response for an output capacitance value of µf. LOAD CURREN V OU CH ma CH mv M4.µs A CH 68mA.4% Figure 87. Output ransient Response, V OU =.8 V, C OU = µf, ma to ma, Load Current Rise ime = ns Input Bypass Capacitor Connecting a µf capacitor from VIN to GND reduces the circuit sensitivity to the PCB layout, especially when long input traces or high source impedance are encountered. If greater than µf of output capacitance is required, increase the input capacitor to match it. Input and Output Capacitor Properties Use any good quality ceramic capacitors with the ADP4, as long as they meet the minimum capacitance and maximum ESR requirements. Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6. V or V are recommended for best performance. Y5V and Z5U dielectrics are not recommended for use with any LDO because of their poor temperature and dc bias characteristics. Figure 88 depicts the capacitance vs. voltage bias characteristic of a 4 µf, V, X5R capacitor. he voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating. In general, a capacitor in a larger package or higher voltage Data Sheet rating exhibits better stability. he temperature variation of the X5R dielectric is about ±5% over the 4 C to +85 C temperature range and is not a function of package or voltage rating. CAPACIANCE (µf) MURAA PAR NUMBER: GRM55R6A5KE VOLAGE (V) Figure 88. Capacitance vs. Voltage Characteristic Use Equation to determine the worst-case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage. C EFF = C BIAS ( EMPCO) ( OL) () where: C BIAS is the effective capacitance at the operating voltage. EMPCO is the worst-case capacitor temperature coefficient. OL is the worst-case component tolerance. In this example, the worst-case temperature coefficient (EMPCO) over 4 C to +85 C is assumed to be 5% for an X5R dielectric. he tolerance of the capacitor (OL) is assumed to be %, and C BIAS is.94 μf at.8 V as shown in Figure 88. Substituting these values in Equation yields C EFF =.94 μf (.5) (.) =.79 μf herefore, the capacitor chosen in this example meets the minimum capacitance requirement of the LDO over temperature and tolerance at the chosen output voltage. o guarantee the performance of the ADP4, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors are evaluated for each application. LDO AS A POSREGULAOR O REDUCE BUCK OUPU NOISE he output of the buck regulator may not be suitable for many noise sensitive applications because of its inherent switching noise. his is particularly true when the buck is operating in PSM mode because the switching noise may be in the audio range. he ADP4 LDO can greatly reduce the noise at the output of the buck at high efficiency because of the load dropout voltage of the LDO and the high PSRR of the LDO. Figure 89 and Figure 9 show the noise reduction that is possible when the LDO is used as a post regulator Rev. A Page 6 of

27 Data Sheet ADP4 BUCK OUPU VOLAGE BUCK OUPU VOLAGE LDO OUPU VOLAGE LDO OUPU VOLAGE CH 5.mV CH.mV M4.µs A CH 7.mV 48.% Figure 89. LDO as a Postregulator (see Figure ), V OU =.8 V, Load Current = 5 ma, V OU =. V, Load Current = 5 ma CH.mV CH.mV M.µs A CH 8µV 48.% Figure 9. LDO as a Postregulator (see Figure ), V OU =.8 V, Load Current = 5 ma, V OU =. V, Load Current = 5 ma Rev. A Page 7 of

28 ADP4 HERMAL CONSIDERAIONS In most applications, the ADP4 does not dissipate much heat due to its high efficiency. However, in applications with high ambient temperature and high supply voltage-to-output voltage differential, the heat dissipated in the package is large enough that it can cause the junction temperature of the die to exceed the maximum junction temperature of 5 C. When the junction temperature exceeds 5 C, the converter enters thermal shutdown. It recovers only after the junction temperature has decreased below C to prevent any permanent damage. herefore, thermal analysis for the chosen application is very important to guarantee reliable performance over all conditions. he junction temperature of the die is the sum of the ambient temperature of the environment and the temperature rise of the package due to the power dissipation, as shown in Equation. o guarantee reliable operation, the junction temperature of the ADP4 must not exceed 5 C. o ensure the junction temperature stays below this maximum value, the user needs to be aware of the parameters that contribute to junction temperature changes. hese parameters include ambient temperature, power dissipation in the power device, and thermal resistances between the junction and ambient air (θ JA ). he θ JA number is dependent on the package assembly compounds that are used and the amount of copper used to solder the package GND pins to the PCB. able shows typical θ JA values of the -lead, mm mm LFCSP for various PCB copper sizes. able. ypical θ JA Values Copper Size (mm ) θ JA ( C/W) he device is soldered to minimum size pin traces. he junction temperature of the ADP4 can be calculated from the following equation: J = A + (P D θ JA ) () where: A is the ambient temperature. P D is the total power dissipation in the die, given by P D = P LDO + P BUCK where: P LDO = [(V IN V OU ) I LOAD ] + (V IN I AGND ) () P BUCK = P SW + P RAN + P SW_COND (4) Data Sheet where: I LOAD is the LDO load current. I AGND is the analog ground current. V IN and V OU are the LDO input and output voltages, respectively. P SW, P RAN, and P SW_COND are defined in the Efficiency section. For a given ambient temperature and total power dissipation, there exists a minimum copper size requirement for the PCB to ensure the junction temperature does not rise above 5 C. he following figures show junction temperature calculations for different ambient temperatures, total power dissipation, and areas of PCB copper. JUNCION EMPERAURE ( C) JUNCION EMPERAURE ( C) mm 45 5mm 5 mm J MAX OAL POWER DISSIPAION (W) Figure 9. Junction emperature vs. Power Dissipation, A = 5 C mm 5mm 6 mm J MAX OAL POWER DISSIPAION (W) Figure 9. Junction emperature vs. Power Dissipation, A = 5 C Rev. A Page 8 of

29 Data Sheet ADP4 JUNCION EMPERAURE ( C) JUNCION EMPERAURE ( C) mm 5mm 75 mm J MAX OAL POWER DISSIPAION (W) Figure 9. Junction emperature vs. Power Dissipation, A = 65 C mm 5mm mm J MAX OAL POWER DISSIPAION (W) Figure 94. Junction emperature vs. Power Dissipation, A = 85 C In cases where the board temperature is known, use the thermal characterization parameter, Ψ JB, to estimate the junction temperature rise. Maximum junction temperature ( J ) is calculated from the board temperature ( B ) and power dissipation (P D ) using the formula J = B + (P D Ψ JB ) (5) he typical Ψ JB value for the -lead, mm mm LFCSP is 6.9 C/W PCB LAYOU CONSIDERAIONS Improve heat dissipation from the package by increasing the amount of copper attached to the pins of the ADP4. However, as listed in able, a point of diminishing returns is eventually reached, beyond which an increase in the copper size does not yield significant heat dissipation benefits. Poor layout can affect the ADP4 buck performance causing electromagnetic interference (EMI) and electromagnetic compatibility (EMC) performance, ground bounce, and voltage losses; thus, regulation and stability can be affected. Implement a good layout using the following rules: Place the inductor, input capacitor, and output capacitor close to the IC using short tracks. hese components carry high switching frequencies and long, large tracks act like antennas. Route the output voltage path away from the inductor and SW node to minimize noise and magnetic interference. Use a ground plane with several vias connected to the component-side ground to reduce noise interference on sensitive circuit nodes. Use of 4- or 6-size capacitors achieves the smallest possible footprint solution on boards where area is limited. Figure 96. PCB Layout, op 79-8 JUNCION EMPERAURE ( C) 8 6 B = 5 C 4 B = 5 C B = 65 C B = 85 C J MAX OAL POWER DISSIPAION (W) 79-8 Figure 97. PCB Layout, Bottom Figure 95. Junction emperature vs. Power Dissipation Rev. A Page 9 of