Section 39. Oscillator (Part III)

Transcription

1 Section 39. Oscillator (Part III) HIGHLIGHTS This section of the manual contains the following topics: 39.1 Introduction CPU Clocking Oscillator Configuration Registers Special Function Registers Primary Oscillator Internal Fast RC (FRC) Oscillator Phase-Locked Loop (PLL) Low-Power Secondary Oscillator (SOSC) Low-Power RC Oscillator Auxiliary Oscillator Fail-Safe Clock Monitor (FSCM) Clock Switching Two-Speed Start-Up Register Maps Related Application Notes Revision History Oscillator (Part III) 2008 Microchip Technology Inc. DS70308B-page 39-1

2 PIC24H Family Reference Manual 39.1 INTRODUCTION The PIC24H oscillator system includes these characteristics: External and Internal Oscillator options On-chip PLL to boost internal operating frequency on select internal and external oscillator sources On-the-fly clock switching between various clock sources Doze mode for system power-saving Fail-Safe Clock Monitor (FSCM) that detects clock failure and permits safe application recovery or shutdown Nonvolatile Configuration bits for clock source selection Auxiliary Crystal Oscillator for Digital-to-Analog Converter (DAC) A block diagram of the PIC24H oscillator system is shown in Figure Figure 39-1: Oscillator (Part III) System Block Diagram Primary Oscillator DOZE<2:0> OSCO OSCI POSCCLK S3 POSCMD<1:0> S1 PLL XT, HS, EC XTPLL, HSPLL, ECPLL, FRCPLL FVCO (1) S2 S1/S3 DOZE FCY 2 FRC Oscillator FRCDIV FRCDIVN S7 FOSC TUN<5:0> 16 FRCDIV<2:0> FRCDIV16 FRC S6 S0 LPRC Oscillator LPRC S5 SOSCO Secondary Oscillator SOSC S4 LPOSCEN SOSCI Clock Fail Clock Switch Reset Auxiliary Oscillator POSCCLK AOSCCLK S7 FVCO (1) NOSC<2:0> FNOSC<2:0> N ACLK WDT, PWRT, FSCM Timer1 DAC (2) AOSCMD<1:0> ASRCSEL SELACLK APSTSCLR<2:0> Note 1: See 39.7 Phase-Locked Loop (PLL) for FVCO values. 2: The DAC is not present in all PIC24H devices. Refer to the specific device data sheet for details. DS70308B-page Microchip Technology Inc.

3 Section 39. Oscillator (Part III) 39.2 CPU CLOCKING The system clock (FOSC) source can be provided by one of the following options. Primary Oscillator (POSC) on the OSCI and OSCO pins Secondary Oscillator (SOSC) on the SOSCI and SOSCO pins Internal Fast RC Oscillator (FRC) with optional clock divider Internal Low-Power RC Oscillator (LPRC) Primary Oscillator with PLL Internal Fast RC Oscillator with PLL The system clock source is divided by two to produce the internal instruction cycle clock. The instruction cycle clock is denoted by FCY. The timing diagram in Figure 39-2 shows the relationship between the system clock (FOSC), the instruction cycle clock (FCY), and the Program Counter (PC). The internal instruction cycle clock (FCY) can be output on the OSCO I/O pin, if the Primary Oscillator mode or the HS mode is not selected as the clock source (see 39.5 Primary Oscillator ). Figure 39-2: Clock/Instruction Cycle Timing TCY FOSC FCY PC PC PC + 2 PC + 4 Fetch INST (PC) Execute INST (PC - 2) Fetch INST (PC + 2) Execute INST (PC) Fetch INST (PC + 4) Execute INST (PC + 2) 39 Oscillator (Part III) 2008 Microchip Technology Inc. DS70308B-page 39-3

4 PIC24H Family Reference Manual 39.3 OSCILLATOR CONFIGURATION REGISTERS Table 39-1 lists the configuration settings that select the device oscillator source and operating mode at Power-on Reset (POR). The Configuration bits are contained in these two registers: FOSCSEL: Oscillator Source Selection Register The Oscillator Source Selection (FOSCSEL) register selects the initial oscillator source and start-up option. FOSC: Oscillator Configuration Register The Oscillator Configuration (FOSC) register configures the Primary Oscillator mode, OSCO pin function, peripheral pin select, and the fail-safe and clock switching modes. The Configuration registers are located in program memory space. They are not Special Function Registers (SFRs). They are mapped into program memory space and are programmed at the time of device programming. The Initial Oscillator Source Selection (FNOSC<2:0>) Configuration bits in the Oscillator Source Selection (FOSCSEL<2:0>) register determine the clock source that is used at a Power-on Reset. Thereafter, the clock source can be changed between permissible clock sources with clock switching. The Internal FRC Oscillator with postscaler (FRCDIVN) is the default (unprogrammed) selection. The Primary Oscillator Mode Selection (POSCMD<1:0>) Configuration bits in the Oscillator Configuration (FOSC<1:0>) register select the Operation mode of the primary oscillator. The OSCO Pin Function bit (OSCIOFNC) Configuration bit in FOSC<2> selects the OSCO pin function, except in HS or XT mode. When OSCIOFNC is unprogrammed ( 1 ), the FCY clock is output on the OSCO pin. When OSCIOFNC is programmed ( 0 ), the OSCO pin becomes a general purpose I/O pin. Table 39-1: Oscillator Source Configuration Bit Values for Clock Selection Oscillator Mode FNOSC Value POSCM D Value Note S0 Fast RC Oscillator (FRC) 000 xx 1 S1 Fast RC Oscillator with PLL (FRCPLL) 001 xx 1 S2 Primary Oscillator (EC) S2 Primary Oscillator (XT) S2 Primary Oscillator (HS) S3 Primary Oscillator with PLL (ECPLL) S3 Primary Oscillator with PLL (XTPLL) S3 Primary Oscillator with PLL (HSPLL) S4 Secondary Oscillator (SOSC) 100 xx 1 S5 Low-Power RC Oscillator 101 xx 1 S6 Fast RC Oscillator with Divide-by-16 (FRCDIV16) 110 xx 1 S7 Fast RC Oscillator with Divide-by-N (FRCDIVN) 111 xx 1, 2 Note 1: The OSCO pin function is determined by the OSCIOFNC Configuration bit. 2: The default oscillator mode for an unprogrammed (erased) device. DS70308B-page Microchip Technology Inc.

5 Section 39. Oscillator (Part III) Register 39-1: FOSCSEL: Oscillator Source Selection Register U U U U U U U U bit 15 bit 8 R/P U U U U R/P R/P R/P IESO FNOSC<2:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unused bits, program to Logic 1 -n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown bit 15-8 Reserved: Reserved bits must be programmed as 1 bit 7 IESO: Internal External Start-up Option bit 1 = Start device with Internal FRC, and then auto-switch to the user-selected oscillator source when ready 0 = Start device with user-selected oscillator source bit 6-3 Reserved: Reserved bits must be programmed as 1 bit 2-0 FNOSC<2:0>: Initial Oscillator Source Selection bits 000 = Fast RC Oscillator (FRC) 001 = Fast RC Oscillator with PLL (FRCPLL) 010 = Primary Oscillator (XT, HS, EC) 011 = Primary Oscillator with PLL (XTPLL, HSPLL, ECPLL) 100 = Secondary Oscillator (SOSC) 101 = Low-Power RC Oscillator (LPRC) 110 = Fast RC Oscillator with Divide-by-16 (FRCDIV16) 111 = Fast RC Oscillator with Divide-by-N (FRCDIVN) 39 Oscillator (Part III) 2008 Microchip Technology Inc. DS70308B-page 39-5

6 PIC24H Family Reference Manual Register 39-2: FOSC: Oscillator Configuration Register U U U U U U U U bit 15 bit 8 R/P R/P R/P U U R/P R/P R/P FCKSM<1:0> IOL1WAY OSCIOFNC POSCMD<1:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unused bits, program to Logic 1 -n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown bit 15-8 Reserved: Reserved bits must be programmed as 1 bit 7-6 FCKSM<1:0>: Clock Switching Mode bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled bit 5 IOL1WAY: Peripheral Pin Select Configuration bit 1 = Allow only one reconfiguration 0 = Allow multiple reconfigurations bit 4-3 Reserved: Reserved bits must be programmed as 1 bit 2 OSCIOFNC: OSCO Pin Function bit (except in XT and HS modes) 1 = OSCO is clock output and instruction cycle (FCY) clock is output on OSCO pin 0 = OSCO is a general purpose digital I/O pin bit 1-0 POSCMD<1:0>: Primary Oscillator Mode Selection bits 11 = Primary Oscillator disabled 10 = HS (High-Speed) Crystal Oscillator mode 01 = XT (Crystal) Oscillator mode 00 = EC (External Clock) mode DS70308B-page Microchip Technology Inc.

7 Section 39. Oscillator (Part III) 39.4 SPECIAL FUNCTION REGISTERS These Special Function Registers provide run-time control and status of the oscillator system: OSCCON: Oscillator Control Register The Oscillator Control (OSCCON) register controls clock switching and provides status information that allows the current clock source, PLL lock, and clock fail conditions to be monitored. CLKDIV: Clock Divisor Register The Clock Divisor (CLKDIV) register controls the Doze mode and selects the PLL prescaler, PLL postscaler and FRC postscaler. PLLFBD: PLL Feedback Divisor Register The PLL Feedback Divisor (PLLFBD) register selects the PLL feedback divisor. OSCTUN: FRC Oscillator Tuning Register The FRC Oscillator Tuning (OSCTUN) register is used to tune the Internal FRC Oscillator frequency in software. It allows the FRC Oscillator frequency to be adjusted over a range of ±12%. ACLKCON: Auxiliary Clock Control Register The Auxiliary Clock Control (ACLKCON) register controls the Auxiliary Oscillator mode and the auxiliary output clock divider. Note: The Oscillator Special Function Registers (OSCCON, CLKDIV, PLLFBD, OSCTUN and ACLKCON) are reset only on Power-on Reset. 39 Oscillator (Part III) 2008 Microchip Technology Inc. DS70308B-page 39-7

8 PIC24H Family Reference Manual Register 39-3: OSCCON: Oscillator Control Register U-0 R-y R-y R-y U-0 R/W-y R/W-y R/W-y COSC<2:0> NOSC<2:0> bit 15 bit 8 R/S-0 R/W-0 R-0 U-0 R/C-0 U-0 R/W-0 R/W-0 CLKLOCK IOLOCK LOCK CF LPOSCEN OSWEN bit 7 bit 0 Legend: U= Unimplemented bit, read as 0 y = Depends on FOSCSEL<FNOSC> bits R = Readable bit W = Writable bit C = Clearable only bit S = Settable only bit -n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as 0 bit COSC<2:0>: Current Oscillator Selection bits (read-only) 000 = Fast RC Oscillator (FRC) 001 = Fast RC Oscillator with PLL (FRCPLL) 010 = Primary Oscillator (XT, HS, EC) 011 = Primary Oscillator with PLL (XTPLL, HSPLL, ECPLL) 100 = Secondary Oscillator (SOSC) 101 = Low-Power RC Oscillator (LPRC) 110 = Fast RC Oscillator with Divide-by-16 (FRCDIV16) 111 = Fast RC Oscillator with Divide-by-N (FRCDIVN) bit 11 Unimplemented: Read as 0 bit 10-8 NOSC<2:0>: New Oscillator Selection bits 000 = Fast RC Oscillator (FRC) 001 = Fast RC Oscillator with PLL (FRCPLL) 010 = Primary Oscillator (XT, HS, EC) 011 = Primary Oscillator with PLL (XTPLL, HSPLL, ECPLL) 100 = Secondary Oscillator (SOSC) 101 = Low-Power RC Oscillator (LPRC) 110 = Fast RC Oscillator with Divide-by-16 (FRCDIV16) 111 = Fast RC Oscillator with Divide-by-N (FRCDIVN) bit 7 CLKLOCK: Clock Lock Enable bit If clock switching is enabled and FSCM is disabled (FOSC<FCKSM> = 01) 1 = Clock switching is disabled, system clock source is locked 0 = Clock switching is enabled, system clock source may be modified by clock switching bit 6 IOLOCK: Peripheral Pin Select Lock bit 1 = Peripheral Pin Select is locked. Writes to Peripheral Pin Select registers are not allowed 0 = Peripheral Pin Select is not locked. Writes to Peripheral Pin Select registers are allowed bit 5 LOCK: PLL Lock Status bit (read-only) 1 = Indicates that PLL is in lock, or PLL start-up timer is satisfied 0 = Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled bit 4 Unimplemented: Read as 0 bit 3 CF: Clock Fail Detect bit (read/clear by application) 1 = FSCM has detected clock failure 0 = FSCM has not detected clock failure bit 2 Unimplemented: Read as 0 bit 1 LPOSCEN: Secondary Oscillator (SOSC) Enable bit 1 = Enable Secondary Oscillator 0 = Disable Secondary Oscillator bit 0 OSWEN: Oscillator Switch Enable bit 1 = Request oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete DS70308B-page Microchip Technology Inc.

9 Section 39. Oscillator (Part III) Register 39-4: CLKDIV: Clock Divisor Register R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 ROI DOZE<2:0> DOZEN (1) FRCDIV<2:0> bit 15 bit 8 R/W-0 R/W-1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PLLPOST<1:0> PLLPRE<4:0> bit 7 bit 0 Legend: y = Value set from Configuration bits on POR R = Readable bit W = Writable bit U = Unimplemented bit, read as 0 -n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown bit 15 ROI: Recover on Interrupt bit 1 = Interrupts will clear the DOZEN bit and the processor clock/peripheral clock ratio is set to 1:1 0 = Interrupts have no effect on the DOZEN bit bit DOZE<2:0>: Processor Clock Reduction Select bits 000 = FCY/1 001 = FCY/2 010 = FCY/4 011 = FCY/8 (default) 100 = FCY/ = FCY/ = FCY/ = FCY/128 bit 11 DOZEN: DOZE Mode Enable bit (1) bit = DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks 0 = Processor clock/peripheral clock ratio forced to 1:1 FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits 000 = FRC/1 (default) 001 = FRC/2 010 = FRC/4 011 = FRC/8 100 = FRC/ = FRC/ = FRC/ = FRC/256 bit 7-6 PLLPOST<1:0>: PLL VCO Output Divider Select bits (also denoted as N2, PLL postscaler) 00 = Output/2 01 = Output/4 (default) 10 = Reserved 11 = Output/8 bit 5 Unimplemented: Read as 0 bit 4-0 PLLPRE<4:0>: PLL Phase Detector Input Divider Select bits (also denoted as N1, PLL prescaler) = Input/2 (default) = Input/ = Input/33 39 Oscillator (Part III) Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs Microchip Technology Inc. DS70308B-page 39-9

10 PIC24H Family Reference Manual Register 39-5: PLLFBD: PLL Feedback Divisor Register U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 PLLDIV<8> bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 PLLDIV<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as 0 -n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as 0 bit 8-0 PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as M, PLL multiplier) = = = = 50 (default) = 513 DS70308B-page Microchip Technology Inc.

11 Section 39. Oscillator (Part III) Register 39-6: OSCTUN: FRC Oscillator Tuning Register U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TUN<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as 0 -n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as 0 bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits = Center frequency % (8.23 MHz) = Center frequency % (8.20 MHz) = Center frequency % (7.40 MHz) = Center frequency (7.37 MHz nominal) = Center frequency % (7.345 MHz) = Center frequency % (6.52 MHz) = Center frequency - 12% (6.49 MHz) 39 Oscillator (Part III) 2008 Microchip Technology Inc. DS70308B-page 39-11

12 PIC24H Family Reference Manual Register 39-7: ACLKCON: Auxiliary Clock Control Register U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SELACLK AOSCMD<1:0> APSTSCLR<2:0> bit 15 bit 8 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 ASRCSEL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as 0 -n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown bit Unimplemented: Read as 0 bit 13 SELACLK: Select Auxiliary Clock Source for Auxiliary Clock Divider 1 = Auxiliary Oscillator provides the source clock for Auxiliary Clock Divider 0 = Fast RC (FRC) with PLL provides the source clock for Auxiliary Clock Divider bit AOSCMD<1:0>: Auxiliary Oscillator Mode 11 = EC (External Clock) Mode Select 10 = XT (Crystal) Oscillator Mode Select 01 = HS (High-Speed) Oscillator Mode Select 00 = Auxiliary Oscillator Disabled (default) bit 10-8 APSTSCLR<2:0>: Auxiliary Clock Output Divider 111 = Divided by = Divided by = Divided by = Divided by = Divided by = Divided by = Divided by = Divided by 256 (default) bit 7 ASRCSEL: Select Reference Clock Source for Auxiliary Clock 1 = Primary Oscillator is the Clock Source 0 = Auxiliary Oscillator is the Clock Source bit 6-0 Unimplemented: Read as 0 DS70308B-page Microchip Technology Inc.

13 Section 39. Oscillator (Part III) 39.5 PRIMARY OSCILLATOR The Primary Oscillator is available on the OSCI and OSCO pins of the PIC24H device. This connection enables an external crystal (or ceramic resonator) to provide the clock to the device. Optionally, the internal PLL can be used to boost the system frequency (FOSC) to 80 MHz for 40 MIPS execution. The Primary Oscillator provides the following modes of operation: Crystal Oscillator (XT Mode) The XT mode is a medium-gain, medium-frequency mode used to work with crystal frequencies of 3 MHz to 10 MHz. High-Speed Oscillator (HS Mode) The HS mode is a high-gain, high-frequency mode used to work with crystal frequencies of 10 MHz to 40 MHz. External Clock Source Operation (EC Mode) If the on-chip oscillator is not used, the EC mode allows the internal oscillator to be bypassed. The device clocks are generated from an external source (0.8 MHz to 64 MHz) and input on the OSCI pin. The Initial Oscillator Source Selection (FNOSC<2:0>) Configuration bits in the Oscillator Source Selection (FOSCSEL<2:0>) register specify the primary oscillator clock source at Power-on Reset. The Primary Oscillator Mode Selection (POSCMD<1:0>) Configuration bits in the Oscillator Configuration (FOSC<1:0>) register specify the Primary Oscillator mode. Table 39-2 shows the options selected by specific bit configurations, which are programmed at the time of device programming. Table 39-2: Primary Oscillator Clock Source Options FNOSC Value POSCMD Primary Oscillator Source/Mode Figure 39-3: C Primary Oscillator with PLL: External Clock Mode (ECPLL) Primary Oscillator with PLL: Crystal Oscillator with PLL Mode (XTPLL) Primary Oscillator with PLL: High-Speed Oscillator with PLL Mode (HSPLL) Primary Oscillator: External Clock Mode (EC) Primary Oscillator: Crystal Oscillator Mode (XT) Primary Oscillator: High-Speed Mode (HS) Figure 39-3 shows a recommended crystal oscillator circuit diagram for PIC24H devices. Capacitors C1 and C2 form the load capacitance for the crystal. The optimum load capacitance (CL) for a given crystal is specified by the crystal manufacturer. Load capacitance can be calculated as shown in Equation Crystal or Ceramic Resonator Operation (XT or HS Oscillator Mode) OSCI To Internal Logic PIC24H 39 Oscillator (Part III) XTAL POSCMD C2 OSCO 2008 Microchip Technology Inc. DS70308B-page 39-13

14 PIC24H Family Reference Manual Equation 39-1: Crystal Load Capacitance where: C S is the stray capacitance C1 C2 C L = C + S C C2 Assuming C1 = C2, Equation 39-2 gives the capacitor value (C1, C2) for a given load and stray capacitance. Equation 39-2: External Capacitor for Crystal C1 = C2 = 2 ( C L C S ) For additional information on crystal oscillators and their operation refer to Related Application Notes Oscillator Start-up Time The oscillator starts oscillating as the device voltage increases from VSS. The time required for the oscillator to start oscillating depends on the following factors: Crystal/Resonator frequency Capacitor values used (C1 and C2 in Figure 39-3) Device VDD rise time System temperature Series resistor value and type if used Oscillator mode selection of device (selects the gain of the internal oscillator inverter) Crystal quality Oscillator circuit layout System noise Figure 39-4 shows a graph of a typical oscillator/resonator start-up. Figure 39-4: Example Oscillator/Resonator Start-up Characteristics Maximum VDD of System Device VDD VIH Voltage VIL 0V Crystal Start-up Time Time To ensure that a crystal oscillator (or ceramic resonator) has started and stabilized, an Oscillator Start-up Timer (OST) is provided with the Primary Oscillator (POSC) and the Secondary Oscillator (SOSC). The OST is a simple 10-bit counter that counts 1024 cycles before releasing the oscillator clock to the rest of the system. This time-out period is denoted as TOST. The amplitude of the oscillator signal must reach the VIL and VIH thresholds for the oscillator pins before the OST can begin to count cycles. The TOST interval is required every time the oscillator restarts (i.e., on POR, BOR and wake-up from Sleep mode). DS70308B-page Microchip Technology Inc.

15 Section 39. Oscillator (Part III) Once the Primary Oscillator is enabled, it takes a finite amount of time to start oscillating. This delay is denoted as TOSCD. After TOSCD, the OST timer takes 1024 clock cycles (TOST) to release the clock. The total delay for the clock to be ready is TOSCD + TOST. If the PLL is used, an additional delay is required for the PLL to lock (see 39.7 Phase-Locked Loop (PLL) ). Primary Oscillator start-up characteristics are illustrated in Figure 39-5, where the CPU starts toggling an I/O pin when it starts execution after the TOSCD + TOST interval. Figure 39-5: Oscillator Start-up Characteristics Primary Oscillator Pin Functionality Table 39-3: Oscillator Source The Primary Oscillator pins (OSCI/OSCO) can be used for other functions when the oscillator is not being used. The POSCMD Configuration bits in the Oscillator Configuration (FOSC<1:0>) register determine the Oscillator pin function. The OSCIOFNC bit (FOSC<2>) determines the OSCO pin function. When FOSC<2> is 0, OSCO is a general purpose digital I/O pin (see Figure 39-6). When FOSC<2> is 1, OSCO is a clock output, and the instruction cycle (FCY) clock is output on the OSCO pin (see Figure 39-7). The Oscillator pin functions are shown in Table Clock Pin Function Selection OSCIOFNC<2> Value POSCMD<1:0> Value OSCI (1) Pin Function OSCO (2) Pin Function Primary OSC Disabled 1 11 Digital I/O Clock Output (FCY) Primary OSC Disabled 0 11 Digital I/O Digital I/O HS (High-Speed) X 10 OSCI OSCO XT (Crystal) X 01 OSCI OSCO EC (External Clock) 1 00 OSCI Clock Output (FCY) EC (External Clock) 0 00 OSCI Digital I/O Note 1: OSCI pin function is determined by Primary Oscillator Mode (POSCMD<1:0>) Configuration bits. 2: OSCI pin function is determined by Primary Oscillator Mode (POSCMD<1:0>) and OSCO Pin Function (OSCIOFNC<2>) Configuration bits. 39 Oscillator (Part III) 2008 Microchip Technology Inc. DS70308B-page 39-15

16 PIC24H Family Reference Manual Figure 39-6: OSCO Pin for Digital I/O (in EC Mode), FOSC<2> = 0 Clock from External System OSCI PIC24H I/O OSCO Figure 39-7: OSCO Pin for Clock Output (in EC Mode), FOSC<2> = 1 Clock from External System OSCI PIC24H FCY OSCO DS70308B-page Microchip Technology Inc.

17 Section 39. Oscillator (Part III) 39.6 INTERNAL FAST RC (FRC) OSCILLATOR The Internal Fast RC (FRC) Oscillator provides a nominal 7.37 MHz clock without requiring an external crystal or ceramic resonator, which results in system cost savings for applications that do not require a precise clock reference. The application software can tune the frequency of the oscillator from -12% to % (30 khz steps) of the nominal frequency value using the FRC Oscillator Tuning (TUN<5:0>) bits in the FRC Oscillator Tuning (OSCTUN<5:0>) register. The nominal or tuned frequency of the FRC Oscillator is expected to remain within ± 2% of the tuned value over temperature and voltage variations of a particular device. Note: Refer to the specific device data sheet for the accuracy of FRC clock frequency over temperature and voltage variations. The Internal FRC Oscillator starts up instantly. Unlike a crystal oscillator, which can take several milliseconds to begin oscillation, the Internal FRC starts oscillating immediately. The Initial Oscillator Source Selection (FNOSC<2:0>) Configuration bits in the Oscillator Source Selection (FOSCSEL<2:0>) register select the FRC clock source. The FRC Clock Source options at the time of Power-on Reset are shown in Table The Configuration bits are programmed at the time of device programming. Table 39-4: FRC Clock Source Options FNOSC<2:0> Value Primary Oscillator Source/Mode 111 FRC Oscillator: Postscaler by N (FRCDIVN) 110 FRC Oscillator: Postscaler by 16 (FRCDIV16) 001 FRC Oscillator with PLL (FRCPLL) 000 FRC Oscillator (FRC) FRC Postscaler Mode (FRCDIVN) In FRC Postscaler mode, a variable postscaler divides the FRC clock output and allows a lower frequency to be chosen. The postscaler is controlled by the Internal Fast RC Oscillator Postscaler (FRCDIV<2:0>) bits in the Clock Divisor (CLKDIV<10:8>) register. These bits allow for eight settings, from 1:1 to 1:256, as shown in Figure Table 39-5: Internal Fast RC Oscillator Postscaler Settings FRCDIV<2:0> Value Internal FRC Oscillator Setting 111 FRC divide by FRC divide by FRC divide by FRC divide by FRC divide by FRC divide by FRC divide by FRC divide by 1 (default) Optionally, the FRC postscaler output can be used with the internal PLL to boost the system frequency (FOSC) to 80 MHz for 40 MIPS instruction cycle execution speed. 39 Oscillator (Part III) Note: The FRC Divider should not be changed dynamically when operating in Internal FRC with PLL. To change the FRC divider: 1. Switch the clock to a non-pll mode (e.g., Internal FRC). 2. Make the necessary changes. 3. Switch the clock back to the PLL mode Microchip Technology Inc. DS70308B-page 39-17

18 PIC24H Family Reference Manual 39.7 PHASE-LOCKED LOOP (PLL) The Primary Oscillator and Internal FRC Oscillator sources can also be used with an on-chip PLL to obtain higher operating speeds. A block diagram of the PLL module is shown in Figure Figure 39-8: PIC24H PLL Block Diagram 0.8 < FREF < 8.0 MHz 100 < FVCO < 200 MHZ FOSC < 80 MHz FIN FREF FVCO FOSC N1 PFD VCO N2 PLLPRE<4:0> M PLLPOST<1:0> PLLDIV<8:0> For proper PLL operation, the Phase Frequency Detector (PFD) input frequency and Voltage Controlled Oscillator (VCO) output frequency must meet the following requirements: The PFD input frequency (FREF) must be in the range of 0.8 MHz to 8 MHz The VCO output frequency (FVCO) must be in the range of 100 MHz to 200 MHz The PLL Phase Detector Input Divider Select (PLLPRE<4:0>) bits in the Clock Divisor (CLKDIV<4:0>) register specify the input divider ratio (N1), which is used to scale down the input clock (FIN) to meet the PFD input frequency range of 0.8 MHz to 8 MHz. The PLL Feedback Divisor (PLLDIV<8:0>) bits in the PLL Feedback Divisor (PLLFBD<8:0>) register specify the divider ratio (M), which scales down the VCO frequency (FVCO) for feedback to the PFD. The VCO frequency (FVCO) is M times the input reference clock (FREF). The PLL VCO Output Divider Select (PLLPOST<1:0>) bits in the Clock Divisor (CLKDIV<7:6>) register specify the divider ratio (N2) to limit the system clock frequency (FOSC) to 80 MHz. Equation 39-3 gives the relation between the input frequency (FIN) and the output frequency (FOSC). Equation 39-3: FOSC Calculation FOSC M FIN ( PLLDIV + 2) = = FIN N1 N ( PLLPRE + 2) 2( PLLPOST + 1) where: N1 = PLLPRE + 2 N2 = 2 x (PLLPOST + 1) M = PLLDIV + 2 Equation 39-4 gives the relation between the input frequency (FIN) and the VCO frequency (FVCO). Equation 39-4: FVCO Calculation M FVCO FIN ( PLLDIV + 2) = FIN N1 = ( PLLPRE + 2) DS70308B-page Microchip Technology Inc.

19 Section 39. Oscillator (Part III) Input Clock Limitation at Start-up for PLL Mode Table 39-6 gives the default values of the PLL Prescaler, PLL Postscaler and PLL Feedback Divisor Configuration bits at Power-on Reset. Table 39-6: Given these reset values, the following equations give the relation between the input frequency (FIN) and PFD input frequency (FREF), and the VCO frequency (FVCO) and system clock frequency (FOSC) at Power-on Reset. Equation 39-5: PLL Mode Defaults Register Bit Field Value at POR Reset PLL Divider Ratio CLKDIV<4:0> PLLPRE<4:0> 00 N1 = 2 CLKDIV<7:6> PLLPOST<1:0> 01 N2 = 4 PLLFBD<8:0> PLLDIV<8:0> M = 50 FREF at Power-on Reset FREF = FIN = N1 0.5( FIN) Equation 39-6: FVCO at Power-on Reset FVco FIN M N1 = = FIN = 2 25( FIN) Equation 39-7: FOSC at Power-on Reset M FOSC = FIN = 6.25( FIN) N1 N2 Given the above equations at Power-on Reset, the input frequency (FIN) to the PLL module must be limited to 4 MHz < FIN < 8 MHz to comply with the VCO output frequency requirement (100M < FVCO < 200M), if the default values of PLLPRE, PLLPOST and PLLDIV are used. The Primary Oscillator can support the following input frequency ranges, which are not within the frequency limit required (4 MHz < FIN < 8 MHz) at Power-on Reset: Primary Oscillator in XT mode supports: 3 MHz to 10 MHz crystal Primary Oscillator in HS mode supports: 10 MHz to 40 MHz crystal Primary Oscillator in EC mode supports: 0.8 MHz to 64 MHz input To use the PLL when the input frequency is not within the 4 MHz to 8 MHz range, this process must be followed: 1. Power-up the device with Internal FRC or Primary Oscillator without PLL. 2. Change the PLLDIV, PLLPRE and PLLPOST bit values, based on the input frequency, to meet these PLL requirements: The PFD input frequency (FREF) must be in the range of 0.8 MHz to 8 MHz The VCO output frequency (FVCO) must be in the range of 100 MHz to 200 MHz 3. Switch the clock to the PLL mode in software. 39 Oscillator (Part III) 2008 Microchip Technology Inc. DS70308B-page 39-19

20 PIC24H Family Reference Manual PLL Lock Status Whenever the PLL input frequency, the PLL prescaler or the PLL feedback divisor is changed, the PLL requires a finite amount of time (TLOCK) to synchronize to the new settings. TLOCK is applied when PLL is selected as the clock source at Power-on Reset, or during a clock switching operation. The value of TLOCK is relative to the time at which the clock is available to the PLL input. For example, with the Primary Oscillator, TLOCK starts after the OST delay. Refer to Oscillator Start-up Time for detailed information. The PLL Lock Status (LOCK) bit in the Oscillator Control (OSCCON<5>) register is a read-only bit that indicates the Lock status of the PLL. The LOCK bit is cleared at Power-on Reset and on a clock-switch operation, when the PLL is selected as the destination clock source. It remains clear when any clock source not using the PLL is selected. It is a good practice to wait for the LOCK bit to be set before executing code after a clock switch event in which the PLL is enabled. Note: The PLL Prescaler (PLLPRE) and PLL Feedback Divisor (PLLDIV) should not be changed when operating in PLL mode. You must clock switch to a non-pll mode (e.g., Internal FRC), to make the necessary changes, and then clock switch back to the PLL mode SETUP FOR USING PLL WITH PRIMARY OSCILLATOR (POSC) The following process can be used to set up the PLL to operate the device at 40 MIPS with a 10 MHz external crystal: 1. To execute instructions at 40 MHz, ensure that the required system clock frequency is: Fosc = 2 x FCY = 80 MHz 2. Ensure that the default reset values of PLLPRE, PLLPOST and PLLDIV meet the PLL and user requirements: FREF = 0.5 FIN = 5 MHz FOSC = 6.25 FIN = 62.5 MHz FVCO = 25 FIN = 250 MHz FVCO is not meeting the PLL requirement FOSC is not meeting the user requirement 3. If the PLL and user requirements are met, directly configure the FNOSC bits (FOSCSEL<2:0>) to select the Primary Oscillator with PLL at Power-on Reset. Otherwise, if the PLL and user requirements are not met, follow these steps: a) Select the PLL postscaler to meet the VCO output frequency requirement (100 MHz < FVCO < 200 MHz): - Select a PLL postscaler ratio of N2 = 2 - Ensure that Fvco = (Fosc N2) = 160 MHz b) Select the PLL prescaler to meet the PFD input frequency requirement (0.8 MHz < FREF < 8 MHz): - Select a PLL prescaler ratio of N1 = 2 - Ensure that FREF = (FIN/N1) = 5 MHz c) Select the PLL feedback divisor to generate the required VCO output frequency based on the PFD input frequency: - Fvco = FREF x M - M = Fvco/FREF = 32 d) Configure the FNOSC bits (FOSCSEL<2:0>) to select a clock source without the PLL (e.g., Internal FRC) at Power-on Reset. e) In the main program, change the PLL prescaler, PLL postscaler and PLL feedback divisor values to those decided in the previous steps, and then perform a clock switch to the PLL mode. Example 39-1 provides the code for using PLL with the Primary Oscillator. See Clock Switching for a clock switching code example. DS70308B-page Microchip Technology Inc.

21 Section 39. Oscillator (Part III) Example 39-1: Code Example for Using PLL with Primary Oscillator (POSC) // Select Internal FRC at POR _FOSCSEL(FNOSC_FRC); // Enable Clock Switching and Configure POSC in XT mode _FOSC(FCKSM_CSECMD & OSCIOFNC_OFF & POSCMD_XT); int main() { // Configure PLL prescaler, PLL postscaler, PLL divisor PLLFBD=30; // M = 32 CLKDIVbits.PLLPOST=0; // N1 = 2 CLKDIVbits.PLLPRE=0; // N2 = 2 // Initiate Clock Switch to Primary Oscillator with PLL (NOSC = 0b011) builtin_write_oscconh(0x03); builtin_write_oscconl(0x01); // Wait for Clock switch to occur while (OSCCONbits.COSC!= 0b011); // Wait for PLL to lock while(oscconbits.lock!=1) {}; } SETUP FOR USING PLL WITH 7.37 MHz INTERNAL FRC The following process can be used to set up the PLL to operate the device at 40 MIPS with a 7.37 MHz Internal FRC. 1. To execute instructions at 40 MHz, ensure that the system clock frequency is: FOSC =2 x FCY = 80 MHz 2. Ensure that the default reset values of PLLPRE, PLLPOST and PLLDIV meet the PLL and user requirements. FREF = 0.5 FIN = 3.68 MHz FOSC = 6.25 FIN = 46 MHz FVCO = 25 FIN = 184 MHz FOSC is not meeting the user requirement 3. If the PLL and user requirements are met, directly configure the FNOSC bits (FOSCSEL<2:0>) to select the Primary Oscillator with PLL at Power-on Reset. Otherwise, if the PLL and user requirements are not met, follow these steps: a) Select the PLL postscaler to meet the VCO output frequency requirement (100 MHz < FVCO < 200 MHz): - Select a PLL postscaler ratio of N2 = 2 - Ensure that FVCO = (FOSC N2) = 160 MHz b) Select the PLL prescaler to meet the PFD input frequency requirement (0.8 MHz < FREF < 8 MHz): - Select a PLL prescaler ratio of N1 = 2 - Ensure that FREF = (Fin/N1) = 3.68 MHz c) Select the PLL feedback divisor to generate the required VCO output frequency based on the PFD input frequency: - FVCO = FREF x M - M = FVCO/FREF = 43 d) Configure the FNOSC bits (FOSCSEL<2:0>) to select a clock source without PLL (e.g., Internal FRC) at Power-on Reset. e) In the main program, change the PLL prescaler, PLL postscaler and PLL feedback divisor to meet the user and PLL requirement, and then perform a clock switch to the PLL mode. 39 Oscillator (Part III) 2008 Microchip Technology Inc. DS70308B-page 39-21

22 PIC24H Family Reference Manual Example 39-2 provides the code for using PLL with a 7.37 MHz Internal FRC. See Clock Switching for a clock switching code example. Example 39-2: Code Example for Using PLL with 7.37 MHz Internal FRC // Select Internal FRC at POR _FOSCSEL(FNOSC_FRC); // Enable Clock Switching and Configure _FOSC(FCKSM_CSECMD & OSCIOFNC_OFF); int main() { // Configure PLL prescaler, PLL postscaler, PLL divisor PLLFBD = 41; // M = 43 CLKDIVbits.PLLPOST=0; // N1 = 2 CLKDIVbits.PLLPRE=0; // N2 = 2 // Initiate Clock Switch to Internal FRC with PLL (NOSC = 0b001) builtin_write_oscconh(0x01); builtin_write_oscconl(0x01); // Wait for Clock switch to occur while (OSCCONbits.COSC!= 0b001); // Wait for PLL to lock while(oscconbits.lock!=1) {}; } DS70308B-page Microchip Technology Inc.

23 Section 39. Oscillator (Part III) 39.8 LOW-POWER SECONDARY OSCILLATOR (SOSC) The Low-Power Secondary Oscillator enables a khz crystal to be attached to the PIC24H device as a secondary crystal clock source for low-power operation. This oscillator uses the SOSCI and SOSCO pins. The Low-Power Secondary Oscillator can also drive Timer1 for real-time clock applications Secondary Oscillator for System Clock The Low-Power Secondary Oscillator is enabled as the system clock when: The Initial Oscillator Source Selection (FNOSC<2:0>) Configuration bits in the Oscillator Source Selection (FOSCSEL<2:0>) register are appropriately set to select the Secondary Oscillator at a Power-on Reset User software initiates a Clock Switch to the Secondary Oscillator for low-power operation If the Low-Power Secondary Oscillator is not being used to provide the system clock, or if the device enters Sleep mode, it is disabled to save power Secondary Oscillator Start-up Delay When the Low-Power Secondary Oscillator is enabled, it takes a finite amount of time to start oscillating. Refer to Oscillator Start-up Time for details Continuous Secondary Oscillator Operation Optionally, you can leave the Secondary Oscillator running at all times. The Secondary Oscillator is always enabled if the Secondary Oscillator Enable (LPOSCEN) bit is set in the Oscillator Control (OSCCON<1>) register. There are two reasons to leave the Low-Power Secondary Oscillator running. First, keeping the oscillator on at all times allows a fast switch to the 32 khz System Clock for lower power operation. Returning to the faster main oscillator still requires an oscillator start-up time if it is a crystal type source (see Oscillator Start-up Time ). Second, the oscillator should remain on at all times when Timer1 is being used as a real-time clock. Note: In Sleep mode, all clock sources (Primary Oscillator, Internal FRC Oscillator and LPRC Oscillator) are shut down, with the exception of the Low-Power Secondary Oscillator. The Low-Power Secondary Oscillator can be active in Sleep mode if the Secondary Oscillator Enable (LPOSCEN) bit is set in the Oscillator Control (OSCCON<1>) register. 39 Oscillator (Part III) 2008 Microchip Technology Inc. DS70308B-page 39-23

24 PIC24H Family Reference Manual 39.9 LOW-POWER RC OSCILLATOR The Low-Power RC (LPRC) Oscillator provides a nominal clock frequency of 32 khz. The LPRC is the clock source for the Power-up Timer (PWRT), Watchdog Timer (WDT), and Fail-Safe Clock Monitor (FSCM) circuits. It can also be used to provide a low-frequency clock source option for the device in those applications where power consumption is critical and timing accuracy is not required. Note: The clock frequency of the LPRC Oscillator will vary depending on the device voltage and operating temperature. Refer to the Electrical Characteristics in the specific device data sheet for details LPRC Oscillator for System Clock The LPRC Oscillator is selected as the system clock when: The Initial Oscillator Source Selection (FNOSC<2:0>) bits in the Oscillator Source Selection (FOSCSEL<2:0>) register are appropriately set to select the LPRC oscillator at Power-on Reset User software initiates a Clock Switch to the LPRC Oscillator for low-power operation Enabling the LPRC Oscillator The LPRC Oscillator is the clock source for the PWRT, WDT and FSCM. The LPRC Oscillator is enabled at Power-on Reset if the Power-on Reset Timer Value Select (FPWRT) bits in the POR Configuration Fuse (FPOR<2:0>) register. The LPRC oscillator remains enabled under these conditions: The FSCM is enabled The WDT is enabled The LPRC Oscillator is selected as the system clock If none of these conditions is true, the LPRC Oscillator shuts off after the PWRT expires. The LPRC Oscillator is shut off in Sleep mode. Note: The LPRC runs in Sleep mode only if the Watchdog Timer is enabled. Under all other conditions, the LPRC is disabled in Sleep mode LPRC Oscillator Start-up Delay The LPRC Oscillator starts up instantly, unlike a crystal oscillator, which can take several milliseconds to begin oscillation. DS70308B-page Microchip Technology Inc.

25 Section 39. Oscillator (Part III) AUXILIARY OSCILLATOR The Auxiliary Oscillator (AOSC) can be used for peripherals that need to operate at a frequency unrelated to the system clock, such as a Digital-to-Analog Converter (DAC). The Auxiliary Oscillator can use one of the following as its clock source: Crystal (XT): Crystal and ceramic resonators in the range of 3 MHz to 10 MHz High-Speed Crystal (HS): Crystals in the range of 10 MHz to 40 MHz. The external crystal is connected to the SOSCI and SOSCO pins External Clock (EC): External clock signal up to 64 MHz. The external clock signal is directly applied to the SOSCI pin Enabling the Auxiliary Oscillator To enable the Auxiliary Oscillator mode and External Oscillator mode, the appropriate Auxiliary Oscillator Mode (AOSCMD<1:0>) bits must be selected in the Auxiliary Clock Control (ACLKCON<12:11>) register. These bits allow for four oscillator mode settings, as shown in Table Once the mode has been selected, set the Select Auxiliary Clock Source for Auxiliary Clock Divider (SELACLK) bit (ACLKCON<12>) to use the Auxiliary Oscillator as the clock reference. Table 39-7: Auxiliary Oscillator and External Oscillator Mode Settings AOSCMD<1:0> Bit Value Oscillator Mode Setting 11 EC (External Clock) Mode Select 10 XT (Crystal) Oscillator Mode Select 01 HS (High-Speed) Oscillator Mode Select 00 Auxiliary Oscillator Disabled (default setting) Note: By default, the DAC module is clocked by the FRC with PLL To use the Primary Oscillator as the clock source, set the following bits in the ACLKCON register: ASRCSEL (selects primary oscillator for the reference clock) SELACLK (enables the reference clock) Auxiliary Clock Output Divider The Auxiliary Clock Output Divider (APSTSCLR<2:0>) bits in the ACLKCON<10:8> register divide the auxiliary clock, which allow a lower frequency to be chosen. These bits allow for eight postscaler settings, from 1:1 to 1:256, as shown in Table Table 39-8: Auxiliary Clock Output Divider Settings APSTSCLR<2:0> Bit Value Auxiliary Oscillator Setting 111 Divide by Divide by Divide by Divide by Divide by Divide by Divide by Divide by 256 (default setting) 39 Oscillator (Part III) 2008 Microchip Technology Inc. DS70308B-page 39-25

26 PIC24H Family Reference Manual FAIL-SAFE CLOCK MONITOR (FSCM) The Fail-Safe Clock Monitor allows the device to continue to operate in the event of an oscillator failure. The FSCM function is enabled by programming the Clock Switching Mode (FCKSM<1:0>) Configuration bits in the Oscillator Configuration (FOSC<7:6>) register at the time of device programming. When FSCM is enabled (FCKSM = 00), the LPRC Internal Oscillator will run at all times except during Sleep mode. The FSCM monitors the system clock. If it does not detect a system clock within a specific period of time (typically 2 ms, maximum 4 ms), it generates a clock failure trap and switches the system clock to the FRC oscillator. The user application then has the option to either attempt to restart the oscillator or execute a controlled shutdown. Note: The FSCM does not wake-up the device if the clock fails while the device is in Sleep mode. The FSCM takes the following actions when it switches to the FRC oscillator: The Current Oscillator Selection (COSC<2:0>) bits (OSCCON<14:12>) are loaded with 000 (Internal FRC) The Clock Fail Detect (CF) bit (OSCCON<3>) is set to indicate the clock failure The Oscillator Switch Enable (OSWEN) control bit (OSCCON<0>) is cleared to cancel any pending clock switches FSCM Delay The FSCM monitors the system clock for activity after the system clock is ready and the nominal delay (TFSCM) has elapsed. The FSCM delay (TFSCM) is applied when the FSCM is enabled and the primary or secondary oscillator is selected as the system clock. Refer to Section 8. Reset (DS70192) for additional information. Check for the most recent documentation on the Microchip web site at Note: Please refer to the Electrical Characteristics section of the specific device data sheet for TFSCM values FSCM and WDT The FSCM and the WDT both use the LPRC Oscillator as their time base. In the event of a clock failure, the WDT is unaffected and continues to run on the LPRC. DS70308B-page Microchip Technology Inc.

27 Section 39. Oscillator (Part III) CLOCK SWITCHING Clock switching can be initiated as a result of a hardware event or a software request. Typical scenarios include: Two-Speed Start-up sequence upon Power-on Reset, which initially uses the Internal FRC Oscillator for quick start-up, and then automatically switches to the selected clock source when the clock is ready Fail-Safe Clock Monitor automatically switches to the Internal FRC Oscillator on a clock failure User application software requests clock switching by setting the OSWEN bit (OSCCON<0>), causing the hardware to switch to the clock source selected by the NOSC bits (OSCCON<10:8>) when the clock is ready In each of these cases, the clock switch event assures that proper make-before-break sequence is executed. That is, the new clock source must be ready before the old clock is deactivated and code must continue to execute as clock switching occurs. With few limitations, applications are free to switch between any of the four clock sources (POSC, SOSC, FRC and LPRC) under software control at any time. To limit the possible side effects that could result from this flexibility, PIC24H devices have a safeguard lock built into the switch process. That is, the OSCCON register is write-protected during clock switching Enabling Clock Switching The Clock Switching Mode (FCKSM<1:0>) Configuration bits in the Oscillator Configuration (FOSC<7:6>) register must be programmed to enable clock switching and the Fail-Safe Clock Monitor (see Table 39-9). Table 39-9: Configurable Clock Switching Modes FCKSM<1:0> Values Clock Switching Configuration FSCM Configuration 1x Disabled Disabled 01 Enabled Disabled 00 Enabled Enabled The first bit determines if clock switching is enabled ( 0 ) or disabled ( 1 ). The second bit determines if the FSCM is enabled ( 0 ) or disabled ( 1 ). FSCM can only be enabled if clock switching is also enabled. If clock switching is disabled ( 1 ), the value of the second bit is irrelevant Clock Switch Sequence The recommended process for a clock switch is as follows: 1. Read the COSC bits (OSCCON<14:12>) to determine the current oscillator source (if this information is relevant to the application). 2. Execute the unlock sequence to allow a write to the high byte of the OSCCON register. 3. Write the appropriate value to the NOSC control bits (OSCCON<10:8>) for the new oscillator source. 4. Execute the unlock sequence to allow a write to the low byte of the OSCCON register. 5. Set the OSWEN bit (OSCCON<0>) to initiate the oscillator switch. After the above steps are completed, the clock switch logic performs the following: 1. The clock switching hardware compares the OSCCON<COSC> status bits with the new value of the NOSC control bit (OSCCON<10:8>). If they are the same, the clock switch is a redundant operation. In this case, the OSWEN bit (OSCCON<0>) is cleared automatically and the clock switch is aborted. 2. If a valid clock switch has been initiated, the PLL Lock (OSCCON<5>) and Clock Fail (OSCCON<3>) status bits are cleared. 39 Oscillator (Part III) 2008 Microchip Technology Inc. DS70308B-page 39-27

28 PIC24H Family Reference Manual 3. The new oscillator is turned on by the hardware (if it is not currently running). If a crystal oscillator (Primary or Secondary) must be turned on, the hardware waits until the OST expires. If the new source uses the PLL, the hardware waits until a PLL lock is detected (OSCCON<5> = 1). 4. The hardware waits for the new clock source to stabilize and then performs the clock switch. 5. The hardware clears the OSWEN bit (OSCCON<0>) to indicate a successful clock transition. In addition, the NOSC bit (OSCCON<10:8>) values are transferred to the COSC status bits (OSCCON<14:12>). 6. The old clock source is turned off at this time, with the exception of LPRC (if WDT or FSCM are enabled) or SOSC (if SOSCEN remains set). The timing of the transition between clock sources is shown in Figure Note 1: Clock switching between XT, HS and EC primary oscillator modes is not possible without reprogramming the device. 2: Direct clock switching between PLL modes is not possible. For example, clock switching should not occur between Primary Oscillator with PLL, and Internal FRC Oscillator with PLL. 3: Setting the CLKLOCK bit (OSCCON<7>) prevents clock switching when clock switching is enabled and fail-safe clock monitoring is disabled by the FCKSM Configuration bits (FOSC<7:6> = 01). The OSCCON<7> bit cannot be cleared once it is set by the software it clears on Power-on Reset. 4: The processor continues to execute code throughout the clock switching sequence. Timing sensitive code should not be executed during this time. Figure 39-9: Clock Transition Timing Diagram New Source Enabled New Source Stable Old Source Disabled Old Clock Source New Clock Source System Clock OSWEN Both Oscillators Active Note: The system clock can be any selected source Primary, Secondary, FRC or LPRC. DS70308B-page Microchip Technology Inc.

29 Section 39. Oscillator (Part III) A recommended code sequence for a clock switch includes the following: 1. Disable interrupts during the OSCCON register unlock and write sequence. 2. Execute the unlock sequence for the OSCCON high byte, in two back-to-back instructions: Write 0x0078 to OSCCON<15:8> Write 0x009A to OSCCON<15:8> 3. In the instruction immediately following the unlock sequence, write the new oscillator source to the NOSC control bits (OSCCON<10:8>). 4. Execute the unlock sequence for the OSCCON low byte. In two, back-to-back instructions: Write 0x0046 to OSCCON<7:0> Write 0x0057 to OSCCON<7:0> 5. In the instruction immediately following the unlock sequence, set the OSWEN bit (OSCCON<0>). 6. Continue to execute code that is not clock-sensitive (optional). 7. Check to see if OSCCON<0> is 0. If it is, the switch was successful. Note: MPLAB C30 provides built-in C language functions for unlocking the OSCCON register: builtin_write_oscconl(value) builtin_write_oscconh(value) See MPLAB IDE Help for more information. Example 39-3 provides the code sequence for unlocking the OSCCON register, and switching from FRC with PLL clock to the LPRC clock source. Example 39-3: Code Example for Clock Switching ;Place the New Oscillator Selection (NOSC=0b101) in W0 MOV #0x15,w0 ;OSCCONH (high byte) Unlock Sequence MOV #OSCCONH, w1 MOV #0x78, w2 MOV #0x9A, w3 MOV.B w2, [w1] ; Write 0x0078 MOV.B w3, [w1] ; Write 0x009A ;Set New Oscillator Selection MOV.B w0, [w1] ; Place 0x01 in W0 for setting clock switch enabled bit MOV #0x01, w0 ;OSCCONL (low byte) Unlock Sequence MOV #OSCCONL, w1 MOV #0x46, w2 MOV #0x57, w3 MOV.B w2, [w1] ; Write 0x0046 MOV.B w3, [w1] ; Write 0x Oscillator (Part III) ; Enable Clock Switch MOV.B w0, [w1] ; Request Clock Switching by Setting OSWEN bit wait: btsc OSCCONL, #OSWEN bra wait 2008 Microchip Technology Inc. DS70308B-page 39-29