Section 3. Reset HIGHLIGHTS. Reset. This section of the manual contains the following major topics:

Transcription

1 Section 3. HIGHLIGHTS This section of the manual contains the following major topics: 3.1 Introduction s and Delay Timers Registers and Status Bit Values Design Tips Related Application Notes Revision History Microchip Technology Inc. DS39503A-page 3-1

2 PIC18C Reference Manual 3.1 Introduction The reset logic is used to place the device into a known state. The source of the reset can be determined by reading the device status bits. The reset logic is designed with features that reduce system cost and increase system reliability. Devices differentiate between various kinds of reset: a) Power-on (POR) b) during normal operation c) during SLEEP d) WDT (normal operation) e) Programmable Brown-out (BOR) f) RESET Instruction g) Stack Overflow h) Stack Underflow Most registers are unaffected by a reset; their status is unknown on POR and unchanged by all other resets. The other registers are forced to a reset state on Power-on,, WDT, Brown-out, during SLEEP and by the RESET instruction. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. Status bits from the RCON register, RI, TO,PD,PORand BOR are set or cleared differently in different reset situations as indicated in Table 3-3. These bits are used in software to determine the nature of the reset. See Table 3-4 for a full description of the reset states of all registers. A simplified block diagram of the on-chip reset circuit is shown in Figure 3-1. This block diagram is a superset of reset features. To determine the features that are available on a specific device, please refer to the device s Data Sheet. Note: While the Enhanced MCU is in a reset state, the internal phase clock is held at Q1 (beginning of an instruction cycle). DS39503A-page Microchip Technology Inc.

3 Section 3. Figure 3-1: Simplified Block Diagram of On-chip Circuit RESET Instruction Stack Pointer Stack Overflow/Underflow External WDT Module rise detect SLEEP WDT Time-out Power-on Brown-out BOREN S OST/PWRT OSC1 OST 10-bit Ripple counter R Q Chip_ On-chip (1) RC OSC PWRT 10-bit Ripple counter 3 Enable PWRT Enable OSTT (2) Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin. 2: See Table 3-1 for time-out situations Microchip Technology Inc. DS39503A-page 3-3

4 PIC18C Reference Manual 3.2 s and Delay Timers Power-on (POR) The device has many sources for a device reset. Depending on the source of the reset, different delays may be initiated. These reset sources and the delays are discussed in the following subsections. A Power-on pulse is generated on-chip when rise is detected. To take advantage of thepor,justtiethepin directly (or through a resistor) to as shown in Figure 3-2.This will eliminate external RC components usually needed to create a Power-on delay. A minimum rise time for is required. See parameter D003 and parameter D004 in the Electrical Specifications section for details. Figure 3-2: Using On-Chip POR R (1) PIC18CXXX Note 1: The resistor is optional. When the device exits the reset condition (begins normal operation), the device operating parameters (voltage, frequency, temperature, etc.) must be within their operating ranges, otherwise the device will not function correctly. Ensure the delay is long enough to get all operating parameters within specification. Figure 3-3 shows a possible POR circuit for a slow power supply ramp up. The external Power-on circuit is only required if the device would exit reset before the device is in the valid operating range. The diode, D, helps discharge the capacitor quickly when powers down. Figure 3-3: External Power-on Circuit (For Slow Power-up) D R R1 PIC18CXXX C Note 1: R<40kΩ is recommended to ensure that the voltage drop across R does not violate the device s electrical specification. 2: R1 = 100Ω to 1 kω will limit any current flowing into from external capacitor C in the event of /VPP pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). DS39503A-page Microchip Technology Inc.

5 Section Power-up Timer (PWRT) The Power-up Timer provides a delay on Power-on (POR) or Brown-out (BOR). See parameter D033 in the Electrical Specifications section. The Power-up Timer operates on a dedicated internal RC oscillator. The device is kept in reset as long as the PWRT is active. The PWRT delay allows to rise to an acceptable level. A configuration bit (PWRTEN) is provided to enable/disable the Power-up Timer. Note: The power-up time delay will vary from device to device due to, temperature and process variations. See DC parameters for details Oscillator Start-up Timer (OST) Some devices require the Power-up Timer to be enabled when the Brown-out circuitry is enabled. Please refer to the device data sheet for requirements. The Oscillator Start-Up Timer (OST) provides a 1024 oscillator cycle delay (from OSC1 input) (parameter 32) after the PWRT delay is over. This ensures that the crystal oscillator or resonator has started and is stable. The OST time-out is invoked only for XT, LP and HS modes, on Power-on, Brown-out, wake-up from SLEEP, or on a transition from Timer1 input clock as the system clock to the oscillator as the system clock by clearing the SCS bit. The oscillator start-up timer is disabled for all resets and wake-ups in RC and EC modes. (See Table 3-1) The OST counts the oscillator pulses on the OSC1/CLKIN pin. The counter only starts incrementing after the amplitude of the signal reaches the oscillator input thresholds. This delay allows the crystal oscillator or resonator to stabilize before the device exits the OST delay. The length of the time-out is a function of the crystal/resonator frequency. Figure 3-4 shows the operation of the OST circuit in conjunction with the power-up timer. For low frequency crystals, this start-up time can become quite long. That is because the time it takes the low frequency oscillator to start oscillating is longer than the power-up timer s delay. The time from when the power-up timer times out to when the oscillator starts to oscillate is a dead time. There is no minimum or maximum time for this dead time (TDEADTIME), and is dependent on the time for the oscillator circuitry to have good oscillations. Figure 3-4: Oscillator Start-up Time POR or BOR Trip Point 3 Oscillator OST TIME_OUT PWRT TIME_OUT TOSC1 TOST TDEADTIME INTERNAL RESET TPWRT TOSC1 TOST = Time for the crystal oscillator to react to an oscillation level detectable by the Oscillator Start-up Timer (OST). = 1024TOSC PLL Lock Time-out When the PLL is enabled, the time-out sequence following a Power-on is different from other oscillator modes. A portion of the Power-up Timer is used to provide a fixed time-out that is sufficient for the PLL to lock to the main oscillator frequency. This PLL lock time-out TPLL (2ms nominal, Parameter 7 in the Electrical Specifications section) follows the Oscillator Start-up Time-out (OST) Microchip Technology Inc. DS39503A-page 3-5

6 PIC18C Reference Manual Power-up Sequence On power-up, the time-out sequence is as follows: First the internal POR is detected, then, if enabled, the PWRT time-out is invoked. After the PWRT time-out is over, the OST is activated. The total time-out will vary based on oscillator configuration and PWRTEN bit status. For example, in RC mode with the PWRTEN bit set (PWRT disabled), there will be no time-out at all. Figure 3-5, Figure 3-6 and Figure 3-7 depict time-out sequences. Since the time-outs occur from the internal POR pulse, if is kept low long enough, the time-outs will expire. Bringing high will begin execution immediately (Figure 3-7). This is useful for testing purposes or to synchronize more than one device operating in parallel. If the device voltage is not within the electrical specifications by the end of a time-out, the /VPP pin must be held low until the voltage is within the device specification. The use of an external RC delay is sufficient for many of these applications. On wake-up from sleep, the OST is activated for various oscillator configurations. When the PLL is activated in HS mode, an additional delay called TPLL (2 ms nominal) is added to the OST time-out to allow the necessary lock time for the PLL. See parameter D003 in the Electrical Specifications section for details. Table 3-1 shows the time-outs that occur in various situations, while Figure 3-5 through Figure 3-8 show four different cases that can happen on powering up the device. Table 3-1: Time-out in Various Situations Power-up (2) or Brown-Out (3) Oscillator Configuration PWRTEN =0 PWRTEN =1 Wake-up from SLEEP or Oscillator Switch HS with PLL enabled (1) 72 ms Tosc + 2ms 1024Tosc + 2 ms 1024Tosc + 2 ms HS, XT, LP 72 ms Tosc 1024Tosc 1024Tosc EC 72 ms External RC 72 ms Note 1: 2 ms = Nominal time required for the PLL to lock. See the Electrical Specifications section. 2: 72 ms is the nominal power-up timer delay. See the Electrical Specifications section. 3: It is recommended that the power-up timer is enabled when using the Brown-out module. Figure 3-5: Time-out Sequence on Power-up ( Tied to ) INTERNAL POR TPWRT (1) PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET Note 1: TPWRT only occurs when PWRTEN = 1. DS39503A-page Microchip Technology Inc.

7 Section 3. Figure 3-6: Time-out Sequence on Power-up ( nottiedto): Case 1 INTERNAL POR TPWRT (1) PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET Note 1: TPWRT only occurs when PWRTEN = 1. Figure 3-7: Time-out Sequence on Power-up ( nottiedto): Case 2 3 INTERNAL POR PWRT TIME-OUT TPWRT (1) TOST OST TIME-OUT INTERNAL RESET Note 1: TPWRT only occurs when PWRTEN = 1. Figure 3-8: Time-out Sequence on Power-up with Slow Rise Time ( Tied to ) 0V 5V INTERNAL POR PWRT TIME-OUT TPWRT (1) TDEADTIME OST TIME-OUT TOST INTERNAL RESET Note 1: TPWRT only occurs when PWRTEN = Microchip Technology Inc. DS39503A-page 3-7

8 PIC18C Reference Manual Figure 3-9: Time-out Sequence on POR w/ PLL Enabled ( Tied to ) IINTERNAL POR TPWRT (1) PWRT TIME-OUT TOST OST TIME-OUT TPLL PLL TIME-OUT INTERNAL RESET TOST = 1024 clock cycles. TPLL =PLLlocktime. Note 1: TPWRT only occurs when PWRTEN = 1. DS39503A-page Microchip Technology Inc.

9 Section Brown-Out (BOR) On-chip Brown-out circuitry places the device into reset when the device voltage () falls below a trip point (VBOR). This ensures that the device does not continue program execution outside the valid voltage operation range of the device. Brown-out resets are typically used in AC line applications (such as appliances) or large battery applications where large loads may be switched in (such as automotive). Appliances encounter brown-out situations during plug-in and online voltage dip. Automotive electronics encounter brown-out when the ignition key is turned. In these application scenarios, the device voltage temporarily falls below the specified operating minimum. If the brown-out circuit meets the current consumption requirements of the system, it may also be used as a voltage supervisory function. Note: Figure 3-10 shows typical brown-out situations. The Brown-out module is enabled by default. To disable the module, the BOREN configuration bit must be cleared at device programming. Figure 3-10: Before using the on-chip brown-out for a voltage supervisory function (monitor battery decay), please review the electrical specifications to ensure that they meet your requirements. Note 1: It is recommended that the power-up timer be enabled when using the BOR module. The power-up timer is enabled by programming the PWRTEN configuration bit to 0. Note 2: Some devices require the Power-up Timer to be enabled when the Brown-out circuitry is enabled. Please refer to the device data sheet for requirements. Brown-Out Situations 3 Internal parameter 33 VBOR VBOR Internal Power-up time (parameter 33) parameter 33 VBOR Internal parameter 33 (1) Note 1: The Electrical Specification Parameter (parameter 33) has a typical value of 72 ms Microchip Technology Inc. DS39503A-page 3-9

10 PIC18C Reference Manual BOR Operation The BOREN configuration bit can disable (if clear/programmed) or enable (if set) the Brown-out circuitry.if falls below VBOR (parameter D005 in the Electrical Specifications section), for greater than the Brown-out Pulse Width Time (TBOR), parameter 35, the brown-out situation will reset the chip. A reset is not guaranteed to occur if falls below VBOR for less than parameter 35. ThechipwillremaininBrown-outuntil rises above VBOR. After which, the Power-up Timer is invoked and will keep the chip in reset an additional time delay (parameter 33). If drops below VBOR while the Power-up Timer is running, the chip will go back into and the Power-up Timer will be re-initialized. Once rises above VBOR, the Power-up Timer will again start a time delay. When the BOREN bit is set, all voltages below VBOR will hold the device in the reset state. This includes during the power-up sequence. The brown-out trip point is user programmable at time of device programming. Figure 3-11 is a block diagram for the BOR circuit. Figure 3-11: Block Diagram of BOR Circuit BORV1:BORV0 BOR Configuration Bits BOREN 3to1MUX BOR VREN LVDEN EN Internally Generated Reference Voltage DS39503A-page Microchip Technology Inc.

11 Section 3. The Brown-out circuit has four available reset trip point voltages. The device selected determines which trip points make sense in an application. All devices have the trip points of 4.2V and 4.5V available. PIC18LCXXX devices add two more trip points. The first is 2.7V, while the second is dependent on the minimum operating voltage of that device. This means that the lowest trip point voltage will either be 2.5V or 1.8V. Table 3-2 shows the state of the configuration bits (BORV1:BORV0) and the BOR trip points that they select. Table 3-2: Example BOR Trip Point Levels BORV1:BORV0 Configuration Bits Minimum Voltage Trip Point Maximum Voltage Trip Point Comment V 1.86 V PIC18LCXXX Devices (w/ MIN =1.8V) V 2.58 V PIC18LCXXX Devices (w/ MIN 2.0V) V 2.78 V PIC18LCXXX Devices V 4.33 V All Devices V 4.64 V All Devices Note: The minimum voltage at which the Brown-out trip point can occur should be in the valid operating voltage range of the device. The BOR is programmable to ensure that the BOR can be optimized to the voltage-frequency of the device, since the minimum device value will depend on the frequency of operation. For example, min. at 40 MHz may be 4.2V, whereas at 2 MHz it may be 1.8V Microchip Technology Inc. DS39503A-page 3-11

12 PIC18C Reference Manual Current Implications for BOR Operation BOR Initialization There are three components to the current consumption of the BOR operation. These are: 1. Current from Internal Reference Voltage 2. Current from BOR comparator 3. Current from resistor ladder The Internal Reference Voltage is also used by the Low Voltage Detect circuitry and the A/D voltage references. The resistor ladder is also used by the Low Voltage Detect circuitry. If the Low Voltage Detect is enabled, then only the additional current of the comparator is added for enabling the BOR feature. When the module is enabled, the BOR comparator and voltage divider are enabled and consume static current. The Electrical Specifications section parameter 32 gives the current specification. The Brown-out Comparator circuit consumes current when enabled. To eliminate this current consumption, the Brown-out can be disabled by programming the Brown-out Enable configuration bit (BOREN) to '0'. The BOR module must be enabled and programmed through the device configuration bits. These include BOREN, which enables or disables the module, and BORV1:BORV0, which set the BOR voltage. DS39503A-page Microchip Technology Inc.

13 Section External Brown-Out Circuits There are some applications where the device s programmable Brown-out trip point levels may still not be at the desired level for the application. Figure 3-12 shows a circuit for external brown-out protection using the MCP100 device. Figure 3-13 and Figure 3-14 are two examples of external circuitry that may be implemented. Each option needs to be evaluated to determine if they match the requirements of the application. Figure 3-12: External Brown-Out Protection Using the MCP100 VSS MCP100 RST bypass capacitor PIC18CXXX Figure 3-13: External Brown-Out Protection Circuit 1 33 kω 10 kω Q kω PIC18CXXX Note 1: Internal Brown-out circuitry should be disabled when using this circuit. 2: Resistors should be adjusted for the characteristics of the transistor. 3: This circuit will activate reset when goes below (Vz + 0.7V) where Vz = Zener voltage. Figure 3-14: External Brown-Out Protection Circuit 2 R1 Q1 R2 40 kω PIC18CXXX Note 1: This circuit is less expensive, but less accurate. Transistor Q1 turns off when is below a certain level such that: R1 R1 + R2 =0.7V 2: Internal Brown-out circuitry should be disabled when using this circuit. 3: Resistors should be adjusted for the characteristics of the transistor Microchip Technology Inc. DS39503A-page 3-13

14 PIC18C Reference Manual 3.3 Registers and Status Bit Values Table 3-3 shows the significance of the device status bits and the initialization conditions for the RCON register. Table 3-4 shows the reset conditions for the Special Function Registers. Register 3-1 shows the bits of the RCON register and Table 3-3 shows the initialization values. Register 3-1: RCON Register Bits and Positions R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-u IPEN LWRT RI TO PD POR BOR bit 7 bit 0 Table 3-3: Status Bits, Their Significance, and the Initialization Condition for RCON Register Condition Program Counter RCON Register RI TO PD POR BOR STKFUL STKUNF Power-on 0000h u u u during normal operation 0000h 00-u uuuu u u u u u u u Software during normal operation 0000h 0u-0 uuuu 0 u u u u u u Stack Overflow during normal operation 0000h 0u-u uu11 u u u u u u 1 Stack Underflow during normal operation 0000h 0u-u uu11 u u u u u 1 u during SLEEP 0000h 00-u 10uu u 1 0 u u u u WDT 0000h 0u-u 01uu u u u u WDT Wake-up PC + 2 uu-u 00uu u 0 0 u u u u Brown-out 0000h 0u-1 11u u u Interrupt Wake-up from SLEEP PC + 2 (1) uu-u 00uu u 1 0 u u u u Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'. Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (0008h or 0018h). DS39503A-page Microchip Technology Inc.

15 Section 3. Table 3-4: Initialization Conditions for SFR Registers Register Power-on, Brown-out s WDT Instruction Stack s Wake-up via WDT or Interrupt TOSU uuuu (3) TOSH uuuu uuuu (3) TOSL uuuu uuuu (3) STKPTR uu-u uuuu (3) PCLATU u uuuu PCLATH uuuu uuuu PCL PC + 2 (2) TBLPTRU uu uuuu TBLPTRH uuuu uuuu TBLPTRL uuuu uuuu TABLAT uuuu uuuu PRODH xxxx xxxx uuuu uuuu uuuu uuuu PRODL xxxx xxxx uuuu uuuu uuuu uuuu INTCON x u uuuu uuuu (1) 3 INTCON uuuu -u-u (1) INTCON uu-u u-uu (1) INDF0 N/A N/A N/A POSTINC0 N/A N/A N/A POSTDEC0 N/A N/A N/A PREINC0 N/A N/A N/A PLUSW0 N/A N/A N/A FSR0H uuuu FSR0L xxxx xxxx uuuu uuuu uuuu uuuu WREG xxxx xxxx uuuu uuuu uuuu uuuu INDF1 N/A N/A N/A POSTINC1 N/A N/A N/A POSTDEC1 N/A N/A N/A PREINC1 N/A N/A N/A Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: The long write enable is only reset on a POR or reset. 5: The bits in the PIR, PIE, and IPR registers are device dependent. Their function and location may change from device to device Microchip Technology Inc. DS39503A-page 3-15

16 PIC18C Reference Manual Table 3-4: Initialization Conditions for SFR Registers (Continued) Register Power-on, Brown-out s WDT Instruction Stack s Wake-up via WDT or Interrupt PLUSW1 N/A N/A N/A FSR1H uuuu FSR1L xxxx xxxx uuuu uuuu uuuu uuuu BSR uuuu INDF2 N/A N/A N/A POSTINC2 N/A N/A N/A POSTDEC2 N/A N/A N/A PREINC2 N/A N/A N/A PLUSW2 N/A N/A N/A FSR2H uuuu FSR2L xxxx xxxx uuuu uuuu uuuu uuuu STATUS ---x xxxx ---u uuuu ---u uuuu TMR0H xxxx xxxx uuuu uuuu uuuu uuuu TMR0L xxxx xxxx uuuu uuuu uuuu uuuu T0CON uuuu uuuu OSCCON u LVDCON uu uuuu WDTCON u RCON (4) q qquu uu-u qquu TMR1H xxxx xxxx uuuu uuuu uuuu uuuu TMR1L xxxx xxxx uuuu uuuu uuuu uuuu T1CON u-uu uuuu u-uu uuuu TMR2 xxxx xxxx uuuu uuuu uuuu uuuu PR T2CON uuu uuuu SSPBUF xxxx xxxx uuuu uuuu uuuu uuuu SSPADD uuuu uuuu SSPSTAT uuuu uuuu SSPCON uuuu uuuu SSPCON uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: The long write enable is only reset on a POR or reset. 5: The bits in the PIR, PIE, and IPR registers are device dependent. Their function and location may change from device to device. DS39503A-page Microchip Technology Inc.

17 Section 3. Table 3-4: Initialization Conditions for SFR Registers (Continued) Register Power-on, Brown-out s WDT Instruction Stack s Wake-up via WDT or Interrupt ADRESH xxxx xxxx uuuu uuuu uuuu uuuu ADRESL xxxx xxxx uuuu uuuu uuuu uuuu ADCON uuuu uuuu ADCON u- uuuu CCPR1H xxxx xxxx uuuu uuuu uuuu uuuu CCPR1L xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON uu uuuu CCPR2H xxxx xxxx uuuu uuuu uuuu uuuu CCPR2L xxxx xxxx uuuu uuuu uuuu uuuu CCP2CON uu uuuu TMR3H xxxx xxxx uuuu uuuu uuuu uuuu TMR3L xxxx xxxx uuuu uuuu uuuu uuuu T3CON uuuu uuuu uuuu uuuu SPBRG xxxx xxxx uuuu uuuu uuuu uuuu RCREG xxxx xxxx uuuu uuuu uuuu uuuu TXREG xxxx xxxx uuuu uuuu uuuu uuuu TXSTA x u uuuu -uuu RCSTA x u uuuu uuuu IPR2 (5) 1 1 u PIR2 (5) 0 0 u (1) PIE2 (5) 0 0 u IPR1 (5) 1 1 u PIR1 (5) 0 0 u (1) PIE1 (5) 0 0 u Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: The long write enable is only reset on a POR or reset. 5: The bits in the PIR, PIE, and IPR registers are device dependent. Their function and location may change from device to device Microchip Technology Inc. DS39503A-page 3-17

18 PIC18C Reference Manual Table 3-4: Initialization Conditions for SFR Registers (Continued) Register Power-on, Brown-out s WDT Instruction Stack s Wake-up via WDT or Interrupt TRISE uuuu -uuu TRISD uuuu uuuu TRISC uuuu uuuu TRISB uuuu uuuu TRIS uuu uuuu LATE xxx uuu uuu LATD xxxx xxxx uuuu uuuu uuuu uuuu LATC xxxx xxxx uuuu uuuu uuuu uuuu LATB xxxx xxxx uuuu uuuu uuuu uuuu LATA -xxx xxxx -uuu uuuu -uuu uuuu PORTE uuu PORTD xxxx xxxx uuuu uuuu uuuu uuuu PORTC xxxx xxxx uuuu uuuu uuuu uuuu PORTB xxxx xxxx uuuu uuuu uuuu uuuu PORTA -x0x u0u uuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: The long write enable is only reset on a POR or reset. 5: The bits in the PIR, PIE, and IPR registers are device dependent. Their function and location may change from device to device. DS39503A-page Microchip Technology Inc.

19 Section Control (RCON) Register The Control (RCON) register contains flag bits to allow differentiation between resets. The Control register has seven bits. The POR (Power-on ) bit is cleared on a Power-on and is unaffected otherwise. The user sets this bit following a Power-on. On subsequent resets, if the POR bit is clear (= 0 ), it will indicate that a Power-on must have occurred. Note: The state of the BOR bit is unknown on Power-on. It must be set by the user and checked on subsequent resets to see if the BOR bit is clear, indicating a brown-out has occurred. The BOR status bit is a don't care and is not necessarily predictable if the brown-out circuit is disabled (by clearing the BOREN bit in the Configuration register). The power-down bit (PD) provides indication if the device was placed into sleep mode. It is set by a power-up, a CLRWDT instruction or by user software. The PD bit is cleared when the SLEEP instruction is executed or by user software. Register 3-2: RCON Register R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-u IPEN LWRT RI TO PD POR BOR bit 7 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts LWRT: Long Write Enable bit 1 = Enable Table Writes to internal program memory Once this bit is set, it can only be cleared by a POR or reset. 0 = Disable Table Writes to internal program memory; Table Writes only to external program memory. Unimplemented: Read as '0' RI: Instruction Flag bit 1= TheRESET instruction was not invoked 0= TheRESET instruction was executed (must be set in software after the RESET instruction is executed) TO: Time-out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction POR: Power-on Flag bit 1 = A Power-on has not occurred 0 = A Power-on occurred (must be set in software after a Power-on occurs) BOR: Brown-out Flag bit 1 = A Brown-out has not occurred 0 = A Brown-out occurred (must be set in software after a Brown-out or Power-on occurs) 3 Legend R = Readable bit W = Writable bit U = Unimplemented bit, read as 0 - n = Value at POR reset 1 = bit is set 0 = bit is cleared x = bit is unknown 2000 Microchip Technology Inc. DS39503A-page 3-19

20 PIC18C Reference Manual 3.4 Design Tips Question 1: With windowed devices, my system resets and operates properly. With an OTP device, my system does not operate properly. Answer 1: The most common reason for this is that the windowed device has not had its window covered. The background light causes the device to power-up in a different state than would typically be seen in a device where no light is present. In most cases, all the General Purpose RAM and Special Function Registers were not initialized by the application software. DS39503A-page Microchip Technology Inc.

21 Section Related Application Notes This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the Enhanced family (that is, they may be written for the Base-Line, the Mid-Range or High-End families), but the concepts are pertinent and could be used (with modification and possible limitations). The current application notes related to s are: Title Application Note # Power-up Trouble Shooting AN607 Power-up Considerations AN522 Note: Please visit the Microchip Web site for additional software code examples. These code examples are stand alone examples to assist in the understanding of the PIC18CXXX. The web address for these examples is: Microchip Technology Inc. DS39503A-page 3-21

22 PIC18C Reference Manual 3.6 Revision History Revision A This is the initial released revision of the Enhanced MCU description. DS39503A-page Microchip Technology Inc.