THE ABILITY of current control to greatly improve

Transcription

1 1028 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 14, NO. 6, NOVEMBER 1999 Discrete Time Modeling and Control of the Voltage Source Converter for Improved Disturbance Rejection P. W. Lehn and M. R. Iravani Abstract A new voltage source converter control approach is presented, based on multivariable z-domain control techniques. Using time-averaging theory in the synchronous reference frame, a linear time-varying model of the converter is developed. The new model may be directly employed as an efficient simulation tool and used as a basis for developing discrete time inverter controls. Application of digital control techniques results in current step tracking in one switching period, with zero overshoot. While dc load fluctuations are rapidly compensated through nonlinear feedforward, ac system voltage disturbances are rejected through a positive and negative sequence bias estimation scheme. As a result, the converter may operate at its current limit under even severe ac voltage unbalance and only a balanced ac current will flow, thus ensuring full protection of the semiconductor devices in all three converter legs. Experimental results validate both the time-varying simulation model as well as the proposed control design. Index Terms Converter, digital control, estimation, modeling, unbalanced operation. I. INTRODUCTION THE ABILITY of current control to greatly improve the dynamic performance of voltage source converters (VSC s) has long been known. Although much early work focused on the development of current regulation through hysteresis control [1], [2], these techniques require use of relatively high average switching frequencies and also result in unpredictable ac-side current harmonics. To overcome these two limitations, research emphasis has turned to dynamic control of pulsewidth modulation (PWM) converters. While some PWM control techniques recommend tracking of time-varying reference quantities, as is the case with predictive control [3], most rely on the tracking of dc quantities in the synchronous reference frame [4] [6]. Independent of the approach selected, however, a fast and well-damped closedloop VSC response with extremely rapid disturbance rejection should be considered the primary design requirement. Steadystate constraints, which were once the primary focus, are now more easily met than ever, due to the high-feedback gains that modern controllers employ. Thermal constraints and efficiency considerations invariably limit the switching frequencies which may be used in medium Manuscript received March 23, 1998; revised March 25, Recommended by Associate Editor, S. Y. R. Hui. The authors are with the Department of Electrical and Computer Engineering, University of Toronto, Toronto, Ont., M5S 3G4, Canada. Publisher Item Identifier S (99) and high-power inverter applications. Consequently, improved dynamics and disturbance rejection must be achieved without an associated increase in switching frequency. This paper presents a new current control approach, developed in the synchronous reference frame, which is capable of reference tracking in one switching period. This is accomplished by first developing a -frame discrete time timevarying model of the VSC which accurately models both the discrete nature of the inverter switching and the continuous time nature of the ac current and dc voltage waveforms. The proposed model may be employed for efficient simulation of the VSC in the frame. Furthermore, it is easily adapted for multioutput state space control. Rapid disturbance rejection is achieved through a combination of nonlinear feedforward and bias estimation. This eliminates classical proportional integral (PI) controllers which slow dynamics, cause overshoot, and require a lengthy integration interval to compensate disturbances. The development of the controller is broken into two sections. The first deals only with ensuring good closedloop system behavior through a combination of full state feedback for assigning the fast system dynamics and nonlinear feedforward for ensuring the elimination of steady-state errors. For many applications this alone may well already meet the required performance specifications. For more critical applications, the addition of a bias estimator, to rapidly eliminate the effect of ac bus voltage fluctuations, is proposed. The benefits of this are threefold. First, fast recovery of the dc voltage is achieved after voltage sags. Second, the unbalance in acside converter currents due to ac voltage unbalance can be eliminated. Third, with the elimination of unbalanced current components, the protection of the switches under unbalanced ac voltage conditions becomes greatly simplified and much more secure. II. THE TIME-VARYING MODEL In general, the complexity of a converter model increases with the accuracy which is demanded of it. While certain applications demand the most precise model available, control design is not one of them. What is required for control design is the simplest possible model which captures all of the relevant system dynamics. For discrete time systems, which now encompass virtually all new switch-mode converter applications, the range of dynamics which are of interest are those that can /99$ IEEE

2 LEHN AND IRAVANI: DISCRETE TIME MODELING AND CONTROL OF CONVERTER 1029 where is the converter constant and and are the - and -axis duty cycles, subject to the constraint. Substituting (4) and (5) into (1) to (3), and expressing the result in matrix form yields Fig. 1. Simplified circuit diagram of the dc supply. be captured at the given sample rate. All dynamics at or beyond the Nyquist frequency are neither controllable nor observable and their calculation is unnecessary for control design. Other effects, however, such as the converter lag and the sample and hold nature of the discrete time system, do manifest themselves within the dynamic range of interest and crude continuous time first-order minimum phase representations of these delays can be improved on. Before modeling the discrete time nature of the system, it is beneficial to first consider the case of an infinite bus connected through a balanced three-phase impedance to an ideal VSC, switching at infinite frequency. Such a circuit is shown in Fig. 1. In the frame, the familiar expression for and can be derived as a function of the line to neutral peak voltage and the peak current quantities (1) (2) Since the converter is ideal, the power into its ac terminals is all transferred losslessly to the dc side. The resulting equation for the dc capacitor is As long as the transformation into the frame occurs through a transformation matrix which varies with precisely the same constant frequency as is used in (1) and (2), the above equations are exact. In other words the transformation neither demands the original frame voltages and to be sinusoidal nor continuous. Clearly, a real VSC is not lossless, but it is possible to approximately break the losses into a term varying with the square of the current, and a constant term. From this approximation, an equivalent ac- and dc-side resistance can be introduced, where the former can simply be lumped with the ac inductor resistance, and the latter represented by the inclusion of a dc shunt resistance. Of greater importance than representing the converter losses, however, is accurate modeling of the VSC terminal voltage when the converter switching frequency takes on a finite value. The most straightforward method of dealing with this is to apply time averaging theory [7] in the frame. This results in the terminal voltage during the sampling interval from time until being approximated by (3) (4) (5) To express this system in a more standard state space form, the states are defined as, and the ac bus voltage components and the dc load current are disturbance terms. This yields the matrix equation The component should not be confused with the system inputs. Over each sampling period the system inputs, and, are constant and incorporated in the matrix. The significance of (7) is that it represents the VSC as a linear but time-varying system. This is in contrast to the conventional nonlinear time invariant representation generally used [4] [6]. Since the VSC will be digitally controlled, the evolution of the states over all time is not required and only their values at the sampling instants are of importance. These can immediately be deduced by solving the linear system of (7) where evaluation of quantities at time, are simply indicated by the superscript to compress notation. In order to evaluate the integral, it is assumed that the disturbances remain constant over one sampling period. This assumption is reasonable since all disturbance terms nominally take on dc values (since ac quantities are in the frame). The solution to (8) can then be written explicitly as where (6) (7) (8) (9) (10) For discrete time control implementations however, the computation time required to calculate the desired system inputs results in a one time step delay. This is accommodated by the model without further approximation by replacing and with their previous values. The new disturbance and state terms are therefore fed through the transition matrices of the previous time step (11) As stated, the system representation is linear time varying and the matrices and, both depend on the original system inputs and. The system will in fact respond to variations in these inputs in a nonlinear fashion, but no

3 1030 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 14, NO. 6, NOVEMBER 1999 nonlinear differential equations need be solved. Simulation of the system simply requires the evaluation of the and matrices at a rate specified by the sampling period of the implementation. For high-power VSC s, simulation time steps are therefore in the s range. III. CONTROLLER DESIGN The model developed thus far conveniently maps the states from one sample instant to the next as a function of the inputs and disturbances. What it does not offer, is a linear relation between the inputs and the states, as would be required for controller design. In order to obtain such a relation, (6) is typically linearized. In contrast, the proposed approach will assume only that the dc capacitor is sufficiently large that its voltage stays nearly constant over one sampling period. As a result, (6) is approximated by where and (12) Applying a zero-order hold to the new disturbance terms allows (12) to be transformed into the discrete time domain by analytically solving the necessary matrix exponential. This yields where the submatrix is time varying. (13) A. The Inner Current Loop An inner current loop is designed for the VSC as this will facilitate both current limiting and device protection. To design the loop, only the first two equations of (13) are considered. Defining reduced state and disturbance vectors of, and allows the equation for the current loop alone to be written where from (12) (14) Fig. 2. Block diagram of the complete inner control loop. with the input vector will be derived from, although the final VSC system inputs (15) Linearization is thereby avoided in the inner loop design, and the response of the system currents will be independent of the dc voltage level. The one element not yet accounted for in the above representation is the single time step delay resulting from the digital implementation. This can be exactly represented in the discrete time model through the addition of two states, one representing delay of the axis, the other of the axis, input component. The augmented matrix equation is then (16) In other words, the input affects only the dummy state for the initial time step, while in the subsequent time step this dummy state serves as the input for the original system. The dynamics of (16) can now be assigned through use of a full state feedback controller [8]. This involves feedback of not only the two current states, but also the two new states. This poses no problem, however, since the values of these new states are simply the values of the control input from the previous time step, and are internally available digital quantities. The input required to assign the closed-loop dynamics is then (17) where is a new input which will permit the states to be driven to a desired reference without steady-state error. Standard discrete time pole placement techniques are used to determine the matrix. For the fastest dynamics, all four poles are placed at the origin of the plane. In steady state, the error between state and reference will be zero, thus,. Also, from (16), therefore steady-state constraints stipulate that. The value of required to eliminate all steady-state error may be found from (12) and is given by (18) Thus, and are all time invariant. Defining a new time-varying input vector as allows the system to be regulated with a linear controller. All subsequent discussion will therefore deal Fig. 2 shows the structure of the complete inner current control loop. The input to the controller is. This consists of the reactive current reference, which is typically set to zero, and the active current reference, whose value will be set by the outer dc voltage loop.

4 LEHN AND IRAVANI: DISCRETE TIME MODELING AND CONTROL OF CONVERTER 1031 Fig. 3. Block diagram of the dc voltage control loop. Fig. 5. A 5-kW experimental setup. steady-state solution of the system to be found. Since full synchronization is achieved in the steady state,. Also, at the desired steady-state operating point, both the - axis current and the dc voltage are at their reference values. Solving (6) for the steady state -axis current yields (20) Fig. 4. varies. Root locus of the voltage loop as the proportional controller gain B. The DC Voltage Loop The block diagram employed for the design of the voltage controller is shown in Fig. 3. It is derived from inspection of the third equation of the discrete time model in (13), where the quantity represents the nominal -axis duty cycle. The element models the control and implementation delays introduced by the inner current control loop. The disturbance current is as shown in Fig. 1 and given by (19) In the steady state, it will be compensated by the feedforward term shown in the control diagram. Finally, the feedback element is a Tustin representation of a first-order low-pass filter with time constant, where is the sampling period of the controller. The filter is used to attenuate both sensor noise and any dc bus voltage harmonics. For control design both the disturbance and feedforward terms are neglected by assuming. With proportional control only (i.e., ), the root locus for the dc voltage control loop as a function of the proportional gain is given in Fig. 4. The dominant roots of a discrete time system are those located far from the origin. The section of the root locus shown in bold corresponds to the entire range of stable operation. Over this range, the dominant roots can be seen to be the pair on the right. Selecting these roots to be located on the curve offers a stable response with minimal voltage overshoot which is still free of oscillation. To eliminate steady-state error in the voltage loop the nonlinear feedforward term is required. This term must be determined from the original time-varying system equations given in (6). Setting the derivatives to zero allows the where the quantity is the desired dc bus voltage,, and is the measured dc load current. Since the nonlinear term is used for feedforward only, it does not affect the eigenvalues of the system. As a result, there are no negative consequences associated with allowing (20) to take on a nonlinear form. IV. EXPERIMENTAL VALIDATION The linear time-varying simulation model and the digital control design are both validated experimentally. Although simulation testing of the controls was carried out prior to their experimental implementation, results from simulation and experiment are presented in tandem to avoid redundancy. A. Experimental System Fig. 5 depicts the 5-kW laboratory system, with parameters as specified in the table. is the resistance of the coupling inductance while and are representations of the effective converter resistance and constant switching losses, as described in Section II. Controller implementation is on a C40 controller board while a space vector pulsewidth modulator is implemented in an FPGA. Communication is carried out through a PC connection PWM VSC SYSTEM khz kw kw V khz F. Based on the parameter values of the experimental system, an inner current controller is designed as per Section III. In contrast to traditional frame techniques which attempt to decouple - and -axis controllers through feedforward of the measured terms and in the and axis, respectively [4], the proposed control uses a single feedback matrix. This matrix also includes cross-coupling terms, but

5 1032 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 14, NO. 6, NOVEMBER 1999 Fig. 6. Simulated and experimental response of the inner current loop to a 20-A step in reference at exactly t =0:010 s. when put on the same basis, they are approximately 40% larger than those suggested by simple feedforward. The large discrepancy results from the fact that the proposed control considers the dynamic coupling of the - and -axis components and takes into account both the sample and hold nature of the discrete controls, as well as the single time step delay for computation. The classical approach on the other hand completely neglects the existence of converter and computational lags. Such an approach is more than acceptable if the sampling and switching periods are small in comparison to the converter dynamics, but this is contrary to the design objective of developing a fast current loop. The dc voltage control loop is designed using the root locus approach as discussed. To eliminate unwanted noise, a feedback filter with a 0.25-ms time constant is selected. Increasing this time constant unnecessarily severely limits the achievable performance of the voltage controller. Selecting a dominant root damping factor of yields a dc voltage controller gain of A/V. The selected set of roots is indicated on the root locus of Fig. 4. The remainder of the controls are implemented precisely as in Figs. 2 and 3. For the feedforward terms of (18) and (20), the quantity is the measured load current, is set to zero, and is times the rms line to line ac bus voltage. B. Simulation and Experimental Results The inner current loop performance is first tested. This is accomplished by subjecting the controls to a step change in the -axis current reference. Although this does not represent normal operation of the dc supply, it does demonstrate the inner current loop dynamics without compromising dc voltage control. The simulated and experimental responses to a 20-A step in reference current are shown in Fig. 6. Several important observations can be made from this figure. First, the simulation response is seen to perform precisely as desired reaching its reference value in two time steps without overshoot. Second, the actual experimental system responds nearly as well in practice as in simulation thus validating the dynamic control approach. Finally, excellent agreement between results from the linear time-varying simulation and from experiment can be seen. While the speed of the controller is admirable, what is perhaps more important is that it comes without any associated current overshoot. Through proper modeling of the delay elements, and elimination of integrators in the current loop, Fig. 7. Simulated and experimental response to the switching on/off of a 3300-W dc load. the normally required tradeoff between overshoot and response time is entirely avoided. A more realistic and comprehensive test is presented in Fig. 7 where the dc supply is operating in normal mode with its reactive current reference set to zero, and where a 3300-W resistive load is first switched onto, then off, the dc bus. Again very good agreement between the simulation model and the experimental system can be observed. Fig. 7 demonstrates the extremely rapid response of the dc voltage controller. Dynamics are basically as predicted by the root locus analysis and the simplified transfer function model of the voltage control loop. The selected damping factor of would be expected to translate into overshoot of 5%. The real system displays virtually no overshoot, due to the effect of significant ac system impedance. In response to a dc voltage dip, the -axis duty cycle is temporarily dropped, and recovery is extremely rapid. Saturation of the controller is generally not a concern when responding to voltage dips. When load is removed from the dc bus, however, the dc voltage rises quickly and a temporary increase in the -axis duty cycle is required. Since the nominal value of the -axis duty cycle is already over 0.8 p.u., and its maximum allowable value is 1 p.u., the controller saturates if a very large load is removed from the dc bus. Consequently response may be somewhat slower in this case. Also apparent from Fig. 7 is that the steady-state dc voltage error remains extremely small, well below 0.1% under the above operating conditions. In general, however, if large ac bus voltage fluctuations exist then steady-state dc voltage errors could approach 0.5%. If more stringent steady-state requirements exist, integral action should be added to the dc voltage control loop alone, as outlined in the Appendix, or alternatively a bias estimator could be implemented. For many applications, the control system outlined thus far would prove more than adequate. The high gain of the controllers, along with feedforward of the measured dc load

6 LEHN AND IRAVANI: DISCRETE TIME MODELING AND CONTROL OF CONVERTER 1033 current [ in (20)] make the dc voltage recovery from load changes extremely fast. Balanced three-phase load changes are also accommodated by feedforward of the ac system voltage [ in (20)]. The measured ac voltage signal, however, requires significant low-pass filtering since only the positive sequence component of the ac voltage may be compensated in this manner. As a result, recovery from substantial ac voltage disturbances is somewhat slow, requiring in the order of one cycle. V. AC BUS VOLTAGE DISTURBANCE REJECTION As stated, the designed controller already offers basic rejection of balanced ac voltage disturbances. For some applications, however, faster recovery to balanced disturbances may be required, and this can be accomplished by adopting a bias estimation approach. Of greater significance than improving response to balanced voltage changes, is to ensure proper converter operation under unbalanced ac voltage conditions. -frame approaches all suffer from the appearance of large second harmonic components in -axis currents and the dc bus voltage when the ac supply becomes unbalanced. One potentially dangerous consequence of this is that the -axis current reference limits which normally provide protection for the semiconductor devices, no longer perform their specified tasks. This is because the assumption that the -axis current be zero is no longer valid, as it too contains a second harmonic component. Even worse, the unbalanced ac voltage disturbance, which enters the control system of Fig. 2 at the same location as the feedforward term, can cause the -axis current alone to exceed its reference. Unbalanced operation can therefore result in the converter entering a steady-state mode of operation where one converter leg is operating significantly above its rated current [9]. To avoid this scenario, the effect of ac bus voltage disturbances can be countered through appropriate feedforward of both positive and negative sequence components. One obvious approach to determine these components is to take a fast Fourier transform (FFT) of the ac bus voltage. While this does indeed work, the FFT algorithm is somewhat slow. A more significant disadvantage of this approach, however, is the unavoidable existence of a residual negative sequence measurement coming from the FFT algorithm, even when the ac system voltage is completely balanced. This may result from the two line-to-line voltage sensors or antialiasing filters not quite being precisely identical (in phase and/or amplitude characteristics) or, if unsynchronized switching is used, a residual will also result from the digital FFT calculation. Since a dc supply generally has an interface inductance between 0.1 and 0.2 p.u., even small voltage errors from the feedforward result in per unit ac current errors which are five ten times larger. This is not terribly serious for the measured positive sequence component of the ac voltage which is fed forward, as the high gain of the dc bus voltage controller will suppress such error quite effectively. Negative sequence feedforward signal errors, however, result in 120-Hz ripple on the dc voltage, which the controller cannot effectively compensate. Negative sequence errors are therefore left unchecked. Since the system currents are so sensitive to minute variations in the voltage components which are fed forward, it seems appropriate to pursue an approach which exploits this high system gain. If, from the currents, the ac bus voltage could be determined, then this extreme sensitivity to voltage measurements would be avoided. A well-established control systems technique which accomplishes this is bias estimation. The basic concept is to measure the system states and, knowing the system inputs, estimate the voltage disturbance. Not only does this eliminate the sensitivity to ac voltage measurements, but, as with any estimator, its outputs attenuate the measurement noise present in the current signals as well. Finally, although estimators are sometimes seen as slow in responding to disturbances, they can in fact respond faster than any FFT approach. A. Bias Estimation Bias estimation of both positive and negative sequence voltage components will be performed simultaneously. Since it will be carried out in the frame, positive sequence components are estimated as dc quantities, while negative sequence components are estimated as coupled 120-Hz components. To reduce the computational burden on the DSP-based controller, an estimator is designed considering only the inner current loop equations. This reduced estimator may be employed since the ac system voltage has no direct effect on the dc bus voltage, as may be seen from (12). To determine the positive sequence voltage disturbance components, dc quantities are estimated in the frame by introducing the equations (21) Negative sequence appears as a coupled second harmonic oscillation in the frame and estimating these components require the introduction of the two state equations (22) Expressing this equation as and augmenting the first two rows of (12) with the above four differential equations yields where. Converting the augmented system to discrete time yields (23) (24) where and may be found without linearization, since the above system matrix is time invariant. An output function is also required for the estimator design, and this is given by (25)

7 1034 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 14, NO. 6, NOVEMBER 1999 Fig. 8. AC voltage disturbance rejection with bias estimation while supplying a 3300-W dc load. 12% dip in three-phase voltage and recovery. where, since the first two states are all measured quantities and the others are unmeasured. From (24) and (25), a discrete time estimator is designed for the system following standard linear optimal estimation techniques [8]. Naturally, the single time step digital implementation lag which the two original system inputs pass through must once again be accounted for. This can be accomplished retroactively by simply driving the estimator with the inputs from the previous time step. As the system displays no lag characteristic toward changes in state, the feedback law employs values from the present sampling instant. The final equation of the estimator therefore becomes (26) Figs. 8 and 9 show the response of the system with bias estimation to a 12% balanced and 11% unbalanced ac voltage disturbance, caused by introduction of a large (parallel RL) load on the system bus, as depicted in Fig. 5. From Fig. 8 the fast response of the bias estimation can be seen with recovery in half of a cycle. Discrepancies between simulation and experiment result from the fact that the simulation model did not include system impedance. While this could be included for modeling and simulation purposes, it does not play a role in the controller design since all bus voltage variations (independent of their cause) are compensated by the bias estimator. Also, the resulting dc voltage steady-state error is further reduced by the introduction of the bias estimation. With bias estimation, steady-state dc error is easy kept below 0.1% over the entire operating range. Fig. 9 depicts the system response to an unbalanced bus voltage disturbance occurring at 0.02 s. Initial response is for large second harmonic currents to flow in both axes as a result of the voltage unbalance. The bias estimator is capable of completely eliminating the second harmonic from the - and -axis current. The final second harmonic that occurs on Fig. 9. AC voltage disturbance rejection with bias estimation while supplying a 3300-W dc load. 11% dip in single line-to-line voltage and recovery. the -axis current is caused solely by the second harmonic current reference command which comes from the dc voltage controller, as seen in the top trace. Since this component enters the reference input, it can be directly limited and poses no problem. With zero -axis current being maintained, and a control system which offers zero overshoot to reference changes, full protection of the switches is possible by simple limiting of only the -axis reference current. Finally, to demonstrate both the current limiting ability of the proposed control as well as its ability to drive balanced current into an unbalanced system, an addition test is performed in which a more significant voltage unbalance is considered. The converter is operated at 4500-W dc output while a 24% drop in one line-to-line voltage occurs. Due to the heavy load, the inverter is no longer able to regulate the dc bus voltage, as this would require more than rated current to flow through the VSC. As a result, the converter operates at its maximum current, here set at 40 A (peak). Fig. 10 presents the response of the VSC with the proposed control. Since it is difficult to determine how much current each inverter leg is actually carrying from current traces, the sampled phase currents are shown. The ac bus voltage traces are also included to give an indication of the overall amplitude and phase change of the system bus voltage. It must be noted, however, that these quantities come from extremely low-bandwidth sensors, and they therefore do not fully capture the initial transient. The experimental results clearly demonstrate that balanced current can be maintained independent of the bus voltage conditions, as predicted.

8 LEHN AND IRAVANI: DISCRETE TIME MODELING AND CONTROL OF CONVERTER s]. This, of course, assumes assembly language coding is employed that exploits the single clock cycle multiplyaccumulate function available on DSP s. A variety of low-cost DSP s are currently available which offer more than sufficient computing power to solve all control and estimation equations in the required time. Fig. 10. AC voltage disturbance rejection with bias estimation while supplying a 4500-W dc load. 24% dip in one line-to-line voltage, resulting in current limiting control. VII. CONCLUSION A new linear time-varying VSC model is presented which accurately models both the continuous time nature of the ac system equations and the inherent discrete time nature of the converter switching. Using the linear time-varying model, a control approach is proposed which avoids linearization of the system equations. Use of multivariable digital control concepts results in improved decoupling of - and -axis current components. Through appropriate nonlinear feedforward, the traditional integral action of the current controllers is eliminated and step tracking in one switching period is achieved, without overshoot. To improve dc voltage regulation, the integral action of the voltage control loop is also removed, and a bias estimator is introduced to ensure that accurate state tracking is still achieved. Further, the bias estimator is designed to also accommodate unbalanced system voltage disturbances thus eliminating second harmonic -axis currents. This allows for straightforward and secure implementation of current protection, through limiting of the -axis reference current alone. Fig. 11. gain varies. Root locus of the voltage loop, with K p =3:7, as the integral In contrast to traditional approaches with two integrators in the current loop and one in the voltage loop, the proposed approach offers the following advantages: zero overshoot in reference current tracking; significantly faster current response, with shorter settling time; reduced dc bus voltage variations from load changes; reduction of dc ripple under imbalance; improved switch protection under imbalance. VI. COMPUTATIONAL REQUIREMENTS The proposed control approach employs significant matrix manipulation to be carried out within the digital controller. This requires use of a DSP-based controller. DSP s are architecturally optimized to solve matrix equations. Consequently, a DSP may solve the estimator equations, as an example, in only 64 single-clock-cycle instructions plus a few cycles overhead [total estimator central processing unit (CPU) time, under APPENDIX If bias estimation is not employed, design of an integral component for the voltage control loop often becomes necessary to ensure that ac bus voltage fluctuations do not result in a steady-state dc voltage error. Root locus design may again be performed, now varying the integral gain and holding the proportional gain, at the value already determined. (For the experimental system this corresponds to a value of A/V and the associated root locations with are marked in Fig. 4.) Permitting to now vary from zero to infinity results in the new system roots tracing out the locus shown in Fig. 11. The section of the locus in bold represents the entire stable operating range. Dominant roots are again on the right, however, now there are three. The gain is selected such that: damping of all three roots is high (i.e., stipulating nonoscillatory behavior); natural frequency of all the roots is as high as possible (i.e., stipulating fast response). These criteria result in the root selection marked in Fig. 11, corresponding to an integral gain of A/Vs. REFERENCES [1] B. T. Ooi, J. Salmon, J. Dixon, and A. Kulkarni, A three-phase controlled-current PWM converter with leading power factor, IEEE Trans. Ind. Applicat., vol. 23, pp , Jan [2] J. Dixon and B. T. Ooi, Indirect current control of a unity power factor sinusoidal current boost type three-phase rectifier, IEEE Trans. Ind. Electron., vol. 35, pp , Nov

9 1036 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 14, NO. 6, NOVEMBER 1999 [3] R. Wu, S. Dewan, and G. Slemon, A PWM ac to dc converter with fixed switching frequency, in IEEE-IAS Conf., 1988, pp [4] V. Blasko and V. Kaura, A new mathematical model and control of a three-phase ac dc voltage source converter, IEEE Trans. Power Electron., vol. 12, pp , Jan [5] J. Dixon and B. T. Ooi, Dynamically stabilized indirect current controlled SPWM boost type 3-phase rectifier, in IEEE-IAS Conf., 1988, pp [6] C. Schauder and H. Mehta, Vector analysis and control of advanced static VAR compensators, Proc. Inst. Elect. Eng., vol. 140, pt. C, pp , July [7] J. Kassakian, M. Schlecht, and G. Verghese, Principles of Power Electronics. Reading, MA: Addison-Wesley, [8] G. Franklin, J. Powell, and M. Workman, Digital Control of Dynamic Systems. Reading, MA: Addison-Wesley, [9] P. Rioual, H. Pouliquen, and J. P. Louis, Regulation of a PWM rectifier in the unbalanced network state using a generalized model, IEEE Trans. Power Electron., vol. 11, pp , May M. R. Iravani received the B.Sc. degree in electrical engineering in 1976 from Tehran Polytechnique University in 1976 and the M.Sc. and Ph.D. degrees in electrical engineering from the University of Manitoba, Canada, in 1981 and 1985, respectively. He was a Consulting Engineer. Currently, he is a Professor at the University of Toronto, Toronto, Ont., Canada. His research interests include power electronics and power system dynamics and control. P. W. Lehn received the B.Sc. and M.Sc. degrees in electrical engineering from the University of Manitoba, Canada, in 1990 and 1992, respectively, and the Ph.D. degree from the University of Toronto, Toronto, Ont., Canada, in From 1992 until 1994, he was with the Network Planning Group of Siemens AG, Erlangen, Germany. Currently, he is an Assistant Professor at the University of Toronto. His research interests include analytical modeling of nonlinear and switched circuits.