Applying FPGA-based Chip to Apparent Power and Power Factor Measurement Considering Nonsinusoidal and Unbalanced Conditions

Transcription

1 hu-chen Wang, Chi-Jui Wu, heng-wen Yang Applying FPGA-based Chip to Apparent Power and Power Factor Measurement Considering Nonsinusoidal and Unbalanced Conditions HU-CHEN WANG Department of Computer and Communication Engineering aipei College of Maritime echnology aipei, aiwan CHI-JUI WU, Dep. of Electrical Engineering, National aiwan University of cience and echnology aipei, aiwan HENG-WEN YANG Dep. of Electrical Engineering, National aiwan University of cience and echnology aipei, aiwan Abstract: - his paper proposes a field-programmable gate array (FPGA)-based integrated circuit (IC) for computing apparent powers and power factors of power systems. In a nonsinusoidal and unbalanced three-phase power system, the calculation of apparent powers and power factors has many definitions. Load characteristics of harmonic and unbalance can not be expressed in the traditional apparent power and power factor, which only consider the fundamental and three-phase balanced sinusoidal conditions. his paper utilizes the FPGA chip to develop the platform to implement the calculation methods of apparent powers and power factors. he proposed design scheme is developed using the very high speed integrated-circuit hardware description language (VHDL), which provides high flexibility and technology independence. his paper discussed the effective power and power factor, the arithmetic power and power factor, and the fundamental power and power factor. he design of filters for the computation of fundamental frequency components is given. Modelim is used at first to simulate the calculation of apparent powers and power factors to ensure the accuracy of timing and function. Research results show that the designed chip can compute accurately the apparent powers and power factors considering the effects of nonsinusoidal and unbalanced conditions. Key-Words: - FPGA, oc, Power Factor, Harmonic, Unbalanced Power ystem. Introduction he nonlinear and fluctuating loads would cause power quality disturbances [-4]. he value of power factor generally is an important penalty factor in the revenue of electricity customers. However, the traditional power factor definition always assumes that the load condition is sinusoidal. he effects of load unbalance and harmonic distortion are neglected. It has been reported that if traditional electro-mechanical meters are used in circumstances of nonsinusoidal and three-phase unbalanced voltages or currents, the errors can reach 0%~0% [5]. In recent years, there are many discussions regarding the power definitions and calculations [6-]. everal definitions are given in the IEEE td. 459, such as effective apparent power, arithmetic apparent power, and vector apparent power. ince harmonic pollution, load unbalance, and reactive power fluctuation could affect the power factor values of customers, six different definitions of power factor values have been investigated for the same recorded measurement data of customers in []. he different results of calculation are dependent on the load characteristics. In [], it is shown that the currently used apparent power definitions, namely the Arithmetic VA and the Vector VA, both lack an important property. he usage and performance of FPGA has risen significantly in recent years for its reconfigurability and flexibility. he FPGA has been applied to analyzing and controlling a power system [4-5]. he major difference between FPGA and DP-based solutions is that FPGA enables simultaneous execution of all control subroutines, which allows IN: Issue 7, Volume 8, July 009

2 hu-chen Wang, Chi-Jui Wu, heng-wen Yang high performance and novel control methods [6]. While conventional designs are based on functions, FPGA is based on the reuse of IP or the function assembly. When a large system is constructed from a number of macro-modules, IP cores can be used to represent those modules. everal particular functional IP cores such as CORDIC and FF cores could be developed. VHDL was also employed to model a digital control system at many levels [7]. VHDL can be considered as a combination of sequential, concurrent, netlist, timing specification, and waveform generation languages. It utilizes the top/down design methodology and can be used to model a complete digital electronic system. he design benefits include easy error correction and technology independence. he same algorithm can be synthesized into any other FPGA. ince good definitions of apparent powers and power factors may well reflect the practical situations of three-phase unbalanced and non-sinusoidal circuits, the effective power, effective power factor, arithmetic power, and arithmetic power factor are investigated in this paper. he calculation algorithms will be implemented by using a FPGA-based chip [8-9]. he methods to obtain the fundamental frequency components are also compared. he effects of nonsinusoidal and unbalanced conditions in a three-phase power system are alsoconsidered. Power Factor Definition. ingle-phase system For a single-phase load under sinusoidal condition, the instantaneous voltage and current are, respectively, v(t) V sin( ωt + α) () i(t) Isin( ωt + β) () Hence the apparent power, active power, and reactive power are, respectively, VI () P VIcosθ (4) where θ α β is the phase angle difference between voltage and current. Q VIsinθ (5) P P (6) PF P + Q When a single-phase system is under non-sinusoidal situation, the instantaneous voltage and current values can be v () t V + V sin( hω + α ) (7) where t 0 h h () t I + I sin( hωt 0 h h i + β ) (8) h h V 0 :average voltage I 0 :average current V h, :rms values of harmonic voltages I h, :rms values of harmonic currents α h :phase angles of harmonic voltages β h :phase angles harmonic currents he root mean squared (rms) values are give by h 0 V RM V h (9) (0) I RM I h h 0 he apparent power, active power, and reactive power are V I () RM RM P V I cos α β () ( ) h h h h h0 V I sin α β B h h h h h Q ( ) () hen the power factor is defined as P P (4) PF P + QB Because P + Q. here is a definition of the distortion power as D P Q (5) B. hree-phase system Arithmetic apparent power and arithmetic power factor are, respectively + + V I + V I + V I (6) A R R R B P (7) PF A A Effective apparent power and effective power factor are, respectively e VeI (8) e P (9) PF e In a three-phase four-wire system: Effective current IR + I + I + IN Ie Effective voltage V e ( VR + V + V ) + ( VR + V + 8 [ V )] In a three-phase three-wire system: Effective current IR + I + I Ie Effective voltage e R (0) () () IN: Issue 7, Volume 8, July 009

3 hu-chen Wang, Chi-Jui Wu, heng-wen Yang VR + V + VR () Ve 9 he fundamental apparent power and fundamental power factor are, respectively + + V I + V I + V I (4) A R R R P (5) PF A A In this paper, there are three definitions for the average power factor. (a) average arithmetic power factor P() t dt (6) PF A ()dt t A (b) average effective power factor P t dt PF e e () () t (c) average fundamental power factor P() t dt PF A () t dt A dt (7) (8). Evaluate of harmonic and unbalance load he effective voltage and current of fundamental components of the three-phase four-wire system are given by (9) [ ( V + V + V ) + ( V + V V )] V e R R + R 8 IR + I + I + IN Ie (0) hose of the three-phase three-wire system are given by VR + V + VR () Ve 9 IR + I + I Ie () he fundamental effective apparent power is V I () e e e hen, the nonfundamental effective apparent power is (4) en e e he normalized nonfundamental effective apparent power is en en (5) e When there is an unbalanced three-phase situation, the fundamental positive-sequence apparent power is ( ) ( ) V I P + Q (6) where + V ( V R+aV +a V) + I ( I R+ ai + a I ),a 0 0 he unbalanced fundamental apparent power is + ( ) U e (7) he normalized fundamental unbalanced apparent power is (8) U U + Low-Pass Filter In calculation of the fundamental frequency components, the low-pass filter is used to obtain the 60-Hz components and reject harmonic components. he impulse response of the filter is computed by Matlab. Infinite-duration impulse response (IIR) digital filters have the input-output characteristics which are governed by linear constant-coefficient difference equations of a recursive nature. he transfer function of an IIR digital filter is a rational function in z -. Consequently, for a prescribed frequency response, the use of an IIR digital filter generally results in a shorter filter length. However, the improvement is achieved at the expense of phase distortion and a transient start-up interval. Finite-duration impulse response (FIR) digital filters have the operation which is governed by liner constant-coefficient difference of nonrecursive nature. he transfer function of an FIR digital filter is a polynomial in z -. Consequently, the FIR digital filters exhibit three important properties: (a) FIR filters can realize a desired magnitude response with an exactly liner phase response without phase distortion. (b) FIR filters are always BIBO. (c) FIR filters have finite memory, and transient star-up duration is limited. his paper uses FIR filters to strain harmonic components and utilizes Kaiser window filter design method. he band characteristics of a low-pass filter are given in Fig.. he cutoff frequency of the ideal low-pass filter should let IN: Issue 7, Volume 8, July 009

4 hu-chen Wang, Chi-Jui Wu, heng-wen Yang As ABLE I Kaiser Parameter β ω M ω P 40dB π 0.098π 7 ( e jω ) + δ δ δ ω p ωs Fig.. Band characteristics of a low-pass filter. Magnitude of (jw) db FIR Lowpass Filter Designed Using Kaiser Window Frequency Hz Fig.. Low-pass filter designed by Kaiser window. V RM 0V 60Hz Fig.. ingle-phase circuit including harmonic current sources. ABLE II etting of fundamental frequency components f P Q Voltage (Hz) (W) (VAR) PF 0(V) ABLE III harmonic current (A) I I 5 I 7 I 9 I ω ω + ω p s ω (9) c ω : the passband cutoff freuency ω : the stopband cutoff freuency p It is determined empirically that the values of β need to achieve a specified value of A s, and is give by 0.0(As 8.7) As > (As ) β (As ) As 50 0 As < (40) A s is the attenuation parameter of stop band. As As > 4.6 Δf (4) M As Δf he Kaiser parameters used in this paper is given in ABLE I. he spectrum characteristics are given in Fig.. he FIR filter has the good ability to filter our the higher frequency components and the fundamental frequency components can be obtained. 4 Calculation of Fundamental Frequency Components he simulation blocks were developed using the imulink and im Power ystems, which work together with the MALAB. he simulation model is shown in Fig.. ABLE II reveals parameters of fundamental components. ABLE III gives the harnomic currents. he use of FF and FIR filters to obtain the fundamental frequency components are compared. he Xilinx IE offers free library of IP that have been verified so that users can program directly. Introduction of model is as follows: () Fast Fourier ransform he FF core computes an N-point forward DF or inverse DF (IDF) where N can be m. he input data are a vector of N complex values represented as bx-bit two s-complement numbers. he bx bits for each of the real and imaginary components of the data sample are bx8~4. imilarly, the phase factors bw can be 8~4 bits wide. In this paper, the transfer function length is 64 and the input data width is bit. he fundamental frequency components can be obtaind from the results of FF. he FF formulas are as follows: IN: Issue 7, Volume 8, July 009

5 hu-chen Wang, Chi-Jui Wu, heng-wen Yang ABLE IV Fundamental Power Factor of FIR V I (V) (A) (VA) (W) PF Matlab FPGA Error(%) ABLE V Fundamental Power Factor of FF V I (V) (A) (VA) (W) PF Matlab FPGA Error(%) ABLE VI FPGA utilization summary of FIR Logic Utilization Used Available Utilization lice Flip Flops % LUs % lices % IOBs % MUL8 8 4 % Clk 8 % Global immig Constraints Period Offset in Offset out P P 8.79(ns) 4.6(ns) 8.59(ns) ABLE VII FPGA utilization summary of FF Logic Utilization Used Available Utilization lice Flip Flops % LUs % lices % IOBs % MUL % Clk 8 % Global immig Constraints V R 0V Period Offset in Offset out Vrs 6.45(ns).8(ns) 9.558(ns) Fig. 4. hree-phase four-wire simulation system ABLE VIII Load parameter of each phase Voltage f (Hz) P (W) Q (VAR) Load PF 0(V) Inductive ABLE IX hree-phase load cases Load Case Case Case Case 4 category U (%) 0 0~00 0 0~00 en (%) 0 0 0~00 00 Loading Conditions balanced unbalanced balanced unbalanced inductive inductive inductive inductive without harmonics without harmonics with harmonics with harmonics Fig. 5. ystematic structure diagram of calculation. V (n) * xk (n) + xk (n) (4) rms re im N xk (n) im V (n) tan (4) θ xk (n) V (n) : rms value of harmonic, n,... rms V (n) : angle of harmonic, n,.. θ xk (n) : real components of harmonic, n,.. re xk (n) : imaginary components of harmonic, n,.. im he detailed of FF is given in Appendix. () Distributed Arithmetic FIR Filter he FIR core filters are used to strain harmonic components. he lengths and coefficients of FIR filters are calculated of Matlab. he filter coefficients are supplied to the filter compiler using a coefficient file with a coe extension. An AII text file with a single-line header that defines the radix of the number representation is used for the coefficient data, followed by the coefficient values themselves. For an N-tap filter, it is described as radixcoefficient_radix; coefdata a(0), a(), a(),. a(n-); re IN: Issue 7, Volume 8, July 009

6 hu-chen Wang, Chi-Jui Wu, heng-wen Yang PF Fig. 9. PF vs U (%) PF A PF e U (%) in Case 4. PF A Fig. 6. he flowchart of FPGA design circuit. PF PF U (%) PF e PF A Fig. 7. PF vs U (%) in Case PF A Fig. 8. PF vs en (%) PF e PF A PF A en (%) in Case. () CORDIC core.0 he model features vector rotation (polar to rectangular), vector translation (rectangular to polar), trigonometric function, and square root calculation are used. Magnitude of FF uses square root operation of CORDIC core.0 IP. (4) Results he computaton results are given in ABLE IV and V by using FIR filter and FF, respectively. he method by using the FF is more accurate. However, the errors by using the FIR filters are acceptable. he FPGA utilization conditions are given in ABLE VI and VII. It can be found that the approach by usin the FIR filters has a lower computation loading. he FIR filters are used for the following study in this paper. 5 hree-phase ystem he simulation block to generator the test data is developed by using the imulink and im Power ystems, which work together with the MALAB [0]. he simulation model is shown in Fig. 4. here are four given loading cases in investigating the power factor calculation, as shown in ABLE VIII and IX, based on the properties of fundamental powers and harmonic currents. he systematic structure diagram of calculation using FPGA is given in Fig. 5. Fig. 6 reveals the flowchart of FPGA design circuit. he most important issue in designing the calculation IC is the choice of numerical data processing schemes. A floating-point arithmetic method has the advantage of a wide dynamic range, but its hardware realization is very complicated. A fixed-point arithmetic scheme is a more practical solution to most industrial applications with simple circuit realization. he proper numerical data scaling plays a significant role in synthesizing an integer controller. In this study, numerical variables and parameters must be transformed into approximate integers with finite word lengths. IN: Issue 7, Volume 8, July 009

7 hu-chen Wang, Chi-Jui Wu, heng-wen Yang ABLE X Utilization conditions of FPGA in calculating effective power factor Logic Utilization Used Available Utilization lice Flip Flops % LUs % lices 77 0% IOBs % MUL % Clk 8 % Global iming Constraints Period Offset in Offset out.4(ns) 4.899(ns) 8.896(ns) ABLE XI Utilization conditions of FPGA in calculating arithmetic power factor Logic Utilization Used Available Utilization lice Flip Flops % LUs % lices 4 6% IOBs % MUL % Clk 8 % Global Period 9.87(ns) iming Offset in 4.899(ns) Constraints Offset out 7.4(ns) ABLE XII Utilization conditions of FPGA in calculating fundamental power Logic Utilization Used Available Utilization lice Flip Flops % LUs % lices 00 97% IOBs % MUL % Clk 8 % Global Period.0(ns) iming Offset in 0.6(ns) Constraints Offset out 8.59(ns) ABLE XIII Power factor values in Case PF e PF A PF A Matlab FPGA Error(%) he test data are obtained as follows. () he 0-V (line-to-line) symmetrical three-phase voltage source block is used. () he three-phase loads are composed of series RLC load blocks and the harmonic current source blocks. he series RLC load blocks can be assigned the fundamental active and reactive powers. hen it is to use the im command to adjust unbalance level and harmonic level. () he instantaneous line-to-line voltages and line currents of the three-phase cases can be obtained by the measurement blocks. he sampling rate is 840 sample/second. (4) hen the instantaneous voltages and current values are sent to calculate apparent powers and power factors. Because float-point calculations need large RAM capacity and long operation time, the instantaneous voltage and current values are mapped to integral values. he procedures are as follows: (a) It is to normalize them to per-unit values. All instantaneous values are divided by the rms value. he rms value of the voltage is 0V and that of the fundamental current is 4.45A in case. (b) hen all per-unit values are multiplied by 000 to increase the effective bit number in FPGA. (c) he calculation error by FPGA is defined as given value(matlab)-calculated value( FPGA) ε (%) 00% given value( Matlab) (44) 6 Apparent Power and Power Factor Calculation Results Figs. 7-9 show the trend of PF e, PF A, and PF A versus U and en. he FPGA routing diagram is given in Fig. 0. Fig.. gives the timing simulation of the calculation IC. he utilization conditions of FPGA are given in ABLE X, XI, and XII. ome observations can be obtained. (a) (b) In Case, the three-phase system is balanced and without harmonic loads. he power factor values are given in ABLE XIII. o the values of three power factors are the same. In Case, the three-phase system is unbalanced but with harmonic loads. he distortion power is zero. Because PF A and PF A do not drop with U, they do not reflect the unbalance degree. Only PF e drops with of U, so that it can reflect the effect of unbalance degree. he analytical results reveal that PF e <PF A PF A. IN: Issue 7, Volume 8, July 009

8 hu-chen Wang, Chi-Jui Wu, heng-wen Yang (c) (d) Case considers the effects of harmonic distortion. he analytical results reveal that since PF A only considers the fundamental components, the harmonic distortion is disregarded. herefore, the values are equal to those in Case. he analytical results reveal that PF e PF A < PF A. he higher the harmonic distortion is, the less PF e and PF A are. Case 4 simultaneously considers the effects of harmonic distortion and unbalance. ome power factor values are given in ABLE XIV. he analytical results reveal that PF e <PF A < PF A. 7 Conclusion his study has presented an FPGA-based calculation IC for obtaining the apparent power and power factor values of three-phase power systems. he design scheme has advantages of concurrent operation, small hardware requirement, and easy and fast circuit modification. Adopting VHDL provides sufficient flexibility and speed to construct the design circuits by some IP cores. All modules were designed and integrated to others. he major benefit of the proposed approach is that it executes all logics continuously and simultaneously. he calculation of apparent powers and power factors are implemented in FPGA considering the effects of harmonic and unbalanced conditions. A lot of algorithms are written into IP on FPGA. he calculation results of power factors have the average error about 0.5%. In the FPGA chip utilization rates, the calculation procedures of fundamental power factor are the highest, and the calculation method of arithmetic the lowest. In calculating time of the procedures of the arithmetic factor is the fastest. he results reveal that the FPGA chip can be used to calculate the power factor values accurately. Fig. 0. FPGA routing diagram Fig.. iming simulation of the calculation IC. References: [] Y. Wang and J. Jiang, Mitigation of Electric Arc Furnace Voltage Flicker using tatic ynchronous Compensator, WEA rans. on Power ystems, Vol., Issue 0, 006, pp [] R. Faranda, M. Giussani, and G. estin, RC Filters Employment for the Protection of Industrial Arc Furnace ransformers during witching off Operations, WEA rans. on Heat and Mass ransfer, Vol., Issue 8, 006, pp [].A. uflis, I.E. Chatzakis, F.V. opalis, and M.B. Kostic, cenarios for a Large cale Installation of Compact Fluorescent Lamps: Influence on the Power Quality, WEA rans. on Circuits and ystems, Vol., Issue 5, 004, pp [4] W.Z. Li, W. Liao, and P. Han, Application of Wavelet Network for Detection and Localization of Power Quality Disturbances, WEA rans. on Power ystems, Vol., Issue, 006, pp [5] IEEE Working Group on Nonsinusoidal ituations: Effects on Meter performance and Definitions of Power, Practical definitions for powers in systems with nonsinusoidal waveforms and unbalanced loads: a discussion, IN: Issue 7, Volume 8, July 009

9 hu-chen Wang, Chi-Jui Wu, heng-wen Yang IEEE rans. on Power Delivery, Vol., No., 996, pp [6] P.. Filipski, Y. Baghzouz, and M. D. Cox, Discussion of power definitions contained in the IEEE dictionary, IEEE rans on Power Delivery, Vol. 9, No., 994, pp [7] IEEE Working Group on Nonsinusoidal ituations, A survey of North American electric utility concerns regarding nonsinusoidal waveforms, IEEE rans. on Power Delivery, Vol., No., 996, pp [8] IEEE td , IEEE rial-use tandard Definitions for the Measurement of Electric Power Quantities Under inusoidal, Nonsinusoidal, Balanced, or Unbalanced Conditions, New York, 000. [9] A. E. Emanuel, Apparent power definitions for three-phase systems, IEEE rans. on Power Delivery, Vol. 4, No., 999, pp [0] L.. Czarnecki, Power related phenomena in three-phase unbalanced systems, IEEE rans. on Power Delivery, Vol. 0, No., 995, pp [] C. J. Wu,. H. Fu, J. and L. Yen, Power Factor Investigation and Analysis of Large-size Customers, research report, Power Research Institute, aiwan Power Company, 99. [] A. E. Emanuel, Apparent power definitions for three-phase systems, IEEE rans. on Power Delivery, Vol. 4, No., 999, pp [] C. J Wu, C. P. Huang,. H. Fu,. C. Zhao and H.. Kuo, Power Factor Investigation of Electric Arc Furnace Loads: Comparison of IEEE tandard And Other Definitions, International Journal of Electrical Engineering, Vol., No., 004, PP.9-0. [4] J. H. Anderson and F. N. Najm, Active Leakage Power Optimization for FPGAs, IEEE ransactions on Computer-Aided Design of Integrated Circuits and ystems, Vol. 5, No., pp. 4-47, 006. [5] F. Li, Y. Lin, L. He, D. Chen, and J. Cong, Power Modeling and Characteristics of Field Programmable Gate Arrays, IEEE ransaction on Computer-Aided Design of Integrated Circuits and ystems, Vol. 4, No., pp. 7-74, 005. [6]. L. Jung, M. Y. Chang, J. Y. Jyang, L. C. Yeh, and Y. Y. zou, Design and Implementation of an FPGA-Based Control IC for AC-Voltage Regulation, IEEE ransactions on Power Electronics, Vol. 4, No., pp. 5-5, 999. [7]. Hauck, he Roles of FPGAs in Reprogrammable ystems, IEEE Proceeding, Vol. 86, No. 4, pp 65-68, 998. [8] Y. Hu, Y. Cai, and. Rodier, atellite Data Analysis with FPGA Reconfigurable Computation, WEA rans. on ystems, Vol., Issue 5, 004, pp [9] R. Humphrey, D.K. Price, M.R. Bodnar, P.F. Curt, and J.P. Durbano, Generic Arithmetic Units for High-Performance FPGA Designs, WEA rans. on Mathematics, Vol. 6, Issue, 007, pp [0] Lyshevski, Engineering and cientific Computation Using MAALB, New York Wiley, 00. Fig. A. tructure diagram of radix-4 FF core. IN: Issue 7, Volume 8, July 009

10 hu-chen Wang, Chi-Jui Wu, heng-wen Yang Appendix: FF core he FF core used in this paper is given in Fig. A, where the radix-4 type is used. he Fast Fourier ransform (FF) is a computationally efficient algorithm for deriving the Discrete Fourier ransform (DF). he FF core developed by Xilinx can compute an N-point forward DF or inverse DF (IDF) where N m, m 4~4. he FF core applies the Cooley-ukey decimation-in-time (DI) algorithm to determine the DF. It utilizes two radix-4 butterfly-processing engines, and offers continuous data processing using input memory, output memory, and intermediate memory banks. Figure 5 illustrates the structure of a radix-4 FF. When using radix-4, the FF consists of log stages, with each stage including 4 ( N ) N 4 radix-4 butterflies. his core can simultaneously perform transform computations on the current data frame, load the input data for the next data frame, and unload the results of the previous frame of data. All memory is on-chip using either block RAM or distributed RAM. he radix-4 04-point DIF method was adopted to process -channel data. ABLE XIV ome power factor values in Case 4 PFe PFA PFA (%) Matlab FPGA ε (%) Matlab FPGA (%) Matlab FPGA U (% ) en ε ε(%) Error(%) 0.0 Error(%) -0.4 Error(%) IN: Issue 7, Volume 8, July 009