Hi-Speed USB 2.0 Switches with ±15kV ESD MAX4983E/MAX4984E. Features

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1 9-435; Rev 2; 9/8 EVALUATION KIT AVAILABLE Hi-Speed USB 2. Switches General Description The are high ESD-protected analog switches that combine the low on-capacitance and low on-resistance necessary for high-performance switching applications. COM and COM2 are protected against ±5kV ESD without latchup or damage. The devices are ideal for USB 2. Hi-Speed applications at 48Mbps. The switches also handle all the requirements for USB low- and full-speed signaling. The double-pole/double-throw (DPDT) switches are fully specified to operate from a single +2.8V to +5.5V power supply and are protected against a +5.5V short to COM and COM2. This feature makes the fully compliant with the USB 2. specification of VBUS fault protection. The devices feature low-threshold-voltage logic inputs, permitting them to be used with low I/O voltage systems. The MAX4983E features an active-low enable input (EN) that when driven high sets the device in shutdown mode. The features an active-high enable input (EN) that when driven low sets the device in shutdown mode. When the device is in shutdown mode, the quiescent supply current is reduced to.µa. The are available in a spacesaving, -pin,.4mm x.8mm UTQFN package, and operate over a -4 C to +85 C temperature range. Cell Phones PDAs Digital Still Cameras GPS Applications Notebook Computers Video Switching Bus Switches Eye Diagram Features USB Hi-Speed Switching ESD Protection on COM ±5kV Human Body Model ±5kV IEC Air Gap ±8kV IEC Contact Power-Supply Range: +2.8V to +5.5V Low 5Ω (typ) On-Resistance (R ON ) -3dB Bandwidth: 95MHz (typ) Compatible with Logic I/O Down to.4v COM Analog Inputs Fault Protected Against Shorts to +5.5V Low Supply Current.6µA (typ) Enable Input: Active-Low (EN) MAX4983E Active-High (EN) Small -Pin,.4mm x.8mm UTQFN Ordering Information PART PIN-PACKAGE TOP MARK MAX4983EEVB+ Ultra-Thin QFN AAA EVB+ Ultra-Thin QFN AAB Note: All devices operate over the -4 C to +85 C extended temperature range. +Denotes a lead-free package. Pin Configuration MAX4983E TOP VIEW NC2 NO2 EN (EN) COM2 USB 2. Hi-SPEED TRANSMIT TEMPLATE V CC GND COM NC NO UTQFN (EN) FOR ONLY. Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at , or visit Maxim s website at

2 Hi-Speed USB 2. Switches ABSOLUTE MAXIMUM RATINGS (All voltages referenced to GND.) V CC, COM_, NO_, NC_, EN, EN, V to +6.V Continuous Current into Any Terminal... ±3mA Continuous Power Dissipation (T A = +7 C) -Pin UTQFN (derate 6.9mW/ C above +7 C) mW Junction-to-Case Thermal Resistance (θ JC ) (Note ) -Pin UTQFN...2. C/W Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Junction-to-Ambient Thermal Resistance (θ JA ) (Note ) -Pin UTQFN C/W Operating Temperature Range C to +85 C Junction Temperature Range C Storage Temperature Range C to +5 C Lead Temperature (soldering s)...+3 C Note : Package thermal resistances were obtained using the method described in JEDEC specification JESD5-7, using a fourlayer board. For detailed information on package thermal considerations, refer to (V CC = +2.8V to +5.5V, T A = -4 C to +85 C, unless otherwise noted. Typical values are at V CC = +3.V, T A = +25 C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS O p er ati ng P ow er - S up p l y Rang e V CC V V V CC = 3.V.6.5 Supply Current I = V or V CC, CC V EN = V or V EN = V CC VCC = 5.5V Shutdown Supply Current I SHDN Switch disabled (V EN = V CC or V EN = V). µa Increase in Supply Current with V, V EN Voltage Analog Signal Range V V IL or V IH V V CC or V EN V IL or V IH V EN V CC 2 µa V COM, V NO, V NC V EN = V CC or V EN = V (Note 3) V CC V Fault-Protection Trip Threshold V FP COM_ only, T A = +25 C V CC +.6 V CC +.8 V COM = V to V CC 5 On-Resistance R ON V COM = 3.6V, V CC = 3.V 5.5 V C C + µa V Ω On-Resistance Match Between Channels ΔR ON V CC = 3.V, V COM = 2V (Note 4). Ω On-Resistance Flatness R FLAT V CC = 3.V, V COM = V to V CC (Note 5). Ω V CC = 4.5V, V COM = V or 4.5V, V NO, V NC = 4.5V or V Off-Leakage Current I COM() V CC = 5.5V, V COM = V or 5.5V, V NO, V NC with 5µA sink current to GND On-Leakage Current I COM(ON) V CC = 5.5V, V COM = V or 5.5V, V NO, V NC = unconnected AC PERFORMANCE na 8 µa na On-Channel -3dB Bandwidth BW R L = R S = 5Ω, signal = dbm 95 MHz Off-Isolation V ISO R L = R S = 5Ω f = 25MHz -2 V NO, V NC = dbm, f = MHz -48 (Figure ) f = 5MHz -7 db 2

3 Hi-Speed USB 2. Switches ELECTRICAL CHARACTERISTICS (continued) (V CC = +2.8V to +5.5V, T A = -4 C to +85 C, unless otherwise noted. Typical values are at V CC = +3.V, T A = +25 C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Crosstalk (Note 6) V CT R L = R S = 5Ω, f = 25MHz -54 V NO, V NC = dbm, f = MHz -73 Figure f = 5MHz -33 LOGIC INPUT Input Logic-High V IH.4 V Input Logic-Low V IL.5 V Input Leakage Current I IN na DYNAMIC Turn-On Time t ON V N O or V N C =.5V, R L = 3Ω, C L = 35p F, V EN = V C C to V or V E N = V to V C C ( Fi g ur e 2) Turn-Off Time t V N O or V N C =.5V, R L = 3Ω, C L = 35p F, V E N = V C C to V or V EN = V to V C C ( Fi g ur e 2) db 2 µs 5 µs Propagation Delay t PLH, t PHL R L = R S = 5Ω, Figure 3 ps Fault Protection Response Time Fault Protection Recovery Time Output Skew Between Switches NO_ or NC_ Off-Capacitance COM Off-Capacitance (Figure 5, Note 7) COM On-Capacitance (Figure 5, Note 7) Total Harmonic Distortion Plus Noise ESD PROTECTION t FP V COM = V to 5V step, R L = R S = 5Ω, V CC = 3.3V (Figure 4) t FPR V COM = 5V to V step, R L = R S = 5Ω, V CC = 3.3V (Figure 4) t SK S kew b etw een sw i tch and 2, R L = R S = 5Ω, ( Fi g ur e 3, N ote 7).5 5. µs µs 4 ps C NO() or f = MHz (Figure 5, Note 7) 2 pf C NC() f = MHz 5.5 C COM() pf f = 24MHz 4.8 f = MHz 6.5 C COM(ON) f = 24MHz 5.5 THD+N V COM = V P-P, V BIAS = V, R L = R S = 5Ω, f = 2Hz to 2kHz Human Body Model ±5 COM, COM2 IEC Air-Gap Discharge ±5 IEC Contact Discharge ±8 All Pins Human Body Model ±2 pf.3 % Note 2: All devices are % production tested at T A = +25 C. All temperature limits are guaranteed by design. Note 3: The switch turns off for voltages above V FP, protecting downstream circuits in case of a fault condition. Note 4: ΔR ON(MAX) = ABS(R ON(CH) - R ON(CH2) ). Note 5: Flatness is defined as the difference between the maximum and minimum value of on-resistance, as measured over specified analog signal ranges. Note 6: Between any two switches. Note 7: Switch off-capacitance, switch on-capacitance, and output skew between switches are not production tested; guaranteed by design. kv 3

4 Hi-Speed USB 2. Switches V OR V CC 5Ω NC COM NO* SWITCH IS ENABLED. MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT IC TERMINALS. -ISOLATION IS MEASURED BETWEEN COM_ AND "" NO_ OR NC_ TERMINAL ON EACH SWITCH. CROSSTALK IS MEASURED FROM ONE CHANNEL TO THE OTHER CHANNEL. SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WORST VALUES ARE RECORDED. Figure. Off-Isolation and Crosstalk V IN V OUT MEAS 5Ω NETWORK ANALYZER 5Ω Test Circuits/Timing Diagrams 5Ω 5Ω REF -ISOLATION = 2log V OUT V IN CROSSTALK = 2log V OUT V IN *FOR CROSSTALK THIS PIN IS NO2. NC2 AND COM2 ARE OPEN. V IN_ NO OR NC COM V OUT LOGIC INPUT V IH V IL 5% tr < 5ns tf < 5ns EN (EN) R L C L V OUT t LOGIC INPUT SWITCH OUTPUT V t ON.9 x V UT. x V OUT C L INCLUDES FIXTURE AND STRAY CAPACITANCE. R V OUT = V IN_ ( L R L + R ON ) IN DEPENDS ON SWITCH CONFIGURATION; INPUT POLARITY DETERMINED BY SENSE OF SWITCH. Figure 2. Switching Time 4

5 Hi-Speed USB 2. Switches V IN+ V IN+ V IN- V CC V R S R S NC OR NO NC2 OR NO2 5% Test Circuits/Timing Diagrams (continued) COM COM2 V IL TO V IH 5% R L R L V OUT+ V OUT- t INRISE t PLH = t PLHX OR t PLHY t PHL = t PHLX OR t PHLY t SK(O) = t PLHX - t PLHY OR t PHLX - t PHLY t SK(P) = t PLHX - t PHLX OR t PLHY - t PHLY 9% 9% t INFALL % % V CC V IN- 5% 5% V t OUTRISE t OUTFALL t PLHX tphlx V OUT+ V CC V 5% 5% 9% 9% % % V CC V OUT- 5% 5% V t PHLY t PLHY Figure 3. Output Signal Skew, Rise/Fall Time, Propagation Delay 5

6 Hi-Speed USB 2. Switches V CC = 3.3V V COM V NO V NC Figure 4. Fault-Protection Response/Recovery Time V FP t FP Test Circuits/Timing Diagrams (continued) COM t FPR 5V 3V V 3V V CAPACITANCE METER NC_ OR NO_ V IL OR V IH Figure 5. Channel Off-/On-Capacitance 6

7 Hi-Speed USB 2. Switches (V CC = 3.V, T A = +25 C, unless otherwise noted.) QUIESCENT SUPPLY CURRENT (μa) RON (Ω) ON-RESISTANCE vs. V COM V CC = 2.8V V CC = 5.5V V COM (V) QUIESCENT SUPPLY CURRENT vs. TEMPERATURE V CC = 5.5V V CC = 2.8V 4E toc 4E toc4 RON (Ω) QUIESCENT SUPPLY CURRENT (μa) ON-RESISTANCE vs. V COM T A = +85 C T A = +25 C 2 3 V COM (V) Typical Operating Characteristics T A = -4 C QUIESCENT SUPPLY CURRENT vs. LOGIC LEVEL 4E toc2 4E toc5 LEAKAGE CURRENT (na) LOGIC THRESHOLD (V) COM LEAKAGE CURRENT vs. TEMPERATURE COM ON-LEAKAGE COM -LEAKAGE TEMPERATURE ( C) LOGIC-INPUT THRESHOLD vs. SUPPLY VOLTAGE V IH V IL 4E toc3 4E toc TEMPERATURE ( C) 2 3 LOGIC LEVEL (V) SUPPLY VOLTAGE (V) MAGNITUDE (db) FREQUENCY RESPONSE ON-LOSS -ISOLATION CROSSTALK 4E toc7 THD+N (%).. TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY R L = 6Ω 4E toc8-9 -, FREQUENCY (MHz).,,, FREQUENCY (Hz) 7

8 Hi-Speed USB 2. Switches MAX4983E PIN NAME NC Normally Closed Terminal for Switch 2 2 NO Normally Open Terminal for Switch 3 3 COM Common Terminal for Switch 4 4 GND Ground 5 5 COM2 Common Terminal for Switch NO2 Normally Open Terminal for Switch NC2 Normally Closed Terminal for Switch 2 8 EN 8 EN FUNCTION Pin Description Active-Low Enable Input. Drive EN high to put switches in high impedance. Drive EN low for normal operation. Active-High Enable Input. Drive EN low to put switches in high impedance. Drive EN high for normal operation. 9 9 V CC Positive Supply Voltage Input. Bypass V CC to GND with a.µf ceramic capacitor as close as possible to the device. Digital Control Input. Drive low to connect COM_ to NC_. Drive high to connect COM_ to NO_. Detailed Description The are ±5kV ESD-protected DPDT analog switches. The devices are ideal for USB 2. Hi-Speed (48Mbps) switching applications and also meet USB low- and full-speed requirements. The are fully specified to operate from a single +2.8V to +5.5V supply. The low V IH threshold of the devices permits them to be used with logic levels as low as.4v. The are based on a charge-pump-assisted n-channel architecture. The devices feature a shutdown mode to reduce the quiescent current to less than.µa (typ). Digital Control Input The provide a single-bit control logic input,. controls the position of the switches as shown in the Functional Diagram/Truth Table. Driving rail-to-rail minimizes power consumption. With a +2.8V to +5.5V supply voltage range, the device is +.4V logic compatible. Analog Signal Levels The on-resistance of the is very low and stable as the analog input signals are swept from ground to V CC (see the Typical Operating Characteristics). These switches are bidirectional, allowing NO_, NC_, and COM_ to be configured as either inputs or outputs. The charge-pump-assisted n-channel architecture allows the switch to pass analog signals that exceed V CC up to the overvoltage fault protection threshold. This allows USB signals that exceed V CC to pass, allowing compliance with USB requirements for voltage levels. Overvoltage Fault Protection The feature overvoltage fault protection on COM_. Fault protection protects the switch and USB transceiver from damaging voltage levels. When voltages on COM exceed the fault protection threshold, (V FP ), COM_, NC_ and NO_ are high impedance. Enable Input The feature a shutdown mode that reduces the supply current to less than.µa and places COM_ in high impedance. Drive EN high for the MAX4983E or EN low for the to place the devices in shutdown mode. When EN is driven low or EN is driven high, the devices are in normal operation. Applications Information USB Switching The analog switches are fully compliant with the USB 2. specification. The low on-resistance and low on-capacitance of these switches make them ideal for high-performance switching applications. 8

9 Hi-Speed USB 2. Switches The are ideal for routing USB data lines (see Figure 6) and for applications that require switching between multiple USB hosts (see Figure 7). The also feature overvoltage fault protection to guard systems against shorts to the USB VBUS voltage that is required for all USB applications. Extended ESD Protection As with all Maxim devices, ESD-protection structures are incorporated on all pins to protect against electrostatic discharges encountered during handling and assembly. COM and COM2 are further protected against static electricity. The ESD structures withstand high ESD in normal operation and when the device is powered down. After an ESD event, the continue to function without latchup. The MAX4983E and are characterized for protection to the following limits: ±5kV using Human Body Model ±8kV using IEC Contact Discharge method ±5kV using IEC Air-Gap Discharge method ESD Test Conditions ESD performance depends on a variety of conditions. Contact Maxim for a reliability report that documents test setup, test methodology, and test results. Human Body Model Figure 8a shows the Human Body Model and Figure 8b shows the current waveform it generates when discharged into a low impedance. This model consists of a pf capacitor charged to the ESD voltage of interest, which is then discharged into the test device through a.5kω resistor. IEC The main difference between tests done using the Human Body Model and IEC is higher peak current in IEC Because series resistance is lower in the IEC ESD test model (Figure 9a), the ESD-withstand voltage measured to this standard is generally lower than that measured using the Human Body Model. Figure 9b shows the current waveform for the ±8kV IEC Level 4 ESD Contact Discharge test. The Air-Gap Discharge test involves approaching the device with a charged probe. The Contact Discharge method connects the probe to the device before the probe is energized. Layout USB Hi-Speed requires careful P layout with 45Ω controlled-impedance matched traces of equal lengths. Functional Diagram/Truth Table NO NC NO2 NC2 EN EN V CC Ensure that bypass capacitors are as close as possible to the device. Use large ground planes where possible. Power-Supply Sequencing Caution: Do not exceed the absolute maximum ratings because stresses beyond the listed ratings may cause permanent damage to the device. Proper power-supply sequencing is recommended for all devices. Always apply V CC before applying analog signals, especially if the analog signal is not current limited. PROCESS: BiCMOS X X = DON'T CARE. X X = DON'T CARE. GND MAX4983E N_ ON N_ ON NC_ ON NC_ ON EN (EN) COM_ HI-Z COM_ HI-Z COM COM2 Chip Information 9

10 Hi-Speed USB 2. Switches ASIC I HI-SPEED USB TRANSCEIVER ASIC II HI-SPEED USB TRANSCEIVER D+ D- D+ D- NC NO NC2 NO2 COM COM2 Figure 6. USB Data Routing/Typical Application Circuit V BUS D+ D- GND USB CONNECTOR HI-SPEED USB TRANSCEIVER D+ D- COM COM2 NC NO NC2 NO2 Figure 7. Switching Between Multiple USB Hosts D+ D- D+ D- USB HOST I USB HOST II R C MΩ CHARGE-CURRENT- LIMIT RESISTOR R D 5Ω DISCHARGE RESISTANCE AMPERES I P % 9% IR PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE) HIGH- VOLTAGE DC SOURCE Cs pf STORAGE CAPACITOR DEVICE UNDER TEST 36.8% % t RL TIME t DL CURRENT WAVEFORM Figure 8a. Human Body ESD Test Model Figure 8b. Human Body Current Waveform HIGH- VOLTAGE DC SOURCE R C 5MΩ to MΩ CHARGE-CURRENT- LIMIT RESISTOR Cs 5pF R D 33Ω DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST IPEAK I % 9% % t R =.7ns to ns 3ns 6ns t Figure 9a. IEC ESD Test Model Figure 9b. IEC ESD Generator Current Waveform

11 Hi-Speed USB 2. Switches Package Information For the latest package outline information, go to PACKAGE TYPE PACKAGE CODE DOCUMENT NO. Ultra-Thin QFN VACN- 2-28

12 Hi-Speed USB 2. Switches REVISION NUMBER REVISION DATE DESCRIPTION Revision History PAGES CHANGED 2/8 Initial release 5/8 Removal of future product asterisks, global change to Hi-Speed, 8, 9, 2 9/8 Changes to EC table 3 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 2 Maxim Integrated Products, 2 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.