MAX14585/MAX14585A Hi-Speed USB and Audio Switches with Negative Signal Capability and High-Voltage-Tolerable VBUS Detection

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1 ; Rev ; 5/11 E V A L U A T I O N K I T A V A I L A B L E /A General Description The /A high-esd-protected doublepole/double-throw (DPDT) switches multiplex Hi-Speed (48Mbps) USB and analog signals such as AC-coupled audio or video. These devices combine the low oncapacitance (C ON ) and low on-resistance (R ON ) necessary for high-performance switching applications in portable electronics and include an internal negative supply to pass audio signals that swing below ground down to -1.8V. The devices also handle USB low-/full-speed signaling and operate from a 2.7V to 5.5V supply. The devices feature a V BUS detection input (V B ) that can handle voltage up to 28V to automatically switch to the USB signal path upon detection of a valid V BUS signal (V B > V VBDET ). In a dead battery situation, the voltage on V B can supply power to the part if V B is greater than 4.5V. The features internal shunt resistors on the audio path to reduce clicks and pops heard at the output. The /A are available in a spacesaving, 1-pin, 1.4mm x 1.8mm UTQFN package and operate over the -4NC to +85NC temperature range. Cell Phones PDAs and Handheld Devices Tablet PCs Applications Benefits and Features S Low Power Consumption Low Supply Current 7µA (typ) Single 2.7V to 5.5V Supply Operation, S Flexible Design Dual Power-Supply Architecture, V B and ANO_ Channel Override Control Input S High Level of Integration for Performance 28V-Capable V B Input with Automatic UNC_ Selection by V BUS Detection Low-Capacitance Hi-Speed USB for Both Channels (UNC_ and ANO_) Distortion-Free Negative Signal Throughput Down to -1.8V on ANO_ Channel 3I (typ) On-Resistance 96MHz Bandwidth.4% THD+N Audio Channel ±15kV Human Body Model (HBM) ESD on COM1, COM2 S Saves Board Space Internal Shunt Resistor Reduces Clicks and Pops () 1-Pin, 1.4mm x 1.8mm UTQFN Package Ordering Information appears at end of data sheet. For related parts and recommended products to use with this part, refer to Typical Operating Circuit 3.V.1µF HI-SPEED USB TRANSCEIVER AUDIO AMPLIFIER UNC1 UNC2 AN1 AN2 /A INT COM1 COM2 COMBINATION USB AND AUDIO CONNECTOR V BUS V B ONLY V VBDET GND AOR Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at , or visit Maxim s website at

2 ABSOLUTE MAXIMUM RATINGS (Voltages referenced to GND.), AOR...-.3V to +6V V B...-.3V to +3V UNC_, ANO_, COM_ ( R 2.7V) V to min( +.3V, 3.7V) UNC_, COM_ (V B R 4.5V, < 2.7V)...-.3V to +3.7V UNC_, ANO_, COM_ ( < 2.7V)..-.3V to min( +.3V, 3.7V) UNC_, ANO_, COM_ ( = V, V B = V)...-.3V to +6V Continuous Current into Any Pin... Q1mA UTQFN Junction-to-Ambient Thermal Resistance (B JA ) NC/W Junction-to-Case Thermal Resistance (B JC )...2.1NC/W Continuous Power Dissipation (T A = +7NC) UTQFN (derate 7mW/NC above +7NC)...559mW Operating Temperature Range... -4NC to +85NC Junction Temperature Range... -4NC to +15NC Storage Temperature Range NC to +15NC Lead Temperature (soldering, 1s)...+3NC Soldering Temperature (reflow)...+26nc Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PACKAGE THERMAL CHARACTERISTICS (Note 1) Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to ELECTRICAL CHARACTERISTICS (T A = -4NC to +85NC, unless otherwise noted. Typical values are at = 3V, T A = +25NC.) (Note 2) POWER SUPPLY PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Power-Supply Range V Supply Current I SUPPLY = 4.2V, V < V AOR <.4V, V AOR R 1.4V 7 14 FA Power-Supply Rejection Ratio PSRR f = 1kHz, = 3. Q.3V, R COM_ = 5I 1 db V B Detect Threshold V VBDET V BUS rising, R 2.7V V V B Detect Hysteresis V VBDET_H V BUS falling, R 2.7V.2 V V B Detect Leakage Current V B = 5.5V 4 FA ANALOG SWITCH Analog-Signal Range V UNC_ R 2.7V for UNC_ V ANO_, V COM_ R 2.7V for ANO_, COM_ -1.8 ANO_ On-Resistance R ON(NO) = 3V, V ANO_ = -1.5V, +1.5V I COM_ = 1mA UNC_ On-Resistance ANO_ On-Resistance Match Between Channels R ON(NC) DR ON(NO) = 3V, V UNC_ = V to, I COM_ = 1mA V B = 4.5V, = V to 5.5V, V UNC_ = V to 2.5V, V AOR = V, I COM_ = 1mA = 3V, V ANO_ = V, I COM_ = 1mA (Note 3) min(3.6v, ) min(3.6v, ) Maxim Integrated Products 2 V 3 6 I I.2 I

3 ELECTRICAL CHARACTERISTICS (continued) (T A = -4NC to +85NC, unless otherwise noted. Typical values are at = 3V, T A = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS UNC_ On-Resistance Match Between Channels DR ON(NC) = 3V, V UNC_ = V, I COM_ = 1mA (Note 3) ANO_ On-Resistance Flatness R FLAT(NO) = 3V, I COM_ = 1mA, V ANO_ = -1.5V to +1.5V (Note 4) UNC_ On-Resistance Flatness R FLAT(NC) = 3V, I COM_ = 1mA, V UNC_ = V to (Note 4).2 I.4.2 I.4.2 I Shunt Switch Resistance R SH I ANO_ = 2mA, R 2.7V 7 13 I AOR Pulldown Resistor R AOR ki UNC_ Off-Leakage Current I UNC_(OFF) Switch open, V UNC_ = 2.5V, V V COM_ = -1.5V, 2.5V, = 3V ANO_ Off-Leakage Current I ANO_(OFF) A, switch open, V ANO_ = 2.5V, V, V COM_ = V, 2.5V, = 3V COM_ Off-Leakage Current I COM_(OFF) = V, V COM_ = 3.6V, V UNC_ = V ANO_ = unconnected COM_ On-Leakage Current I COM_(ON) USB mode Audio mode = 3V, V ANO_ = V, 2.5V, unconnected, V COM_ = V, 2.5V = 3V, V UNC_ = V, 2.5V, unconnected, V COM_ = -1.5V, 2.5V na na FA na na Turn-On Time t ON ANO_ to COM_, Figure 1 = 3V, V ANO_ = 1.5V, R L = 5I; V AOR = V, V B = V to 5V or V B = 5V, Fs V AOR = V to UNC_ to COM_, Figure 1 = 3V, V UNC_ = 1.5V, R L = 5I; V AOR = V, V B = V to 5V Fs ANO_ from COM_, Figure 1 = 3V, V ANO_ = 1.5V, R L = 5I; V AOR = V, V B = V to 5V 8 4 Fs Turn-Off Time t OFF UNC_ from COM_, Figure 1 = 3V, V UNC_ = 1.5V, R L = 5I; V AOR = V, V B = V to 5V or V B = 5V, 8 4 Fs V AOR = V to Break-Before-Make Time Delay t D R L = 5I, time delay between one side of the switch open and the other side closed 28 Fs Output Skew (Same Switch) t SK(P) Figure 2 4 ps Output Skew Between Switches t SK(O) Figure 2 4 ps ANO_ Off-Capacitance C NO_(OFF) V ANO_ =.5V P-P, DC bias = V, f = 1MHz 2.5 pf UNC_ Off-Capacitance C NC_(OFF) V UNC_ =.5V P-P, DC bias = V, f = 1MHz 2.5 pf Maxim Integrated Products 3

4 ELECTRICAL CHARACTERISTICS (continued) (T A = -4NC to +85NC, unless otherwise noted. Typical values are at = 3V, T A = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS On-Capacitance C COM_(ON) V COM_ =.5V P-P, DC bias = V, f = 24MHz, R L = 5I AC PERFORMANCE 6.7 pf ANO_ -3dB Bandwidth BW NO R S = R L = 5I, V ANO_ = dbm, Figure 3 96 MHz UNC_ -3dB Bandwidth BW NC R S = R L = 5I, V UNC_ = dbm, Figure 3 96 MHz Off-Isolation Crosstalk Total Harmonic Distortion Plus Noise LOGIC INPUT THD+N f = 1kHz, V COM_ = 1V RMS, R L = 5I, Figure 3 f = 1kHz, V COM_ = 1V RMS, R L = 5I, Figure 3 (Note 5) ANO_ to COM_, f = 2Hz to 2kHz, V COM_ =.5V P-P, DC bias = V, R L = 6I -84 db -86 db.42 % AOR Input Logic-High V IH R 2.7V 1.4 V AOR Input Logic-Low V IL R 2.7V.4 V AOR Input Leakage Current I IN V AOR = V or, R 2.7V FA ESD PROTECTION COM1, COM2 Human Body Model IEC Air Gap Discharge IEC Contact Discharge All Other Pins Human Body Model Q2 kv Note 2: All devices are 1% production tested at T A = +25NC. Limits over the operating temperature range are guaranteed by design; not production tested. Note 3: DR ON(MAX) = ABS(R ON(CH1) - R ON(CH2) ). Note 4: Flatness is defined as the difference between the maximum and minimum value of on-resistance, as measured over specified analog-signal ranges. Note 5: Between two switches. Q15 Q8 Q8 kv V IN_ ANO_ OR UNC_ A COM_ V OUT LOGIC INPUT V IH V IL 5% t OFF t R < 5ns t F < 5ns LOGIC INPUT R L CONTROL C L INCLUDES FIXTURE AND STRAY CAPACITANCE. R V OUT = V IN_ ( L R L + R ON ) C L SWITCH OUTPUT V V OUT t ON.9 x V UT.1 x V OUT CONTROL DEPENDS ON SWITCH CONFIGURATION; INPUT POLARITY DETERMINED BY SENSE OF SWITCH. Figure 1. Switching Time Maxim Integrated Products 4

5 V IN+ V IN- R S R S UNC1 OR ANO1 UNC2 OR ANO2 A COM1 COM2 R L V OUT+ V OUT- t PLH = t PLHX OR t PLHY t PHL = t PHLX OR t PHLY t SK(O) = t PLHX - t PLHY OR t PHLX - t PHLY t SK(P) = t PLHX - t PHLX OR t PLHY - t PHLY CONTROL DEPENDS ON SWITCH CONFIGURATION. R L CONTROL V IL TO V IH t INRISE t INFALL V IN+ V 5% 5% 9% 9% 1% 1% V IN- 5% 5% V t OUTRISE t OUTFALL t PLHX tphlx V OUT+ V 5% 5% 9% 9% 1% 1% V OUT- 5% 5% V t PHLY tplhy Figure 2. Output Skew 5Ω UNC1 A COM1 ANO1* V IN V OUT MEAS NETWORK ANALYZER 5Ω 5Ω REF OFF-ISOLATION = 2log V OUT V IN ON-LOSS = 2log V OUT V IN CROSSTALK = 2log V OUT V IN 5Ω 5Ω OFF-ISOLATION IS MEASURED BETWEEN COM_ AND "OFF" ANO_ OR UNC_ TERMINAL ON EACH SWITCH. ON-LOSS IS MEASURED BETWEEN COM_ AND "ON" ANO_ OR UNC_ TERMINAL ON EACH SWITCH. CROSSTALK IS MEASURED FROM ONE CHANNEL TO THE OTHER CHANNEL. *FOR CROSSTALK THIS PIN IS ANO2. UNC2 AND COM2 ARE OPEN. Figure 3. On-Loss, Off-Isolation, and Crosstalk Maxim Integrated Products 5

6 ( = 3.V, T A = +25NC, unless otherwise noted.) Typical Operating Characteristics ON-RESISTANCE (Ω) UNC_ ON-RESISTANCE vs. COM_ VOLTAGE 3.3 I UNC_ = 1mA 3.2 = 2.7V = 5V V COM_ (V) /85A toc1 ON-RESISTANCE (Ω) ANO_ ON-RESISTANCE vs. COM_ VOLTAGE 3.3 I ANO_ = 1mA = 2.7V = 5V V COM_ (V) /85A toc2 ON-RESISTANCE (Ω) UNC_ ON-RESISTANCE vs. COM_ VOLTAGE T A = +85 C T A = +25 C T A = -4 C = 3V I UNC_ = 1mA V COM_ (V) /85A toc3 ON-RESISTANCE (Ω) ANO_ ON-RESISTANCE vs. COM_ VOLTAGE T A = +85 C T A = +25 C T A = -4 C = 3V I ANO_ = 1mA V COM_ (V) /85A toc4 ON-LEAKAGE CURRENT (na) COM_ ON-LEAKAGE CURRENT vs. TEMPERATURE V COM_ = 2.5V TEMPERATURE ( C) /85A toc5 OFF-LEAKAGE CURRENT (µa) COM_ OFF-LEAKAGE CURRENT vs. TEMPERATURE = V V COM_ = 3.6V TEMPERATURE ( C) /85A toc6 SUPPLY CURRENT (µa) SUPPLY CURRENT vs. SUPPLY VOLTAGE T A = +85 C T A = +25 C T A = -4 C /85A toc7 VB CURRENT (µa) V B SUPPLY CURRENT vs. SUPPLY VOLTAGE 7 V AOR = V OR 3V /85A toc8 VB THRESHOLD (V) V B DETECT THRESHOLD vs. TEMPERATURE 3.5 V 3.4 B RISING V 2.9 B FALLING /85A toc SUPPLY VOLTAGE (V) V B VOLTAGE (V) TEMPERATURE ( C) Maxim Integrated Products 6

7 ( = 3.V, T A = +25NC, unless otherwise noted.) Typical Operating Characteristics (continued) TURN-ON TIME (µs) TURN-OFF TIME vs. SUPPLY VOLTAGE TOGGLE V B ANO_ FROM COM_ UNC_ FROM COM_ /85A toc1 TURN-ON TIME (µs) TURN-ON TIME vs. SUPPLY VOLTAGE TOGGLE V B UNC_ TO COM_ ANO_ TO COM_ /85A toc11 MAGNITUDE (db) FREQUENCY RESPONSE ON-LOSS OFF-ISOLATION CROSSTALK /85A toc SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) FREQUENCY (MHz) THD+N (%) TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY 1 R L = 6Ω , 1, FREQUENCY (Hz) /85A toc13 DIFFERENTIAL SIGNAL (V) UNC_ EYE DIAGRAM /85A toc TIME ((x1-9 )s) Maxim Integrated Products 7

8 Pin Configuration TOP VIEW COM2 COM1 AOR V B 9 A 4 GND UNC ANO1 UNC1 ANO2 UTQFN Pin Description PIN NAME FUNCTION 1 UNC1 USB Input 1. Normally closed terminal for switch 1. 2 ANO2 Audio Input 2. Normally open terminal for switch 2. 3 ANO1 Audio Input 1. Normally open terminal for switch 1. 4 GND Ground 5 Positive Supply-Voltage Input. Bypass to GND with a.1ff capacitor as close as possible to the device. 6 COM1 Common Terminal for Switch 1 7 COM2 Common Terminal for Switch 2 8 AOR Audio Override Input. Drive AOR low to have V B control the switch. Drive AOR high to connect COM_ to ANO_. AOR has an internal pulldown resistor to GND. 9 V B V BUS Detection Input. If V B R V VBDET, COM_ connects to UNC_. Otherwise, COM_ connects to ANO_. 1 UNC2 USB Input 2. Normally closed terminal for switch 2. Maxim Integrated Products 8

9 Functional Diagrams/Truth Table UNC1 UNC2 INT COM1 UNC1 UNC2 A INT COM1 ANO1 COM2 ANO1 COM2 ANO2 ANO2 V B V B V VBDET V VBDET GND AOR GND AOR /A V B AOR UNC_ ANO_ ANO_SHUNT > V VBDET ON OFF ON < V VBDET OFF ON OFF X 1 OFF ON OFF X = DON T CARE Detailed Description The /A are high-esd-protected single DPDT switches that operate from a 2.7V to 5.5V supply and are designed to multiplex Hi-Speed USB signals and AC-coupled analog signals. These switches combine the low on-capacitance (C ON ) and low on-resistance (R ON ) necessary for high-performance switching applications. These devices meet the requirements for USB low-speed and full-speed signaling. The negative signal capability of the analog channel allows signals below ground to pass through without distortion. Analog-Signal Levels The devices are bidirectional, allowing ANO_, UNC_, and COM_ to be configured as either inputs or outputs. Note that UNC_ and ANO_ are only protected against ESD up to Q2kV (HBM) and could require additional ESD protection if used as outputs. These devices feature a charge pump that generates a negative supply to allow analog signals as low as -1.8V to pass through ANO_ when supply is greater than 2.7V. This allows AC-coupled signals that drop below ground to pass when operating from a single power supply. Maxim Integrated Products 9

10 When is below 2.7V and V B is less than 4.5V, the switches accept signals from to 3.6V but do not switch according to the Functional Diagrams/Truth Table. V BUS Detection Input The devices feature a V BUS detection input (V B ) that connects COM_ to UNC_ when V B exceeds the V BUS detection threshold (V VBDET ). For applications where V BUS is always present, drive the audio override input (AOR) high to connect ANO_ to COM_ (see the Functional Diagrams/Truth Table). Drive AOR low to have V B control the switch position. Drive AOR rail-to-rail to minimize power consumption. The V B input is capable of handling voltage up to 28V for higher V BUS application. In the case where the main power is lost due to an event such as a dead battery, V B becomes the power supply if V B is greater than 4.5V. Click-and-Pop Suppression () The switched 7I (typ) shunt resistors on the automatically discharge any capacitance at the ANO_ terminals when they are unconnected from COM_. This reduces audio click-and-pop sounds that can occur when switching between USB and audio sources. Applications Information Extended ESD Protection ESD protection structures are incorporated on all pins to protect against electrostatic discharges up to Q2kV (HBM) encountered during handling and assembly. COM1 and COM2 are further protected against ESD up to Q15kV (HBM) without damage. The ESD structures withstand high ESD in both normal operation and when the devices are powered down. After an ESD event, the devices continue to function without latchup. ESD Test Conditions ESD performance depends on a variety of conditions. Contact Maxim for a reliability report that documents test setup, test methodology, and test results. Human Body Model Figure 4 shows the HBM. Figure 5 shows the current waveform it generates when discharged into a lowimpedance state. This model consists of a 1pF capacitor charged to the ESD voltage of interest that is then discharged into the device through a 1.5kI resistor. R C 1MΩ CHARGE-CURRENT- LIMIT RESISTOR R D 15Ω DISCHARGE RESISTANCE AMPERES I P 1% 9% I r PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE) HIGH- VOLTAGE DC SOURCE C s 1pF STORAGE CAPACITOR DEVICE UNDER TEST 36.8% 1% t RL TIME t DL CURRENT WAVEFORM Figure 4. Human Body ESD Test Model Figure 5. Human Body Current Waveform Maxim Integrated Products 1

11 HIGH- VOLTAGE DC SOURCE R C 5MΩ TO 1MΩ CHARGE CURRENT LIMIT RESISTOR C s 15pF R D 33Ω DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST IEC The IEC standard covers ESD testing and performance of finished equipment. It does not specifically refer to integrated circuits. The major difference between tests done using the HBM and IEC is higher peak current in IEC , because series resistance is lower in the IEC model. Hence, the ESD withstand voltage measured to IEC is generally lower than that measured using the HBM. Figure 6 shows the IEC model and Figure 7 shows the current waveform for the Q8kV, IEC , Level 4, ESD Contact-Discharge Method. Figure 6. IEC ESD Test Model I 1% 9% Layout Hi-Speed USB requires careful PCB layout with 45I single-ended/9i differential controlled-impedance matched traces of equal lengths. Ensure that bypass capacitors are as close to the device as possible. Use large ground planes where possible. IPEAK 1% t r =.7ns to 1ns 3ns t 6ns Figure 7. IEC ESD Generator Current Waveform PART Ordering Information/ Selector Guide TOP MARK SHUNT RESISTOR PIN- PACKAGE EVB+T AAY Yes 1 UTQFN AEVB+T AAZ No 1 UTQFN Note: All devices are specified over the -4 C to +85 C temperature range. +Denotes a lead(pb)-free/rohs-compliant package. T = Tape and reel. PROCESS: BiCMOS Chip Information Package Information For the latest package outline information and land patterns (footprints), go to Note that a +, #, or - in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 1 UTQFN V11A1CN Maxim Integrated Products 11

12 Revision History REVISION NUMBER REVISION DATE DESCRIPTION PAGES CHANGED 5/11 Initial release Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 12 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.